ES8707062A1 - Un dispositivo controlador de interconexion - Google Patents

Un dispositivo controlador de interconexion

Info

Publication number
ES8707062A1
ES8707062A1 ES552382A ES552382A ES8707062A1 ES 8707062 A1 ES8707062 A1 ES 8707062A1 ES 552382 A ES552382 A ES 552382A ES 552382 A ES552382 A ES 552382A ES 8707062 A1 ES8707062 A1 ES 8707062A1
Authority
ES
Spain
Prior art keywords
memory
interface
microprocessor
terminal devices
peripheral terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES552382A
Other languages
English (en)
Other versions
ES552382A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES8707062A1 publication Critical patent/ES8707062A1/es
Publication of ES552382A0 publication Critical patent/ES552382A0/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer And Data Communications (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

DISPOSITIVO CONTROLADOR DE INTERCONEXION. COMPRENDE: UN CONTROLADOR DE TRASNPORTE DE DATOS (26) QUE INCLUYE UN CONTROLADOR DE BUS DE COMUNICACION (28), UN MEDIO DE ALMACENAMIENTO (30) Y UN MICROORDENADOR (18) QUE INCLUYE UN MICROPROCESADOR (32) CON UN BUS LOCAL (34) ASOCIADO CON EL AL CUAL SE INTERCONECTAN UNA MEMORIA ROM (38), UNA MEMORIA DE ACCESO ALEATORIO RAM (36) Y UNA PARTE DE PROGRAMA DE SERVICIO LOCAL (40); MEDIOS (12) PARA LA INTERCONEXION CON EL BUS (14); MEDIOS (16) PARA LA INTERCONEXION CON EL MICROPROCESADOR (18); MEDIOS DE ALMACENAMIENTO DE UN PROGRAMA ESPECIFICO DE DISPOSITIVO; Y UN MICROPROCESADOR (24). TIENE APLICACION EN TERMINALES DE ORDENADOR, IMPRESORAS Y SIMILARES.
ES552382A 1985-02-25 1986-02-25 Un dispositivo controlador de interconexion Expired ES8707062A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70545885A 1985-02-25 1985-02-25

Publications (2)

Publication Number Publication Date
ES8707062A1 true ES8707062A1 (es) 1987-07-01
ES552382A0 ES552382A0 (es) 1987-07-01

Family

ID=24833543

Family Applications (1)

Application Number Title Priority Date Filing Date
ES552382A Expired ES8707062A1 (es) 1985-02-25 1986-02-25 Un dispositivo controlador de interconexion

Country Status (6)

Country Link
EP (1) EP0193105A3 (es)
JP (1) JPS61196344A (es)
CN (1) CN1005658B (es)
AU (1) AU581497B2 (es)
ES (1) ES8707062A1 (es)
MX (1) MX161413A (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6719894B2 (ja) * 2015-12-04 2020-07-08 キヤノン株式会社 機能デバイス、制御装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
US4115852A (en) * 1976-12-07 1978-09-19 Harris Data Communications, Inc. Microprogrammed controller
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4556953A (en) * 1982-02-24 1985-12-03 Caprio A Ronald Interchangeable interface circuitry arrangements for use with a data processing system
MX152416A (es) * 1982-02-24 1985-07-10 Digital Equipment Corp Mejoras en estructura de circuito de interfaz intercambiable
JPS5922120A (ja) * 1982-07-28 1984-02-04 Fanuc Ltd システム作成方式

Also Published As

Publication number Publication date
JPS61196344A (ja) 1986-08-30
EP0193105A3 (de) 1990-03-21
EP0193105A2 (de) 1986-09-03
AU5344786A (en) 1986-08-28
CN1005658B (zh) 1989-11-01
AU581497B2 (en) 1989-02-23
ES552382A0 (es) 1987-07-01
MX161413A (es) 1990-09-24
CN85109213A (zh) 1986-08-20

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970203