EP0187159A4 - External interface control circuitry for microcomputer systems. - Google Patents

External interface control circuitry for microcomputer systems.

Info

Publication number
EP0187159A4
EP0187159A4 EP19850903128 EP85903128A EP0187159A4 EP 0187159 A4 EP0187159 A4 EP 0187159A4 EP 19850903128 EP19850903128 EP 19850903128 EP 85903128 A EP85903128 A EP 85903128A EP 0187159 A4 EP0187159 A4 EP 0187159A4
Authority
EP
European Patent Office
Prior art keywords
external device
signal
state
interface
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19850903128
Other languages
German (de)
French (fr)
Other versions
EP0187159A1 (en
Inventor
William Fredrick Pickert
Joseph M Pettinger
Peter Biancalana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0187159A1 publication Critical patent/EP0187159A1/en
Publication of EP0187159A4 publication Critical patent/EP0187159A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Definitions

  • the present invention relates generally to external interface circuitry for data processing systems, and more particularly to a controlled interface for coupling an external device to microcomputer systems.
  • interface circuitry and peripherals have been typically added to such systems by means of buffering interface signals including address, data and control lines.
  • the interface circuitry is powered up when the computer system is switched on.
  • Specialized interfaces such as the RS-232 interface, have also been developed where special devices are required and special data transfer protocols are used.
  • none of these prior art computer systems has a controlled interface which is powered up and powered down in an orderly fashion depending on whether an external device or peripheral is present.
  • the present invention encompasses interface control circuitry for coupling data processing circuitry to an external device.
  • the external device includes circuitry for producing an indication signal when it is coupled to the interface control circuitry and also circuitry for producing a ready signal in response to the application of power to the external device.
  • the interface control circuitry comprises circuitry for applying power to the external device in response to a power control signal; and circuitry for applying interface signals from the data processing circuitry to the external device in response to an interface control signal.
  • the data processing means is responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
  • both power and the interface signals from the data processing circuitry are not applied to the external device until both the external device indication signal indicates that the external device is coupled to the interface control circuitry and the external device produces the ready signal.
  • Figure 1 is a block diagram of an external device ana a microcomputer system embodying the present inven ⁇ tion.
  • Figure 2 is a detailed circuit diagram of the bus control in Figure 1.
  • Figure 3 is a detailed circuit diagram of a typical external device in Figure 1.
  • Figure 4 is a flowchart of the process steps executed by the microcomputer in Figure 1 for controlling an external device.
  • Figure 5 is a timing diagram for selected signals coupled between the microcomputer system and external device in Figure 1.
  • FIG. 1 there is illustrated a data processing system including an external device 800 which is coupled to microcomputer system 100 embodying the present invention.
  • External device 800 may be any of a number of peripheral devices such as, for example, read-only memories, random-access memories, printers, light pens, MODEMS and other data -processing peripherals.
  • Micro ⁇ computer system 100 includes microcomputer 102, bus control 104, peripheral interface adapter 106 and power switch 108.
  • microcomputer 102 is a Motorola , type M6801 single chip microcomputer, although any suitable computer or microcomputer could be utilized in practicing the present invention.
  • Peripheral interface adapter 106 is a Motorola type MC146823 PIA.
  • Power switch 108 is preferably an Intersil type ICL7663 programmable voltage regulator which converts V cc provided by a +7.5V battery down to +V of +5V.
  • Power switch 108 turns on or off in response to the PSC* control signal. Power switch 108 produces a switched +V supply voltage from the V cc supply voltage of the microcomputer system 100.
  • the specific circuitry in bus control 104 is shown in more detail in Figure 2.
  • PIA 106 is coupled to microcomputer 102 by way of address, data and control lines and produces the peripheral disable signal PD* and peripheral control signal PC and receives the ready/interrupt request signal READY*/IRQ* and the peripheral inserted signal PI* from external device 800 by means of buffer gates. Pull up . resistors couple the READY*/IRQ* signal and the PI* signal to corresponding supply voltages for maintaining these signals at preselected voltage states.
  • Bus control 104 there is illustrated a detailed circuit diagram of bus control 104 in Figure 1.
  • Address signals A8-A17, address/data signals AD0-AD7 and control signals AS, E, R/W*, AV*, SDO and SDI from micro ⁇ computer 102 are coupled by bus control 104 to external device 800. All of the signals coupled by a bus control 104 between micrcomputer 102 and external device 800 are gated with the PD* signal such that whenever the external device 800 is disabled, all signals applied by bus control 104 to external device 800 are at a binary zero state. Since the preferred embodiment of bus control 104 is comprised of CMOS devices, it is preferable that all interface signals applied to external device 800 be at a binary zero state for preventing SCR latch-up of the CMOS devices. Moreover, the interface signals are not applied to external device 800 unless the external device 800 is present and has responded to microcomputer system 100 with the READY* signal.
  • address signals A8-A17 are gated with the PD* signal and applied to external device 800 by means of eight gates, one of which is shown in block 202.
  • the address/data signals' AD0-AD7 are also gated with the PD* signal and applied to the external device by way of eight bidirectional gates, one of which is shown in block 206.
  • Address signals present on the AD0-AD7 signals are demultiplexed and stored in latch 204 for application to external device 800 as address signals A0-A7.
  • the control signal for enabling latch 204 is supplied by gate 210, and the control signal for controlling the tri-state buffers in gates 206 is supplied by or gate 208.
  • Interface signals AS, E, R/W* are likewise gated with the PD* signal by gates 212, 213, 214 and 215, respectively and applied to external device 800.
  • Serial interface signals SDO and SDI are coupled by tri-state buffers 222 and 221 , respectively, which are controlled by the PD* signal.
  • the serial interface signals SDO and SDI may be utilized with additional circuitry to provide a serial data interface, such as, for example an RS-232 interface.
  • RAM 302 together with address decode circuits 304 and delay gates 308 may be provided on a printed circuit board which is insertable into a connector of microcomputer system 100.
  • signal PI* is coupled to ground for providing a signal indicating that RAM 302 has been inserted into microcomputer system 100.
  • Delay circuit 308 is coupled to the PC signal and the +V voltage, and may consist of a number of cascaded buffer gates for producing the READY* signal.
  • Address decode circuits 304 may include logic gates which are coupled to address signals A13-A17 and control signals AV* and PC for decoding a particular address assigned to RAM 302.
  • Address signals A0-A12 are applied to the A0-A12 inputs of RAM 302.
  • Data signals AD0-AD7 are applied to data inputs D0-D7 of RAM 302.
  • Control signals R/W* and E are applied to inputs R/W* and CS2 of RAM 302.
  • the control signal E is coupled to inverting gate 306 and applied to input OE* of RAM 302.
  • RAM 302 may be an Hitachi HM6264 type 8KX8 RAM. According to the present invention, RAM 302 is powered up by microcomputer system 100 whenever the microcomputer system requires the use of the memory locations provided thereby. Thus, for example, RAM 302 may be powered up when a particular subroutine requiring a large scratch pad memory is executed by microcomputer 102.
  • RAM 302 need .only be powered up when that particular subroutine is executed. This unique feature of the present invention minimizes current drain from the +V supply, which is typically sourced from a battery.
  • external devices 800 such as printers, read-only memories, telephone line MODEMS, RF MODEMS, light pens, and other data handling apparatus, may be utilized with microcomputer system 100.
  • FIG 4 there is illustrated a detailed flow ⁇ chart of the process steps executed by microcomputer 102 whenever external device 800 is powered up and powered down.
  • the flowchart in Figure 4 is entered at START block 402.
  • decision block 404 a check is made- to see if PI* signal has a binary zero state. If not, NO branch is taken to return. Whenever the PI* signal has a binary one state, an external device has not been inserted into micro ⁇ computer system 100. If the PI* signal has a binary zero state, YES branch is taken to block 410 where the power to the peripheral is turned on by producing a binary zero state of the PSC* signal.
  • a 0.5 second delay is produced to allow time for the external device 800 to turn on and stabilize.
  • a 0.5 second timer is initialized.
  • the READY* signal is checked at decision block 414 to determine if it is a binary zero state. If not, NO branch is taken to decision block 415 where a check is made to determine if the 0.5 second timer has elapsed. If so, YES branch is taken to block 428 where the power is turned off by producing a binary one state of the PSC* signal. Other- wise, NO branch is taken back to decision block 414.
  • READY* signal has a binary zero state
  • YES branch is taken from decision block 414 in Figure 4, to block 416 where the interface signals on the bus between bus control 104 and external device 800 are enabled by producing a binary one state of the PD* signal.
  • a binary one state is produced on the PC signal.
  • the PC signal is used to enable the external device 800.
  • the PC signal is part of the RAM address decoded by address decode circuits 304.
  • a two microsecond timer is initialized.
  • decision block 422 a check is made to see if the READY* signal has a binary one state. If so, YES branch is taken to return indicating that the external device 800 has been properly powered up. If not, NO branch is taken to decision block 423 where a check is made to see if the two microsecond timer has elapsed. If not, NO branch is taken back to decision block 422. Otherwise, YES branch is taken to block 424 for powering down the external device.
  • the READY*/IRQ* signal is treated as an IRQ* signal for interrupting microcomputer 102.
  • the binary state of the IRQ* signal is changed to a binary zero state by external device 800 for requesting service.
  • the IRQ* signal is changed back to a binary one state.
  • blocks 420, 422 and 423 may be bypassed as indicated by dotted line 430.
  • the READY*/IRQ* signal is treated as an immediate request for service if the READY*/IRQ* signal remains at a binary zero state after the PC signal has changed to a binary one state.
  • the external device 800 will change the READY*/IRQ* signal to a binary one state. This unique mode of operation is utilized in the preferred embodiment of the present invention.
  • External device 800 may be powered down whenever it is not needed or whenever the external device does not properly respond to the process steps executed by microcomputer 102 during the power up sequence. In other words, if external device 800 does not properly sequence the binary states of the READY* signal, the external device is powered down. The external device is powered down if YES branch is taken from either decision block 415 or decision block 423. During the power down process, a binary zero state of the PC signal is produced at block 424. Next, at block 426, the bus between bus control 104 and external device 800 is disabled by producing a binary zero state of the PD* signal. Lastly, the power to external device 800 is turned off by producing a binary one state of the PSC* signal at block 428.
  • the external device need not be powered down when not in use but instead only disabled.
  • This mode of operation is provided when microcomputer 102 executes blocks 806, 824 and 826. In this mode, a binary zero state of the PC signal is produced at block 824, and a binary zero state of the PD* signal is produced at block 826. If the external device 800 requires service, the binary state of the READY*/IRQ* signal can be changed to interrupt microcomputer 102. Once interrupted, microcomputer 102 executes the power-up flowchart beginning at START block 402.
  • the flowchart in Figure 4 provides a detailed description of the process steps executed by micro- computer 102 for powering up and powering down external device 800.
  • the coding of the process steps of the flowchart in Figure 4 into the appropriate instructions of a suitable conventional microcomputer is a mere mechanical step for one skilled in the art.
  • the detailed flowcharts in Figure 4 are equivalent to a detailed schematic for an electric circuit where provision of the exact part values for the components of the electrical circuit corresponds to provision of the actual computer instructions for the blocks of the flowchart.
  • Waveform 504 illustrates the PSC* signal which turns on and off power switch 108.
  • PSC* When PSC* has a binary zero state, +V is applied to external device 800 by power switch 108. Before the power up process, a binary zero state is produced by external device 800 on the PI* signal, illustrated by waveform 510. Next, a binary zero state is produced on the PSC* signal. The READY* signal illustrated by waveform 512 then changes from a binary one state to a binary zero state. Next, the PD* signal changes from a binary zero to a binary one state as illustrated Dy waveform 506 for enabling the bus between bus control 104 and external device bOO. The PC signal as illustrated by waveform 508 then changes state from a binary zero state to a binary one state for enabling operation of external device 800.
  • the PC signal changes from a binary one state to a binary zero state, followed by change of the PD* signal from a binary one state to a binary zero state a d lastly, by a change of the PSC* signal from a binary zero state to a binary one state.
  • the changes in binary state of the signals illustrated by the waveforms in Figure 5 take place in the order shown although the time between the changes in binary state may vary depending on actual delays in both the microcomputer system 100 and external device 800.
  • unique interface control circuitry has been described for coupling data processing circuitry to an external device.
  • the external device is powered up and down according to a unique process that insures that the interface circuitry is only powered up when an external device is present and that the state of the interface signals is controlled to prevent destruction of devices in the interface control circuitry.
  • the inter ⁇ face control circuitry of the present invention can be utilized in any application where data processing circuitry interfaces to an external device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Power Sources (AREA)

Abstract

External interface control circuitry that couples a microcomputer system (100) to an external device (800). The control circuitry includes a microcomputer (102), a power switch (108) for applying power to the external device (800) in response to a PSC* signal, bus control (104) for gating interface signals from the microcomputer (102) with a PD* signal for application to the external device (800) and a peripheral interface adapter (106) for producing the PC and PD* signals and coupling the PI* and READY*/IRQ* signals to the microcomputer (102). A power-up sequence is executed by the microcomputer (102) in response to grounding the PI* signal when the external device (800) is plugged into the microcomputer system (100). Next, the external device (800) produces a binary zero state of the READY*/IRQ* signal, and in response microcomputer (102) produces a binary one state of the PD* signal and thereafter the PC signal. The sequence is then completed when the external device (800) returns the READY*/IRQ* signal to the binary one state. The unique power-up process insures that the external device (800) is only powered when present and protects CMOS devices in the interface control circuitry from being inadvertently destroyed.

Description

EXTERNAL INTERFACE CONTROL CIRCUITRY FOR MICROCOMPUTER SYSTEMS
Background of the Invention
The present invention relates generally to external interface circuitry for data processing systems, and more particularly to a controlled interface for coupling an external device to microcomputer systems. In prior art computer systems, interface circuitry and peripherals have been typically added to such systems by means of buffering interface signals including address, data and control lines. In such systems, the interface circuitry is powered up when the computer system is switched on. Specialized interfaces, such as the RS-232 interface, have also been developed where special devices are required and special data transfer protocols are used. However, none of these prior art computer systems has a controlled interface which is powered up and powered down in an orderly fashion depending on whether an external device or peripheral is present.
Objects and Summary of the Invention
Accordingly, it is an object of the present invention to provide improved interface control circuitry for coupling data processing circuitry to an external device. It is the further object of the present invention to provide an improved interface control circuitry that * powers up and down an external device depending on the presence and operating conditions thereof. Briefly described, the present invention encompasses interface control circuitry for coupling data processing circuitry to an external device. The external device includes circuitry for producing an indication signal when it is coupled to the interface control circuitry and also circuitry for producing a ready signal in response to the application of power to the external device. The interface control circuitry comprises circuitry for applying power to the external device in response to a power control signal; and circuitry for applying interface signals from the data processing circuitry to the external device in response to an interface control signal. The data processing means is responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal. Thus, both power and the interface signals from the data processing circuitry are not applied to the external device until both the external device indication signal indicates that the external device is coupled to the interface control circuitry and the external device produces the ready signal.
Brief Description of the Drawings
Figure 1 is a block diagram of an external device ana a microcomputer system embodying the present inven¬ tion. Figure 2 is a detailed circuit diagram of the bus control in Figure 1. Figure 3 is a detailed circuit diagram of a typical external device in Figure 1.
Figure 4 is a flowchart of the process steps executed by the microcomputer in Figure 1 for controlling an external device.
Figure 5 is a timing diagram for selected signals coupled between the microcomputer system and external device in Figure 1.
Detailed Description of the Preferred Embodiment
In Figure 1 there is illustrated a data processing system including an external device 800 which is coupled to microcomputer system 100 embodying the present invention. External device 800 may be any of a number of peripheral devices such as, for example, read-only memories, random-access memories, printers, light pens, MODEMS and other data -processing peripherals. Micro¬ computer system 100 includes microcomputer 102, bus control 104, peripheral interface adapter 106 and power switch 108.
In the preferred embodiment of the present invention, microcomputer 102 is a Motorola, type M6801 single chip microcomputer, although any suitable computer or microcomputer could be utilized in practicing the present invention. Peripheral interface adapter 106 is a Motorola type MC146823 PIA. Power switch 108 is preferably an Intersil type ICL7663 programmable voltage regulator which converts Vcc provided by a +7.5V battery down to +V of +5V.
Power switch 108 turns on or off in response to the PSC* control signal. Power switch 108 produces a switched +V supply voltage from the Vcc supply voltage of the microcomputer system 100. The specific circuitry in bus control 104 is shown in more detail in Figure 2. PIA 106 is coupled to microcomputer 102 by way of address, data and control lines and produces the peripheral disable signal PD* and peripheral control signal PC and receives the ready/interrupt request signal READY*/IRQ* and the peripheral inserted signal PI* from external device 800 by means of buffer gates. Pull up . resistors couple the READY*/IRQ* signal and the PI* signal to corresponding supply voltages for maintaining these signals at preselected voltage states.
Referring next to Figure 2, there is illustrated a detailed circuit diagram of bus control 104 in Figure 1. Address signals A8-A17, address/data signals AD0-AD7 and control signals AS, E, R/W*, AV*, SDO and SDI from micro¬ computer 102 are coupled by bus control 104 to external device 800. All of the signals coupled by a bus control 104 between micrcomputer 102 and external device 800 are gated with the PD* signal such that whenever the external device 800 is disabled, all signals applied by bus control 104 to external device 800 are at a binary zero state. Since the preferred embodiment of bus control 104 is comprised of CMOS devices, it is preferable that all interface signals applied to external device 800 be at a binary zero state for preventing SCR latch-up of the CMOS devices. Moreover, the interface signals are not applied to external device 800 unless the external device 800 is present and has responded to microcomputer system 100 with the READY* signal.
Referring more specifically to Figure 2, address signals A8-A17 are gated with the PD* signal and applied to external device 800 by means of eight gates, one of which is shown in block 202. The address/data signals' AD0-AD7 are also gated with the PD* signal and applied to the external device by way of eight bidirectional gates, one of which is shown in block 206. Address signals present on the AD0-AD7 signals are demultiplexed and stored in latch 204 for application to external device 800 as address signals A0-A7. The control signal for enabling latch 204 is supplied by gate 210, and the control signal for controlling the tri-state buffers in gates 206 is supplied by or gate 208.
Interface signals AS, E, R/W* are likewise gated with the PD* signal by gates 212, 213, 214 and 215, respectively and applied to external device 800. Serial interface signals SDO and SDI are coupled by tri-state buffers 222 and 221 , respectively, which are controlled by the PD* signal. The serial interface signals SDO and SDI may be utilized with additional circuitry to provide a serial data interface, such as, for example an RS-232 interface.
Referring next to Figure 3, there is illustrated a detailed circuit diagram of an external device 800 that includes a random-access memory (RAM) 302. RAM 302 together with address decode circuits 304 and delay gates 308 may be provided on a printed circuit board which is insertable into a connector of microcomputer system 100. When inserted, signal PI* is coupled to ground for providing a signal indicating that RAM 302 has been inserted into microcomputer system 100. Delay circuit 308 is coupled to the PC signal and the +V voltage, and may consist of a number of cascaded buffer gates for producing the READY* signal. Address decode circuits 304 may include logic gates which are coupled to address signals A13-A17 and control signals AV* and PC for decoding a particular address assigned to RAM 302. Address signals A0-A12 are applied to the A0-A12 inputs of RAM 302. Data signals AD0-AD7 are applied to data inputs D0-D7 of RAM 302. Control signals R/W* and E are applied to inputs R/W* and CS2 of RAM 302. In addition, the control signal E is coupled to inverting gate 306 and applied to input OE* of RAM 302. RAM 302 may be an Hitachi HM6264 type 8KX8 RAM. According to the present invention, RAM 302 is powered up by microcomputer system 100 whenever the microcomputer system requires the use of the memory locations provided thereby. Thus, for example, RAM 302 may be powered up when a particular subroutine requiring a large scratch pad memory is executed by microcomputer 102. Since it is desired to conserve current drain from from the +V supply, RAM 302 need .only be powered up when that particular subroutine is executed. This unique feature of the present invention minimizes current drain from the +V supply, which is typically sourced from a battery. Many other types of external devices 800, such as printers, read-only memories, telephone line MODEMS, RF MODEMS, light pens, and other data handling apparatus, may be utilized with microcomputer system 100.
In Figure 4, there is illustrated a detailed flow¬ chart of the process steps executed by microcomputer 102 whenever external device 800 is powered up and powered down. When external device 800 is to be powered up, the flowchart in Figure 4 is entered at START block 402. At decision block 404, a check is made- to see if PI* signal has a binary zero state. If not, NO branch is taken to return. Whenever the PI* signal has a binary one state, an external device has not been inserted into micro¬ computer system 100. If the PI* signal has a binary zero state, YES branch is taken to block 410 where the power to the peripheral is turned on by producing a binary zero state of the PSC* signal. Next, at block 412, a 0.5 second delay is produced to allow time for the external device 800 to turn on and stabilize. Then, at block 413, a 0.5 second timer is initialized. The READY* signal is checked at decision block 414 to determine if it is a binary zero state. If not, NO branch is taken to decision block 415 where a check is made to determine if the 0.5 second timer has elapsed. If so, YES branch is taken to block 428 where the power is turned off by producing a binary one state of the PSC* signal. Other- wise, NO branch is taken back to decision block 414. If the READY* signal has a binary zero state, YES branch is taken from decision block 414 in Figure 4, to block 416 where the interface signals on the bus between bus control 104 and external device 800 are enabled by producing a binary one state of the PD* signal.
Thereafter, at block 418 a binary one state is produced on the PC signal. The PC signal is used to enable the external device 800. In the case of RAM 302 in Figure 3, the PC signal is part of the RAM address decoded by address decode circuits 304. At block 420, a two microsecond timer is initialized. Then, at decision block 422, a check is made to see if the READY* signal has a binary one state. If so, YES branch is taken to return indicating that the external device 800 has been properly powered up. If not, NO branch is taken to decision block 423 where a check is made to see if the two microsecond timer has elapsed. If not, NO branch is taken back to decision block 422. Otherwise, YES branch is taken to block 424 for powering down the external device.
Once external device 800 is properly powered up, the READY*/IRQ* signal is treated as an IRQ* signal for interrupting microcomputer 102. The binary state of the IRQ* signal is changed to a binary zero state by external device 800 for requesting service. Once external device 800 is serviced, the IRQ* signal is changed back to a binary one state.
According to an alternative embodiment of the present invention, blocks 420, 422 and 423 may be bypassed as indicated by dotted line 430. In this mode of operation, the READY*/IRQ* signal is treated as an immediate request for service if the READY*/IRQ* signal remains at a binary zero state after the PC signal has changed to a binary one state. Once serviced, the external device 800 will change the READY*/IRQ* signal to a binary one state. This unique mode of operation is utilized in the preferred embodiment of the present invention.
Whenever external device 800 is to be powered down, blocks 406, 424, 426 and 428 are executed by microcomputer 102. External device 800 may be powered down whenever it is not needed or whenever the external device does not properly respond to the process steps executed by microcomputer 102 during the power up sequence. In other words, if external device 800 does not properly sequence the binary states of the READY* signal, the external device is powered down. The external device is powered down if YES branch is taken from either decision block 415 or decision block 423. During the power down process, a binary zero state of the PC signal is produced at block 424. Next, at block 426, the bus between bus control 104 and external device 800 is disabled by producing a binary zero state of the PD* signal. Lastly, the power to external device 800 is turned off by producing a binary one state of the PSC* signal at block 428.
According to a further feature of the present ■ invention, the external device need not be powered down when not in use but instead only disabled. This mode of operation is provided when microcomputer 102 executes blocks 806, 824 and 826. In this mode, a binary zero state of the PC signal is produced at block 824, and a binary zero state of the PD* signal is produced at block 826. If the external device 800 requires service, the binary state of the READY*/IRQ* signal can be changed to interrupt microcomputer 102. Once interrupted, microcomputer 102 executes the power-up flowchart beginning at START block 402.
The flowchart in Figure 4 provides a detailed description of the process steps executed by micro- computer 102 for powering up and powering down external device 800. The coding of the process steps of the flowchart in Figure 4 into the appropriate instructions of a suitable conventional microcomputer is a mere mechanical step for one skilled in the art. By way of analogy to an electrical circuit diagram, the detailed flowcharts in Figure 4 are equivalent to a detailed schematic for an electric circuit where provision of the exact part values for the components of the electrical circuit corresponds to provision of the actual computer instructions for the blocks of the flowchart. Referring next to Figure 5, there is illustrated a timing diagram of selected control signals coupled between microcomputer system 100 and external device 800. Waveform 504 illustrates the PSC* signal which turns on and off power switch 108. When PSC* has a binary zero state, +V is applied to external device 800 by power switch 108. Before the power up process, a binary zero state is produced by external device 800 on the PI* signal, illustrated by waveform 510. Next, a binary zero state is produced on the PSC* signal. The READY* signal illustrated by waveform 512 then changes from a binary one state to a binary zero state. Next, the PD* signal changes from a binary zero to a binary one state as illustrated Dy waveform 506 for enabling the bus between bus control 104 and external device bOO. The PC signal as illustrated by waveform 508 then changes state from a binary zero state to a binary one state for enabling operation of external device 800. Whenever it is desired to power down external device 800, the PC signal changes from a binary one state to a binary zero state, followed by change of the PD* signal from a binary one state to a binary zero state a d lastly, by a change of the PSC* signal from a binary zero state to a binary one state. The changes in binary state of the signals illustrated by the waveforms in Figure 5 take place in the order shown although the time between the changes in binary state may vary depending on actual delays in both the microcomputer system 100 and external device 800.
In summary, unique interface control circuitry has been described for coupling data processing circuitry to an external device. The external device is powered up and down according to a unique process that insures that the interface circuitry is only powered up when an external device is present and that the state of the interface signals is controlled to prevent destruction of devices in the interface control circuitry. The inter¬ face control circuitry of the present invention can be utilized in any application where data processing circuitry interfaces to an external device.

Claims

Claims
1. Interface control circuitry for coupling processing means interface signals to an external device having means for producing an indication signal when the external device is coupled to said interface circuitry, and means for producing a ready signal in response to the application of power to the external device, said interface control circuitry comprising: means for applying power to the external device in response to a power control signal; means for applying the processing means inter¬ face signals to the external device in response to an interface control signal; and processing means responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
2. The interface control circuitry according to Claim 1 , wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
3. The interface control circuitry according to Claim 1 , wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
4. The interface control circuitry according to Claim 1 , wherein the ready signal producing means of the external device changes the state of the ready signal from a first state to a second state in response to the application of power to the external device and thereafter changes the state of the ready signal from the second state to the first state in response to a device control signal, said processing means being responsive to the change in state of the external device ready signal from the first state to the second state for producing the interface control signal and thereafter producing the device control signal for servicing said external device.
5. The interface control circuitry according to Claim 4, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
6. The interface control circuitry according to Claim 4, wherein said processing means is responsive to the absence of a subsequent change in state of the external device ready signal from the second state to the first state for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
7. The interface control circuitry according to claim 1 , wherein said processing means disables said interface signal applying means when the external device is not being used.
8. The interface control circuitry according to claim 7, wherein said processing means is responsive to changes in state of the external device ready signal for re-enabling said interface signal applying means.
9. The interface control circuitry according to claim 1 , wherein said processing means further is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
10. The interface control circuitry according to claim 1 , wherein said interface signal applying means includes means for combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
11. The interface control circuitry according to claim 1 , wherein said processing means is responsive to subsequent changes in state of the external device ready signal for servicing said external device. 12. A system comprising in combination:
(a) an external device comprising:
(i) means for producing an indication signal indicating that the external device is present; and
(ii) means for producing a ready signal in response to the application of power to the external device;
(b) processing means producing interface signals and being responsive to the external device indication signal for producing a power control signal and responsive to the external device ready signal for producing an interface control signal; and
(c) interface control circuitry for coupling said processing means to said external device, comprising:
(i) means for applying power to the external device in response to the power control signal; and (ii) means for applying the processing means interface signals to the external device in response to the interface control signal.
13. The system according to Claim 12, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
14. The system according to Claim 12, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
15. The system according to Claim 12, wherein the ready signal producing means of the external device changes the state of the ready signal from a first state to a second state in response to the application of power to the external device and thereafter changes the state of the ready signal from the second state to the first state in response to a device control signal, said processing means being responsive to the change in state of the external device ready signal from the first state to the second state for producing the interface control signal and thereafter producing the device control signal for servicing said external device.
16. The system according to Claim 15, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
17. The system according to Claim 15, wherein said processing means is responsive to the absence of a subsequent change in state of the external device ready signal from the second state to the first state for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
18. The system according to claim 12, wherein said processing means disables said interface signal applying means when the external device is not being used.
19. The system according to claim 18, wherein said processing means is responsive to changes in state of the external device ready signal for re-enabling said interface signal applying means.
20. The system according to claim 12, wherein said processing means further is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
21. The system according to claim 12, wherein said interface signal applying means includes means for combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
22. The system according to claim 12, wherein said processing means is responsive to subsequent changes in state of the external device ready signal for servicing said external device. 23. A method for coupling processing means interface signals to an external device having means for producing an indication signal when the external device is coupled to said interface circuitry, and means for producing a ready signal in response to the application of power to the external device, said method comprising the steps of: applying power to the external device in response to a power control signal; applying the processing means interface signals to the external device in response to an interface control signal; producing the power control signal in response to the external device indication signal; and producing the interface control signal in response to the external device ready signal.
24. The method according to Claim 23, further including the step of disabling said power applying means in response to the absence of the external device indication signal, thereby removing power from the
5 external device.
25. The method according to Claim 23, further including the step of disabling said power applying means fc and said interface signal applying means in response to the absence of the external device indication signal, 10 thereby removing power and the processing means interface signals from the external device.
26. The method according to Claim 23, wherein the ready signal producing means of the external device changes the state of the ready signal from a first state
15 to a second state in response to the application of power to the external device and thereafter changes the state of the ready signal from the second state to the first state in response to a device control signal, said interface control signal producing step producing the
20 iriterface control signal in response to the change in state of the external device ready signal from the first state to the second state and thereafter producing the device control signal for servicing said external device.
25 27. The method according to Claim 26, further including the step of disabling said power applying means in response to the absence of the external device indication signal, thereby removing power from the external device.
30 28. The method according to Claim 26, further including the step of disabling said power applying means and said interface signal applying means in response to the absence of a subsequent change in state of the external device ready signal from the second state to the first state, thereby removing power and the processing means interface signals from the external device.
29. The method according to claim 23, further including the step of disabling said interface signal applying means when the external device is not being used.
30. The method according to claim 29, further including the step of re-enabling said interface signal applying means in response to changes in state of the external device ready signal.
31. The method according to claim 23, further including the step of producing a device control signal in response to the external device ready signal, said external device including means responsive to the device control signal for enabling operation thereof.
32. The method according to claim 23, wherein said interface signal applying step includes the step of combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
33. The method according to claim 23, further including the step of servicing said external device in response to subsequent changes in state of the external device ready signal. 34. An external device coupled to processing apparatus interface signals, said processing apparatus interface signals, said processing apparatus applying power to the external device in response to an external device indication signal, applying the processing apparatus interface signals to the external device a predetermined time interval after applying power, and servicing said external device in response to an external device ready signal, said external device comprising: means for producing an indication signal when the external device is present; and means for producing a ready signal in response to the application of power to the external device.
35. The system according to Claim 34, wherein the ready signal producing means of the external device includes means for changing the state of the ready signal from a first state to a second state in response to the application of power to the external device and thereafter changing the state of the ready signal from the second state to the first state in response to a device control signal, said processing apparatus being responsfve to the change in state of the external device ready signal from the first state to the second state for producing the interface control signal and thereafter producing the device control signal for servicing said external device.
36. The external device according to Claim 35, wherein said processing apparatus is responsive to the subsequent absence of the external device indication signal for removing power from the external device.
37. The external device according to Claim 35, wherein said processing apparatus is responsive to the absence of said subsequent change in state of the external device ready signal from the second state to the first state for removing power and the processing apparatus interface signals from the external device.
38. The external device according to Claim 35, wherein said processing apparatus removes the device control signal when the external device is not being serviced.
39. The external device according to Claim 38, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device. 40. The external device according to Claim 34, wherein said processing apparatus removes said interface signals when the external device is not being serviced.
41. The external device according to Claim 40, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying said interface signals and servicing said external device.
42. The external device according to Claim 34, wherein said processing apparatus is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
43. The external device according to Claim 42, wherein said processing apparatus removes the device control signal when the external device is not being serviced.
44. The external device according to Claim 43, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
45. The external device according to Claim 34, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to subsequent changes in state of the external device ready signal for servicing said external device. 46. The interface control circuitry according to Claim 4, wherein said processing means removes the device control signal when the external device is not being serviced.
47. The interface control circuitry according to Claim 46, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing means being responsive to changes in state of the external device ready signal for reapplying thedevice control signal and servicing said external device.
48. The system according to Claim 15, wherein said processing means removes the device control signal when the external device is not being serviced.
49. The system according to Claim 48, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing means being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
50. The method according to Claim 26, wherein said interface control signal producing step includes the step of removing the device control signal when the external device is not being serviced.
51. The method according to Claim 50, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said interface control signal producing step including the step of reapplying the device control signal and servicing said external device in response to changes in state of the external device ready signal.
EP19850903128 1984-06-07 1985-06-05 External interface control circuitry for microcomputer systems. Withdrawn EP0187159A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61811584A 1984-06-07 1984-06-07
US618115 1984-06-07

Publications (2)

Publication Number Publication Date
EP0187159A1 EP0187159A1 (en) 1986-07-16
EP0187159A4 true EP0187159A4 (en) 1986-11-07

Family

ID=24476379

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19850903128 Withdrawn EP0187159A4 (en) 1984-06-07 1985-06-05 External interface control circuitry for microcomputer systems.

Country Status (6)

Country Link
EP (1) EP0187159A4 (en)
JP (1) JPS61502429A (en)
KR (1) KR860700166A (en)
CA (1) CA1233909A (en)
IL (1) IL75374A (en)
WO (1) WO1986000154A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774422A (en) * 1987-05-01 1988-09-27 Digital Equipment Corporation High speed low pin count bus interface
FR2628863B1 (en) * 1988-03-21 1990-08-17 Silicone Sa REMOTE ACTIVATION DEVICE OF A MICROCOMPUTER
JPH03144716A (en) * 1989-10-31 1991-06-20 Toshiba Corp Personal computer
EP0429780B1 (en) * 1989-11-29 1997-11-12 Kabushiki Kaisha Toshiba Computer system capable of connecting an expansion unit
US5241643A (en) * 1990-06-19 1993-08-31 Dell Usa, L.P. Memory system and associated method for disabling address buffers connected to unused simm slots

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2130405A (en) * 1980-08-30 1984-05-31 British Aerospace Electronic calculator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4218740A (en) * 1974-10-30 1980-08-19 Motorola, Inc. Interface adaptor architecture
JPS5335667A (en) * 1976-09-16 1978-04-03 Teijin Seiki Co Ltd Method and device for controlling pressure applying machine
US4213174A (en) * 1977-05-31 1980-07-15 Andover Controls Corporation Programmable sequence controller with drum emulation and improved power-down power-up circuitry
US4161787A (en) * 1977-11-04 1979-07-17 Motorola, Inc. Programmable timer module coupled to microprocessor system
US4266271A (en) * 1978-10-10 1981-05-05 Chamoff Martin E Reconfigurable cluster of data-entry terminals
JPS5731018A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Power supply controlling system
JPS57106924A (en) * 1980-12-24 1982-07-03 Fujitsu Ltd Power source controlling system for input and output equipment
JPS58154026A (en) * 1982-03-08 1983-09-13 Hitachi Ltd Error processing system of information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2130405A (en) * 1980-08-30 1984-05-31 British Aerospace Electronic calculator

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENTS ABSTRACTS OF JAPAN, vol. 6, no. 100 (P-121)[978], 9th June 1982; & JP - A - 57 31 018 (FUJITSU K.K.) 19-02-1982 *
PATENTS ABSTRACTS OF JAPAN, vol. 6, no. 198 (P-147)[1076], 7th October 1982; & JP - A - 57 106 924 (FUJITSU K.K.) 03-07-1982 *
PATENTS ABSTRACTS OF JAPAN, vol. 7, no. 274 (P-241)[1419], 7th December 1983; & JP - A - 58 154 026 (HITACHI SEISAKUSHO K.K.) 13-09-1983 *
See also references of WO8600154A1 *

Also Published As

Publication number Publication date
WO1986000154A1 (en) 1986-01-03
IL75374A0 (en) 1985-09-29
KR860700166A (en) 1986-03-31
CA1233909A (en) 1988-03-08
IL75374A (en) 1989-02-28
EP0187159A1 (en) 1986-07-16
JPS61502429A (en) 1986-10-23

Similar Documents

Publication Publication Date Title
US4794525A (en) External interface control circuitry for microcomputer systems
US5781744A (en) Method and apparatus for ensuring safe peripheral connection
KR100352224B1 (en) Direct memory access(dma) transactions on a low pin count bus
TW370650B (en) System and method for interfacing manually controllable input devices to a universal computer bus system
JPS62160849A (en) Multiple protocol communication adaptor circuit
JPH0157380B2 (en)
JPS62227243A (en) Transmission control system
KR20030031255A (en) Universal serial bus device having logical circuit for conversive and immediate USB Host reset operation
EP0187159A4 (en) External interface control circuitry for microcomputer systems.
US6564279B1 (en) Method and apparatus facilitating insertion and removal of modules in a computer system
EP0172344A2 (en) Power saving system
WO1996008773A3 (en) Pcmcia dma data bus mastering
US6125418A (en) Method and apparatus for enabling a computer user to convert a computer system to an intelligent I/O system
CA2025657A1 (en) Method and apparatus for preventing bus contention problems between two processors
TW372289B (en) Automatic power-on method and apparatus for computer peripherals
EP0354523A3 (en) Remote control for an electronic apparatus with switching power supply
JPS54153541A (en) Control system for interruption priority
JPS59112320A (en) Method for controlling power supply of controlling device
JPS6359613A (en) Automatic power source control system for electric computer
JPH09265448A (en) System for controlling plural integrated circuits by cpu
JPH04140810A (en) Information processor
JPH03225516A (en) Integrated circuit
JPS57111725A (en) Data transmission control system
JPH04107671A (en) Serial data transmitting system
JPH05120201A (en) Data processor

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19860124

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB LI NL SE

A4 Supplementary search report drawn up and despatched

Effective date: 19861107

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19871214

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PETTINGER, JOSEPH, M.

Inventor name: PICKERT, WILLIAM, FREDRICK

Inventor name: BIANCALANA, PETER