JPH09265448A - System for controlling plural integrated circuits by cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load of a CPU and to make it unnecessary prepare I<2> C I/F circuits for all ICs by preparing one IC for receiving I<2> C data from the CPU and transmitting a control signal from the IC to other ICs. SOLUTION: The CPU 12 is connected to a controlling IC 14 through two clock and data serial bus lines 18a, 18b. Thereby an I<2> C data (control signal) from the CPU 12 is received by an I<2> C I/F circuit 16b in the IC 14. The received I<2> C data are temporarily stored in a register 20, read out again and applied to a decoder 22. The I<2> C data are decoded by the decoder 22, and when necessary, the decoded data (control signal) are transmitted to ICs 24a, 24b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a plurality of ICs as a CPU.
System controlled by, for example, consumer VT
In the R or VCR, etc., in the recording or reproducing mode, the CPU controls a plurality of ICs, which temporarily puts all circuits unrelated to the operation into a standby state by the standby signal output from the CPU. Regarding the system.

[0002]

2. Description of the Related Art In a conventional system for controlling a plurality of ICs of this type by a CPU, a so-called I ² which is generally composed of two buses of a serial data line (SDA) and a serial clock line (SCL). The C bus is often used. Then, as shown in FIG.
When the CPU 1 and the system 3 composed of the three ICs 2a, 2b and 2c are connected by the I ² C bus, the system 3 is brought into a standby state (a mode in which the circuit is in a sleep state to reduce power consumption). Has
CPU for each of the three ICs 2a, 2b and 2c
I ² C receiving control signal (standby signal) from 1
I / F (interface) circuits 4a, 4b and 4c are provided, and the respective ICs 2a, 2b and 2c are provided with CPUs.
The standby signal was output from 1.

Further, in the system shown in FIG. 2B, which requires the I ² C bus only when the standby mode is designated, ICs 5a and 5b have I ² C I
Instead of the / F circuit, a dedicated input port for receiving a standby signal from the CPU 1 is provided and the standby signal is directly received from the input port.

[0004]

However, in the former prior art shown in FIG. 2 (A), the standby signal is sent to each of the ICs 2a, 2b and 2c in spite of wanting to make one system 3 stand by. Since the CPU 1 has to output, the load on the software of the CPU 1 becomes large, and the I ² C I / F circuits (4a, 4b and 4c) need to be installed in each IC, which results in a large scale circuit. There was a drawback that the cost was high.

In the latter conventional technique shown in FIG. 2B, the IC 5a and 5b are each provided with an input port for a standby signal, so that I ² C I /
Although the F circuit is not necessary and the ICs 5a and 5b can be simplified, there is a problem that the CPU 1 must be provided with an output port dedicated to standby in addition to the I ² C bus. Also in this system, C
Since the PU1 needs to output the control signal to each of the I ² C and the standby dedicated port, the load on the CPU 1 is heavy.

Therefore, the main object of the present invention is to provide a C
(EN) It is possible to provide a system for controlling a plurality of ICs by a CPU, which can reduce a load on PU software, can be simple and inexpensive, and can output a control signal to the plurality of ICs.

[0007]

According to the present invention, the CPU has two CPUs.
In a system including a first bus interface for a serial bus line of a book, the CPU of which provides control signals such as a standby signal and a reset signal from the first bus interface to the plurality of ICs through the serial bus line, And a second bus interface for two serial bus lines and a decoder for decoding a control signal received by the second bus interface,
A system for controlling a plurality of ICs by a CPU, wherein a control signal decoded by a decoder from one IC to another IC is transmitted through one signal line.

[0008]

A standby signal as a control signal output from the CPU to each IC is given to one of a plurality of ICs from, for example, an I ² C bus interface through an I ² C bus. One such IC includes, for example, an I ² C bus interface similar to a CPU, where the CP
The I ² C data from U is received, and its address, data, etc. are extracted. These received data are stored in the register in bit (or byte) units according to the clock signal. The stored data is decoded by the decoder and then the IC that should receive the control signal
In response, a standby signal designating the standby mode is output. This standby signal allows multiple ICs
Any of the ICs will be in a standby state.

[0009]

According to the present invention, one I from the CPU and the first bus interface through the serial bus line.
It suffices to output the control signal only to C. Therefore, CP
The load on U can be reduced, and it is not necessary to provide a bus interface for all ICs, so that the circuit scale can be reduced and the cost can be reduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, the system 10 of this embodiment.
Is mounted on, for example, a consumer VCR (not shown), and C
Including PU12. The CPU 12 is connected to the control IC 14 by an external data bus or the like. That is, the CPU 12 and the control IC 14 are
As can be seen from the figure, it includes a bus interface, for example, I ² C I / F circuits 16a and 16b, to which two serial bus (I ² C bus) lines 18a for clock (SCL) and data (SDA) and 18b is connected. As a result, 8-bit data (command information) such as a standby signal or a reset signal is sent from the CPU 12 (CPU section 12a) to the control IC 14.
Is transmitted to In other words, I ² C I / as a driver
The command information from the CPU 12 output from the F circuit 16a is received by the I ² CI / F circuit 16b as a receiver.

The I ² C I / F circuit 16 of the control IC 14
b is, CPU 12 receives the instruction information from (CPU unit 12a) (I ² C data) from the I ² C data, monitors the example start condition or address, the I ² C
When the data is data destined for itself, that is, data to be processed by the control IC 14, command data, data count, address, parity, etc. are extracted from the received I ² C data. These data are given to a parity processing circuit (not shown), and the parity is compared there. Then, the comparison result and the command data are given to the register 20 of the control IC 14.

In the register 20, the command data from the CPU 12 is temporarily stored bit by bit or byte in an arbitrary register according to the command data according to the address extracted from the I ² C data. The command data stored in the register 20 is read out again, and the decoder 2
2, the command data is decoded. Then, according to the clock signal from the CPU 12, the decoder 22 outputs command data to each of the ICs 24a and 24b. That is, the decoder 22 is the CPU 1
2 has an output means for transmitting the I ² C data from the IC ² to the IC 24a and the IC 24b, and the data output by this output means has one serial bus line (signal line) 2
6 to IC24a and IC24b. Therefore, IC24a and IC24b are CP
It is controlled according to the command information from U12.

In operation, for example, a VC not shown
When R is set to the recording mode, the CPU 12 controls
Stamps IC24a and 24b against IC14
Mode (a circuit that puts the circuit in a sleep state to reduce power consumption.
Output the standby signal. That is,
Does not work in recording mode, eg ICs 24a and 2
4b, the standby signal is output from the CPU 12.
It is. CPU12 I ^TwoScan from the C I / F circuit 16a
The standby signal is sent to the above-mentioned two serial bus lines 18
I of control IC 14 through a and 18b^TwoC I
It is received by the / F circuit 16b.

The I ² C I / F circuit 16b includes a CPU 12
If the I ² C data (command) from the I ² C data is judged to be the data addressed to itself and it is confirmed that it is the data addressed to itself, the decoder 22 determines based on the command data. , A standby signal for controlling the ICs 24a and 24b, that is, a standby signal is output to the ICs 24a and 24b.

As described above, since the I ² C data from the CPU 12 is transmitted to the plurality of ICs (24a and 24b) via the control IC 14, the CPU 12
Is an instruction (I ² C data) only to the control IC 14.
Should be output. Therefore, the load on the software of the CPU 12 can be reduced. In addition, like the conventional system shown in FIG. 2A, all ICs (2a, 2b)
I ² C I for receiving an I ² C data to and 2c)
It is not necessary to provide the / F circuit (4a, 4b and 4c), and the circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 shows a conventional technique, in which (A) is a CPU and all ICs.
The is a block diagram of a system for connecting with I ² C bus lines, (B) is a block diagram of a system provided with an input port for receiving a dedicated standby signal to all of the IC.

[Explanation of symbols]

10 ... system 12 ... CPU 14 ... control ^{IC 16a, 16b ... I 2 C} I / F circuit 18a, 18b, 26 ... a serial bus line 22 ... decoder 24a, 24b ... IC

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kenichi Kido 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Masahiko Tomikawa 2-chome, Keihan Hondori, Moriguchi City, Osaka Prefecture No. 5-5 Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. A CPU includes a first bus interface for two serial bus lines, and the CPU sends control signals such as a standby signal and a reset signal from the first bus interface to a plurality of ICs through the serial bus line. In the giving system, one of the plurality of ICs is provided with a second bus interface for the two serial bus lines and a decoder for decoding the control signal received by the second bus interface. A system for controlling a plurality of ICs by a CPU, wherein a control signal decoded by the decoder is transmitted to another IC through a single signal line.