CA1233909A - External interface control circuitry for microcomputer systems - Google Patents
External interface control circuitry for microcomputer systemsInfo
- Publication number
- CA1233909A CA1233909A CA000483276A CA483276A CA1233909A CA 1233909 A CA1233909 A CA 1233909A CA 000483276 A CA000483276 A CA 000483276A CA 483276 A CA483276 A CA 483276A CA 1233909 A CA1233909 A CA 1233909A
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- Prior art keywords
- external device
- signal
- state
- interface
- producing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
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- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Power Sources (AREA)
Abstract
EXTERNAL INTERFACE CONTROL CIRCUITRY
FOR MICROCOMPUTER SYSTEMS
Abstract External interface control circuitry is described that couples a microcomputer system (100) to an external device (800). The control circuitry includes a microcomputer (102), a power switch (108) for applying power to the external device (800) in response to a PSC*
signal, bus control (104) for gating interface signals from the microcomputer (102) with a PD* signal for application to the external device (800) and a peripheral interface adapter (106) for producing the PC and PD*
signals and coupling the PI* and READY*/IRQ* signals to the microcomputer (102). A power-up sequence is executed by the microcomputer (102) in response to grounding the PI* signal when the external device (800) is plugged into the microcomputer system (100). Next, the external device (800) produces a binary zero state of the READY*/IRQ* signal, and in response microcomputer (102) produces a binary one state of the PD* signal and thereafter the PC signal. The sequence is then completed when the external device (800) returns the READY*/IRQ*
signal to the binary one state. The unique power-up process insures that the external device (800) is only powered when present and protects CMOS devices in the interface control circuitry from being inadvertently destroyed.
FOR MICROCOMPUTER SYSTEMS
Abstract External interface control circuitry is described that couples a microcomputer system (100) to an external device (800). The control circuitry includes a microcomputer (102), a power switch (108) for applying power to the external device (800) in response to a PSC*
signal, bus control (104) for gating interface signals from the microcomputer (102) with a PD* signal for application to the external device (800) and a peripheral interface adapter (106) for producing the PC and PD*
signals and coupling the PI* and READY*/IRQ* signals to the microcomputer (102). A power-up sequence is executed by the microcomputer (102) in response to grounding the PI* signal when the external device (800) is plugged into the microcomputer system (100). Next, the external device (800) produces a binary zero state of the READY*/IRQ* signal, and in response microcomputer (102) produces a binary one state of the PD* signal and thereafter the PC signal. The sequence is then completed when the external device (800) returns the READY*/IRQ*
signal to the binary one state. The unique power-up process insures that the external device (800) is only powered when present and protects CMOS devices in the interface control circuitry from being inadvertently destroyed.
Description
~,~3~
~XT~L~IAL INT~RFAC~ CONTROL ~'IRCUIT~Y
FOX ~IICROCO~I~UT~R SYSTEMS
B _ round ox the Invention The present invention relates generally to external interface circuitry for data processing systems, and more particularly to a controlled interface for coupling an external device to microcomputer systems.
In prior art computer systems, interface circuitry and peripherals have been typically added to such systems by means ot buffering interface signals including address, data and control lines In such systems, the interface circuitry is powered up when the computer system is switched on. Specialized interfaces, such as che ~S-232 incer~ace, have also been developed where special devices are required and special data transfer protocols are used however, none of these prior art computer systems has a controlled interface which îs powered up and powered down in an orderly fashion depending on whether an external device or peripheral is present.
sects and Summarv of the Invention __._ _ Accordingly, it is an object of the present invention to provide improved interface control circuitry
~XT~L~IAL INT~RFAC~ CONTROL ~'IRCUIT~Y
FOX ~IICROCO~I~UT~R SYSTEMS
B _ round ox the Invention The present invention relates generally to external interface circuitry for data processing systems, and more particularly to a controlled interface for coupling an external device to microcomputer systems.
In prior art computer systems, interface circuitry and peripherals have been typically added to such systems by means ot buffering interface signals including address, data and control lines In such systems, the interface circuitry is powered up when the computer system is switched on. Specialized interfaces, such as che ~S-232 incer~ace, have also been developed where special devices are required and special data transfer protocols are used however, none of these prior art computer systems has a controlled interface which îs powered up and powered down in an orderly fashion depending on whether an external device or peripheral is present.
sects and Summarv of the Invention __._ _ Accordingly, it is an object of the present invention to provide improved interface control circuitry
2~ for coupling data processing circuitry to an external device It is the further object ox the present invention to provide an improved interface control circuitry that powers up and down an external device depending on the presence and operating conditions thereof.
S Briefly described, the present invention encompasses interface control circuitry for coupling data processing circuitry to an external device. The external device includes circuitry for producing an indication signal when it is coupled to the interface control circuitry and also circuitry for producing a ready signal in response to the application of power to the external device. The interface control circuitry comprises circuitry for applying power to the external device in response to a power control signal; and circuitry for applying interface signals prom the data processing circuitry to the external device in response to an interface control signal. The data processing means is responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
Thusl both power and the interface signals from the data processing circuitry are not applied co the external device until both the external device indication signal indicates that the external device is coupled to the ~5 interface control circuitry ana the external device produces the ready signal.
Brief Description of the Drawings inure 1 is a block diagram of an external device an a microcomputer system embodying the present inven-lion ~0 figure 2 is a detailed circuit diagram of the bus control in tune 1.
~3~
Figure 3 is a detailed circuit diagram of a typical external device in Figure lo Figure 4 is a flowchart of the process steps executed by the microcomputer in Figure 1 for controlling an external device.
igure 5 is a timing diagram for selected slgnals coupled between the microcomputer system and external device in figure 1.
retailed Description of the Preferred Embodiment In Figure 1 there is illustrated a data processing system including an external device ~00 which is coupled to microcomputer system 100 embodying the present invention, external device ~0 may be any of a number of peripheral devices such as, for example, read only memories, random-access memories, printers, light pens IIODE~I~ and other data processing perlpherals. Hero computer system 100 includes microcomputer 10~, bus control 104, peripheral interface adapter 106 and power switch 108.
In the preferred embodiment of the present invention, microcomputer 102 is a Llotorola type il68Ul single chip microcomputer, aithough any suitable computer or microcomputer could be utilized in practicing the present invention. Peripheral interface adapter 106 is a ~lotorola type tlCl 46823 PIA. Power switch 10~ is preferably an Intersil type ICL7663 programmable voltage re~ulacor which converts Vcc provided by a +7.5V
bactery flown to -TV of +5V.
Power switch 1~8 turns on or off in response to the P~C* control signal Power switch 10~ produces a swicched +V supply voltage from the Vcc supply voltage of the microCOMpUter systern 100. The speciric circuicry in bus control 104 is shown in Gore detail in ~'igure I. PIA 106 is coupled to microcomputer 1~2 by way ~L2~3~
of address, data and control lines and produces the peripheral disable signal PD* and peripheral control signal PC and receives the ready/interrupt request signal READY*/IR~* and the peripheral inserted signal PI* from external device 800 by means of buffer gates. Pull up resis-tors couple the READY*/IRQ* signal and the PI*
signal -to corresponding supply voltages for maintaining these signals at preselected voltage states.
Referring next to Figure 2, there is illustrated a detailed circuit diagram of bus control 104 in Figure 1.
Address signals A8-A17, address/data signals AD0-AD7 and control signals AS, E, R/W*, AV*, SD0 and SDI from micro-computer 102 are coupled by bus control 104 to external device 800. All of the signals coupled by a Gus control 104 between microcomputer 102 and external device 800 are gated with the PD* signal such that whenever the ex-ternal device 800 is disabled, all signals applied by bus control 104 to external device 800 are at a binary zero state Since the preferred embodiment of bus control 104 is comprised of CMOS devices, it is preferable that all interface signals applied to external device 800 be at a binary zero state for preventing SCR latch-up of the CMOS
devices. Moreovex, the interface signals are not applied to external dev.ice 800 unless the external device 800 is present and has responded to microcomputer system 100 with the READY* signal.
Referring more specifi.cally to Fi.gure 2, address siynals A8-A17 are gated with the PD* signal and applied to ex-ternal device 800 by means of eight gates, one of which is shown in block 202. The address/data signals AD0-AD7 are also gated with th.e PD* signal and applied to the external device by way oE eight bidirectional gates, one ox which is shown in block 206. Address signals present on the AD0-AD7 signals are demultiplexed and storecl in latch 20~ for application -to external device 800 as address signals A0-A7. The control signal or ~L'f~33~
enabling latch 204 is supplied by gate 210, and the control signal for controlling the tri-state buffers in gates 206 is supplied by or yate 2Q8.
In-terface signals AS, En R/W* and AV are likewise 5 yated with the PD* signal by gates 212, 213, 214 and 215, respectively and applied to external device 800. Serial interface siynals S~0 and SDI are coupled by tri-state buf:~ers 222 and 221, xespectively, which are controlled by the PD* siynal. The serial interface signals SD0 and SDI may be utilized with additional circuitry to provide serial data interface, such as, for example an RS-232 interface.
Referring next to Figure 3, there is illustrated a detailed circuit diagram of an external device 800 that includes a random-access memory (RAM 302. R~ 302 together with address decode circuits 304 and delay gates 308 may be provided on a printed circuit board which is insertable into a connector ox microcomputer system 100.
When inserted, signal PI* is coupled to ground for providing a signal indicating that 302 has teen inserted into microcomputer system 100. Delay circuit 308 is coupled to~the PC signal and the +V voltage, and may consist of a number of cascaded buffer gates for producing the READY* signal. address decode circuits 304 may include logic gates which are coupled to address signals A13-A17 and control signals AV* and PC for decoding a particular address assigned to R~ 302.
Address signals A0-A12 are applied to the A0-A12 inputs oE RAM 302. Data signals AD0-AD7 are applied to data inputs D0-D7 of Al 302. Control signals R/W* and E are applied to inputs R/W* and CS2 of RAM 302. In addition the control signal E is coupled to inverting gate 306 and applied to input OE* of RUM 302. RAM 302 may be an Hitachi HM6264 type 8KX8 JAM.
According to the present invention, JAM 302 is powered up by microcomputer system 100 whenever the microcomputer system requires the use of the memory a3 locations provided thcreby. Thus, for example, KA~I 302 may be powered up when a particular subroutine requiring a large scratch pad memory is executed by microcomputer 102. Since it is desired to conserve current drain from from the +V supply, RAM 302 need only be powered up when that particular subroutine is executed. This unique feature of the present invention minimizes current drain from the TV supply, which is typically sourced from a battery. ~1any other types of external devices ~0, such as printers, read-only memories, telephone line ~1~D~Is, RF ~1ODE~Is, light pens, and other data handling apparatus, may be utilized with microcomputer system 100.
In Figure 4, there is illustrated a detailed flow-chart of the process steps executed by microcomputer 102 whenever external device 800 is powered up and powered down. ~Jhen external device ~00 is to be powered up, the flowchart in ~`igure 4 is entered at START block 402. At decision block 404, a check is maae to see if PI* signal has a binary zero state. If not, JO branch is taken to return. ~ihenever the I* signal has a binary one state, an external device has not been inserted into micro-computer system 100. If the I* signal has a binary zero state, YES branch is taken to Dlock 41~ where che power co the peripheral is turned on by producing a binary zero ~5 state of the ~S~* signal. Nexc, at block 412, a 0.5 second delay is produced to allow time for the external device 800 to turn on and stabilize. Then, at block 413, a 0.5 second timer is initialized. l'he LADY* signal is checked at decision block 414 to determine if it is a binary zero state. If not, RIO branch is taken co decision block 415 where a check is made to determine ir the 0.5 second timer has elapsed. Ir so, YES branch is taken to block 4~ where the power is turned off by producing a binary one state ox the ~S~* signal. Other-wise, branch is taken back to decision block 414.
~33~
If the READY* signal has a binary 2ero state, YESbranch is taken from decision block 414 in Figure 4, to block 416 where the interface signals on the bus between bus control 104 and external device 800 are enabled by producing a binary one state of the PD* signal.
Thereafter, at block 41~ a binary one state is produced on the O signal The PC signal is used to enable the external device ~0~. In the case of KAM 3~ in ~'igure 3, the O signal is part of the ~A~I address aecoded by address decode circuits 304. At block 420, a two microsecond timer is initialized. Then, at decision block 422, a check is made to see if the RAY signal has a binary one state. If so, YES branch is taken to return indicating that the external device 800 has been properly powered up. If not, JO branch is taken to decision block 423 where a check is made to see if the two microsecond timer has elapsed. If not, NO branch is taken back to decision block 422. Otherwise, YES branch is taken to block 424 for powering down the external device.
Once external device 8~0 is properly powered up, the R~A~Y*/IRQ* signal is treated as an IRK* signal for interrupting microcomputer 1~2. The binary state of the IRQ* signal is changed to a binary zero state by external device 8~0 for requesting service. Once external device 800 is serviced, the IKQ* signal is changed back to a binary one state.
Accoraing to an alternative embodiment of the present invention, blocks 420, 422 and 423 may be bypassed as indicated by dotter line 4~. In chis mode ot operation, the R~ADY*/IR~* signal is treated as an immediate request or service if the R~ADY~/L~* signal remains at a binary Nero state after the O signal has changed Jo a binary one state. Gnce serviced, the external device ~00 wiLl change the R~ADY*/IR(~* signal to a binary one stave. 'l'his unique mode of operation is ~3~
utilized in the preferred embodiment of the present invention.
Whenever external device 800 is to be powered down, blocks 406, 4~4, 426 and 4~ are executed by S microcomputer 102. External device 800 may be powered down whenever it is not needed or whenever the external device does not properly respona to the process steps executed by microcomputer 102 during the power up sequence. In other words, if external device 800 does not properly sequence the binary states of the READY* signal, the external device is powered down. The external device is powered down if YES branch is taken from either decision block 415 or decision block 423. During the power down process, a binary zero state of the PC signal is produced at block 4~4. text, at block 426, the bus between bus control 104 and external device 800 is disabled by producing a cinary zero state of the PD*
signal. Lastly, the power to external device ~00 is turned of by producing a binary one state of the O
signal at block 4~8.
According to a further feature of the present invention, the external device need not be powered down when not in use but instead only disabled. This moae of operacion is provided when microcompucer 102 executes Dlocks 806, 824 and 826~ In chis lode, a binary zero state of the PC signal is produced at block 824, ana a binary zero state of the Pi* signal is produced at block ~26. If the external device 800 requires service, the binary state of the R~A~Y*/IRQ* signal can be changea co interrupt microcomputer 1~2. once interrupced, microcompucer 102 executes the power-up rlowch~rc be~innin~ at 8TA~T block 4U2.
The flowchart in Figure 4 provides a detailea descripcion of the process steps executed by ulicro-computer 1~2 ior powering up and powering down external device ~00. The coding of tile process steps of the ~33~
flowchart in Figure 4 into the appropriate instructionsof a suitable conventional microcomputer is a mere mechanical step for one skilled in the art. By way of analogy to an electrical circuit diagram, the detailed flowcharts in Figure 4 are equivalent to a detailed schematic for an electric circuit where provision of the exact part values for the components of the electrical circuit corresponds to provision of the actual computer instructions for the blocks of the flowchart.
Referring next to Figure 5, there is illustrated a tirning diagram of selected control signals coupled between microcomputer system 100 and external device ~00.
waveform 504 illustrates the PSC* signal which turns on and off power switch 108. then YSC* has a binary zero state, +V is applied to external device ~00 by power switch 108. Before the power up process, a binary zero state is produced by external device ~00 on the PI*
signal, illustrated by waveform 510. Next, a binary zero state is produced on the SO signal. The READY* signal illustrated by waveform 512 then changes from a binary one state to a binary zero state. Next, the YD* signal changes fron1 a binary zero to a binary one state as illustratea Dy waveform 506 Lor enabling the bus between bus control 104 and external device ~0~. The Ye signal as illustrated by waveform SUP then changes state from a binary zero state to a binary one state for enabling operation vf external device ~00. Iihenever it is desired to power down external device ~00, the Y0` signal changes from a binary one state to a binary zero state, followed my change of the Pi* signal frorn a binary one state co a binary zero scate and lastly, by a change of the YS~*
signal prom a binary zero state to a binary one state.
The changes in binary stave of the signals illustrated by the waveforms in figure 5 take place in the order shown ~5 although the time between the changes in binary state may l o vary depending on actual delays in both the microcomputer system 100 and external device ~00.
In sun~ary, unique interface control circuitry has been described for coupling data processing circuitry to an external device The external device is powered up and down according to a unique process that insures that the interface circuitry is only powered up when an external device is present and that the state of the interface sigrla1s is controlled to prevent destruction of clevices in the interface control circuitry. The inter-face control circuitry of the present invention can be utilizecl in any application where data processing circuitry interfaces to an external aevice.
S Briefly described, the present invention encompasses interface control circuitry for coupling data processing circuitry to an external device. The external device includes circuitry for producing an indication signal when it is coupled to the interface control circuitry and also circuitry for producing a ready signal in response to the application of power to the external device. The interface control circuitry comprises circuitry for applying power to the external device in response to a power control signal; and circuitry for applying interface signals prom the data processing circuitry to the external device in response to an interface control signal. The data processing means is responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
Thusl both power and the interface signals from the data processing circuitry are not applied co the external device until both the external device indication signal indicates that the external device is coupled to the ~5 interface control circuitry ana the external device produces the ready signal.
Brief Description of the Drawings inure 1 is a block diagram of an external device an a microcomputer system embodying the present inven-lion ~0 figure 2 is a detailed circuit diagram of the bus control in tune 1.
~3~
Figure 3 is a detailed circuit diagram of a typical external device in Figure lo Figure 4 is a flowchart of the process steps executed by the microcomputer in Figure 1 for controlling an external device.
igure 5 is a timing diagram for selected slgnals coupled between the microcomputer system and external device in figure 1.
retailed Description of the Preferred Embodiment In Figure 1 there is illustrated a data processing system including an external device ~00 which is coupled to microcomputer system 100 embodying the present invention, external device ~0 may be any of a number of peripheral devices such as, for example, read only memories, random-access memories, printers, light pens IIODE~I~ and other data processing perlpherals. Hero computer system 100 includes microcomputer 10~, bus control 104, peripheral interface adapter 106 and power switch 108.
In the preferred embodiment of the present invention, microcomputer 102 is a Llotorola type il68Ul single chip microcomputer, aithough any suitable computer or microcomputer could be utilized in practicing the present invention. Peripheral interface adapter 106 is a ~lotorola type tlCl 46823 PIA. Power switch 10~ is preferably an Intersil type ICL7663 programmable voltage re~ulacor which converts Vcc provided by a +7.5V
bactery flown to -TV of +5V.
Power switch 1~8 turns on or off in response to the P~C* control signal Power switch 10~ produces a swicched +V supply voltage from the Vcc supply voltage of the microCOMpUter systern 100. The speciric circuicry in bus control 104 is shown in Gore detail in ~'igure I. PIA 106 is coupled to microcomputer 1~2 by way ~L2~3~
of address, data and control lines and produces the peripheral disable signal PD* and peripheral control signal PC and receives the ready/interrupt request signal READY*/IR~* and the peripheral inserted signal PI* from external device 800 by means of buffer gates. Pull up resis-tors couple the READY*/IRQ* signal and the PI*
signal -to corresponding supply voltages for maintaining these signals at preselected voltage states.
Referring next to Figure 2, there is illustrated a detailed circuit diagram of bus control 104 in Figure 1.
Address signals A8-A17, address/data signals AD0-AD7 and control signals AS, E, R/W*, AV*, SD0 and SDI from micro-computer 102 are coupled by bus control 104 to external device 800. All of the signals coupled by a Gus control 104 between microcomputer 102 and external device 800 are gated with the PD* signal such that whenever the ex-ternal device 800 is disabled, all signals applied by bus control 104 to external device 800 are at a binary zero state Since the preferred embodiment of bus control 104 is comprised of CMOS devices, it is preferable that all interface signals applied to external device 800 be at a binary zero state for preventing SCR latch-up of the CMOS
devices. Moreovex, the interface signals are not applied to external dev.ice 800 unless the external device 800 is present and has responded to microcomputer system 100 with the READY* signal.
Referring more specifi.cally to Fi.gure 2, address siynals A8-A17 are gated with the PD* signal and applied to ex-ternal device 800 by means of eight gates, one of which is shown in block 202. The address/data signals AD0-AD7 are also gated with th.e PD* signal and applied to the external device by way oE eight bidirectional gates, one ox which is shown in block 206. Address signals present on the AD0-AD7 signals are demultiplexed and storecl in latch 20~ for application -to external device 800 as address signals A0-A7. The control signal or ~L'f~33~
enabling latch 204 is supplied by gate 210, and the control signal for controlling the tri-state buffers in gates 206 is supplied by or yate 2Q8.
In-terface signals AS, En R/W* and AV are likewise 5 yated with the PD* signal by gates 212, 213, 214 and 215, respectively and applied to external device 800. Serial interface siynals S~0 and SDI are coupled by tri-state buf:~ers 222 and 221, xespectively, which are controlled by the PD* siynal. The serial interface signals SD0 and SDI may be utilized with additional circuitry to provide serial data interface, such as, for example an RS-232 interface.
Referring next to Figure 3, there is illustrated a detailed circuit diagram of an external device 800 that includes a random-access memory (RAM 302. R~ 302 together with address decode circuits 304 and delay gates 308 may be provided on a printed circuit board which is insertable into a connector ox microcomputer system 100.
When inserted, signal PI* is coupled to ground for providing a signal indicating that 302 has teen inserted into microcomputer system 100. Delay circuit 308 is coupled to~the PC signal and the +V voltage, and may consist of a number of cascaded buffer gates for producing the READY* signal. address decode circuits 304 may include logic gates which are coupled to address signals A13-A17 and control signals AV* and PC for decoding a particular address assigned to R~ 302.
Address signals A0-A12 are applied to the A0-A12 inputs oE RAM 302. Data signals AD0-AD7 are applied to data inputs D0-D7 of Al 302. Control signals R/W* and E are applied to inputs R/W* and CS2 of RAM 302. In addition the control signal E is coupled to inverting gate 306 and applied to input OE* of RUM 302. RAM 302 may be an Hitachi HM6264 type 8KX8 JAM.
According to the present invention, JAM 302 is powered up by microcomputer system 100 whenever the microcomputer system requires the use of the memory a3 locations provided thcreby. Thus, for example, KA~I 302 may be powered up when a particular subroutine requiring a large scratch pad memory is executed by microcomputer 102. Since it is desired to conserve current drain from from the +V supply, RAM 302 need only be powered up when that particular subroutine is executed. This unique feature of the present invention minimizes current drain from the TV supply, which is typically sourced from a battery. ~1any other types of external devices ~0, such as printers, read-only memories, telephone line ~1~D~Is, RF ~1ODE~Is, light pens, and other data handling apparatus, may be utilized with microcomputer system 100.
In Figure 4, there is illustrated a detailed flow-chart of the process steps executed by microcomputer 102 whenever external device 800 is powered up and powered down. ~Jhen external device ~00 is to be powered up, the flowchart in ~`igure 4 is entered at START block 402. At decision block 404, a check is maae to see if PI* signal has a binary zero state. If not, JO branch is taken to return. ~ihenever the I* signal has a binary one state, an external device has not been inserted into micro-computer system 100. If the I* signal has a binary zero state, YES branch is taken to Dlock 41~ where che power co the peripheral is turned on by producing a binary zero ~5 state of the ~S~* signal. Nexc, at block 412, a 0.5 second delay is produced to allow time for the external device 800 to turn on and stabilize. Then, at block 413, a 0.5 second timer is initialized. l'he LADY* signal is checked at decision block 414 to determine if it is a binary zero state. If not, RIO branch is taken co decision block 415 where a check is made to determine ir the 0.5 second timer has elapsed. Ir so, YES branch is taken to block 4~ where the power is turned off by producing a binary one state ox the ~S~* signal. Other-wise, branch is taken back to decision block 414.
~33~
If the READY* signal has a binary 2ero state, YESbranch is taken from decision block 414 in Figure 4, to block 416 where the interface signals on the bus between bus control 104 and external device 800 are enabled by producing a binary one state of the PD* signal.
Thereafter, at block 41~ a binary one state is produced on the O signal The PC signal is used to enable the external device ~0~. In the case of KAM 3~ in ~'igure 3, the O signal is part of the ~A~I address aecoded by address decode circuits 304. At block 420, a two microsecond timer is initialized. Then, at decision block 422, a check is made to see if the RAY signal has a binary one state. If so, YES branch is taken to return indicating that the external device 800 has been properly powered up. If not, JO branch is taken to decision block 423 where a check is made to see if the two microsecond timer has elapsed. If not, NO branch is taken back to decision block 422. Otherwise, YES branch is taken to block 424 for powering down the external device.
Once external device 8~0 is properly powered up, the R~A~Y*/IRQ* signal is treated as an IRK* signal for interrupting microcomputer 1~2. The binary state of the IRQ* signal is changed to a binary zero state by external device 8~0 for requesting service. Once external device 800 is serviced, the IKQ* signal is changed back to a binary one state.
Accoraing to an alternative embodiment of the present invention, blocks 420, 422 and 423 may be bypassed as indicated by dotter line 4~. In chis mode ot operation, the R~ADY*/IR~* signal is treated as an immediate request or service if the R~ADY~/L~* signal remains at a binary Nero state after the O signal has changed Jo a binary one state. Gnce serviced, the external device ~00 wiLl change the R~ADY*/IR(~* signal to a binary one stave. 'l'his unique mode of operation is ~3~
utilized in the preferred embodiment of the present invention.
Whenever external device 800 is to be powered down, blocks 406, 4~4, 426 and 4~ are executed by S microcomputer 102. External device 800 may be powered down whenever it is not needed or whenever the external device does not properly respona to the process steps executed by microcomputer 102 during the power up sequence. In other words, if external device 800 does not properly sequence the binary states of the READY* signal, the external device is powered down. The external device is powered down if YES branch is taken from either decision block 415 or decision block 423. During the power down process, a binary zero state of the PC signal is produced at block 4~4. text, at block 426, the bus between bus control 104 and external device 800 is disabled by producing a cinary zero state of the PD*
signal. Lastly, the power to external device ~00 is turned of by producing a binary one state of the O
signal at block 4~8.
According to a further feature of the present invention, the external device need not be powered down when not in use but instead only disabled. This moae of operacion is provided when microcompucer 102 executes Dlocks 806, 824 and 826~ In chis lode, a binary zero state of the PC signal is produced at block 824, ana a binary zero state of the Pi* signal is produced at block ~26. If the external device 800 requires service, the binary state of the R~A~Y*/IRQ* signal can be changea co interrupt microcomputer 1~2. once interrupced, microcompucer 102 executes the power-up rlowch~rc be~innin~ at 8TA~T block 4U2.
The flowchart in Figure 4 provides a detailea descripcion of the process steps executed by ulicro-computer 1~2 ior powering up and powering down external device ~00. The coding of tile process steps of the ~33~
flowchart in Figure 4 into the appropriate instructionsof a suitable conventional microcomputer is a mere mechanical step for one skilled in the art. By way of analogy to an electrical circuit diagram, the detailed flowcharts in Figure 4 are equivalent to a detailed schematic for an electric circuit where provision of the exact part values for the components of the electrical circuit corresponds to provision of the actual computer instructions for the blocks of the flowchart.
Referring next to Figure 5, there is illustrated a tirning diagram of selected control signals coupled between microcomputer system 100 and external device ~00.
waveform 504 illustrates the PSC* signal which turns on and off power switch 108. then YSC* has a binary zero state, +V is applied to external device ~00 by power switch 108. Before the power up process, a binary zero state is produced by external device ~00 on the PI*
signal, illustrated by waveform 510. Next, a binary zero state is produced on the SO signal. The READY* signal illustrated by waveform 512 then changes from a binary one state to a binary zero state. Next, the YD* signal changes fron1 a binary zero to a binary one state as illustratea Dy waveform 506 Lor enabling the bus between bus control 104 and external device ~0~. The Ye signal as illustrated by waveform SUP then changes state from a binary zero state to a binary one state for enabling operation vf external device ~00. Iihenever it is desired to power down external device ~00, the Y0` signal changes from a binary one state to a binary zero state, followed my change of the Pi* signal frorn a binary one state co a binary zero scate and lastly, by a change of the YS~*
signal prom a binary zero state to a binary one state.
The changes in binary stave of the signals illustrated by the waveforms in figure 5 take place in the order shown ~5 although the time between the changes in binary state may l o vary depending on actual delays in both the microcomputer system 100 and external device ~00.
In sun~ary, unique interface control circuitry has been described for coupling data processing circuitry to an external device The external device is powered up and down according to a unique process that insures that the interface circuitry is only powered up when an external device is present and that the state of the interface sigrla1s is controlled to prevent destruction of clevices in the interface control circuitry. The inter-face control circuitry of the present invention can be utilizecl in any application where data processing circuitry interfaces to an external aevice.
Claims (51)
1. Interface control circuitry for coupling processing means interface signals to an external device having means for producing an indication signal when the external device is coupled to said interface circuitry, and means for producing a ready signal in response to the application of power to the external device, said interface control circuitry comprising:
means for applying power to the external device in response to a power control signal;
means for applying the processing means interface signals to the external device only in response to an interface control signal; and processing means for producing the processing means interface signals and being responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
means for applying power to the external device in response to a power control signal;
means for applying the processing means interface signals to the external device only in response to an interface control signal; and processing means for producing the processing means interface signals and being responsive to the external device indication signal for producing the power control signal and responsive to the external device ready signal for producing the interface control signal.
2. The interface control circuitry according to claim 1, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
3. The interface control circuitry according to claim 1, wherein said processing means is responsive to the absence of the external device indication signal and ready signal for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
4. The interface control circuitry according to claim 1, wherein the ready signal producing means of the external device changes the state of the ready signal from a first state to a second state in response to the application of power to the external device and a predetermined time interval thereafter changes the state of the ready signal from the second state to the first state in response to a device control signal, said processing means being responsive to the change in state of the external device ready signal from the first state to the second state for producing the interface control signal and a predetermined time interval thereafter producing the device control signal for servicing said external device.
5. The interface control circuitry according to claim 4, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
6. The interface control circuitry according to claim 4, wherein said processing means is responsive to the absence of a subsequent change in state of the external device ready signal from the second state to the first state for disabling said power applying means, thereby removing power from the external device.
7. The interface control circuitry according to claim 1, wherein said processing means disables said interface signal applying means when the external device is not being used.
8. The interface control circuitry according to claim 7, wherein said processing means is responsive to changes in state of the external device ready signal for re-enabling said interface signal applying means.
9. The interface control circuitry according to claim 1, wherein said processing means further is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
10. The interface control circuitry according to claim 1, wherein said interface signal applying means includes means for combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
11. The interface control circuitry according to claim 1, wherein said processing means is responsive to subsequent changes in state of the external device ready signal for servicing said external device.
12. A system comprising in combination:
(a) an external device comprising:
(i) means for producing an indication signal indicating that the external device is present; and (ii) means for producing a ready signal in response to the application of power to the external device;
(b) processing means producing interface signals and being responsive to the external device indication signal for producing a power control signal and responsive to the external device ready signal for producing an interface control signal; and (c) interface control circuitry for coupling said processing means to said external device, comprising:
(i) means for applying power to the external device in response to the power control signal; and (ii) means for applying the processing means interface signals to the external device only in response to the interface control signal.
(a) an external device comprising:
(i) means for producing an indication signal indicating that the external device is present; and (ii) means for producing a ready signal in response to the application of power to the external device;
(b) processing means producing interface signals and being responsive to the external device indication signal for producing a power control signal and responsive to the external device ready signal for producing an interface control signal; and (c) interface control circuitry for coupling said processing means to said external device, comprising:
(i) means for applying power to the external device in response to the power control signal; and (ii) means for applying the processing means interface signals to the external device only in response to the interface control signal.
13. The system according to claim 12, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
14. The system according to claim 12, wherein said processing means is responsive to the absence of the external device indication signal and ready signal for disabling said power applying means and said interface signal applying means, thereby removing power and the processing means interface signals from the external device.
15. The system according to claim 12, wherein the ready signal producing means of the external device changes the state of the ready signal from a first state to a second state in response to the application of power to the external device and a predetermined time interval thereafter changes the state of the ready signal from the second state to the first state in response to the first state in response to a device control signal, and processing means being responsive to the change in state of the external device ready signal from the first state to the second state for producing the interface control signal and a predetermined time interval thereafter producing the device control signal for servicing said external device.
16. The system according to claim 15, wherein said processing means is responsive to the absence of the external device indication signal for disabling said power applying means, thereby removing power from the external device.
17. The system according to claim 15, wherein said processing means is responsive to the absence of a subsequent change in state of the external device ready signal from the second state to the first state for disabling said power applying means, thereby removing power from the external device.
18. The system according to claim 12, wherein said processing means disables said interface signal applying means when the external device is not being used.
19. The system according to claim 18, wherein said processing means is responsive to changes in state of the external device ready signal for re-enabling said interface signal applying means,
20. The system according to claim 12, wherein said processing means further is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
21. The system according to claim 12, wherein said interface signal applying means includes means for combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
22. The system according to claim 12, wherein said processing means is responsive to subsequent changes in state of -the external device ready signal for servicing said external device.
23. A method for coupling processing means interface signals to an external device having means for producing an indication signal when the external device is coupled to said interface circuitry, and means for producing a ready signal in response to the application of power to the external device, said method comprising the steps of:
applying power to the external device in response to a power control signal;
applying the processing means interface signals to the external device only in response to an interface control signal;
producing the power control signal in response to the external device indication signal; and producing the interface control signal in response to the external device ready signal.
applying power to the external device in response to a power control signal;
applying the processing means interface signals to the external device only in response to an interface control signal;
producing the power control signal in response to the external device indication signal; and producing the interface control signal in response to the external device ready signal.
24. The method according to claim 23, further including the step of removing power in response to the absence of the external device indication signal,
25. The method according to claim 23, further including the step of removing power and the processing means interface signals from the external device in response to the absence of the external device indication signal and ready signal.
26, The method according to claim 23, wherein the ready signal producing means of the external device changes the state of the ready signal from a first state to a second state in response to the application of power to the external device and a predetermined time interval thereafter changes the state of the ready signal from the second state to the first state in response to a device control signal said interface control signal producing step producing the interface control signal in response to the change in state of the external device ready signal from the first state to the second state a predetermined time interval and thereafter producing the device control signal for servicing said external device.
27, The method according to claim 26, further including the step of removing power from the external device in response to the absence of the external device indication signal.
28. The method according to claim 26, further including the step of removing power from the external device in response to the absence of changing the state of the external device ready signal from the second state to the first state.
29. The method according to claim 23, further including the step of removing the processing means interface signals from the external device when the external device is not being used.
30. The method according to claim 29, further including the step of reapplying the processing means interface signals to the external device in response to changes in state of the external device ready signal.
31. The method according to claim 23, further including the step of producing a device control signal in response to the external device ready signal, said external device including means responsive to the device control signal for enabling operation thereof.
32. The method according to claim 23, wherein said interface signal applying step includes the step of combining the processing means interface signals and the interface control signal to produce combined signals for application to the external device.
33. The method according to claim 23, further including the step of servicing said external device in response to subsequent changes in state of the external device ready signal.
34. An external device coupled to processing apparatus interface signals produced by processing apparatus, said processing apparatus applying power to the external device in response to an external device indication signal, applying the processing apparatus interface signals to the external device a predetermined time interval after applying power, and servicing said external device in response to an external device ready signal, said external device comprising:
means for producing an indication signal when the external device is present; and means for producing a ready signal in response to the application of power to the external device.
means for producing an indication signal when the external device is present; and means for producing a ready signal in response to the application of power to the external device.
35. The system according to claim 34, wherein the ready signal producing means of the external device includes means for changing the state of the ready signal from a first state to a second state in response to the application of power to the external device and a predetermined time interval thereafter changing the state of the ready signal from the second state to the first state in response to a device control signal, said processing apparatus being responsive to the change in state of the external device ready signal from the first state to the second state for producing the device control signal for servicing said external device.
36. The system according to claim 35, wherein said processing apparatus is responsive to the subsequent absence of the external device indication signal for removing power from the external device.
37, The system according to claim 35, wherein said processing apparatus is responsive to the absence of changing the state of the external device ready signal from the second state to the first state for removing the processing apparatus interface signals from the external device.
38. The system according to claim 35, wherein said processing apparatus removes the device control signal when the external device is not being serviced.
39. The system according to claim 38, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
40. The system according to claim 34, wherein said processing apparatus removes said interface signals when the external device is not being serviced.
41. The system according to claim 40, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying said interface signals and servicing said external device.
42. The system according to claim 34, wherein said processing apparatus is responsive to the external device ready signal for producing a device control signal, said external device including means responsive to the device control signal for enabling operation thereof.
43. The system according to claim 42, wherein said processing apparatus removes the device control signal when the external device is not being serviced.
44. The system according to claim 43, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
45. The system according to claim 34, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing apparatus being responsive to subsequent changes in state of the external device ready signal for servicing said external device.
46. The interface control circuitry according to claim 4, wherein said processing means removes the device control signal when the external device is not being serviced.
47. The interface control circuitry according to claim 46, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing means being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
48. The system according to claim 15, wherein said processing means removes the device control signal when the external device is not being serviced.
49. The system according to claim 48, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said processing means being responsive to changes in state of the external device ready signal for reapplying the device control signal and servicing said external device.
50. The method according to claim 26, wherein said interface control signal producing step includes the step of removing the device control signal when the external device is not being serviced.
51. The method according to claim 50, wherein said ready signal producing means includes means for changing the state of the ready signal to request service, said interface control signal producing step including the step of reapplying the device control signal and servicing said external device in response to changes in state of the external device ready signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US61811584A | 1984-06-07 | 1984-06-07 | |
| US618,115 | 1984-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1233909A true CA1233909A (en) | 1988-03-08 |
Family
ID=24476379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000483276A Expired CA1233909A (en) | 1984-06-07 | 1985-06-06 | External interface control circuitry for microcomputer systems |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0187159A4 (en) |
| JP (1) | JPS61502429A (en) |
| KR (1) | KR860700166A (en) |
| CA (1) | CA1233909A (en) |
| IL (1) | IL75374A (en) |
| WO (1) | WO1986000154A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4774422A (en) * | 1987-05-01 | 1988-09-27 | Digital Equipment Corporation | High speed low pin count bus interface |
| FR2628863B1 (en) * | 1988-03-21 | 1990-08-17 | Silicone Sa | REMOTE ACTIVATION DEVICE OF A MICROCOMPUTER |
| JPH03144716A (en) * | 1989-10-31 | 1991-06-20 | Toshiba Corp | Personal computer |
| DE69031705T2 (en) * | 1989-11-29 | 1998-04-02 | Toshiba Kawasaki Kk | Computer system suitable for connecting an expansion unit |
| US5241643A (en) * | 1990-06-19 | 1993-08-31 | Dell Usa, L.P. | Memory system and associated method for disabling address buffers connected to unused simm slots |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4218740A (en) * | 1974-10-30 | 1980-08-19 | Motorola, Inc. | Interface adaptor architecture |
| JPS5335667A (en) * | 1976-09-16 | 1978-04-03 | Teijin Seiki Co Ltd | Method and device for controlling pressure applying machine |
| US4213174A (en) * | 1977-05-31 | 1980-07-15 | Andover Controls Corporation | Programmable sequence controller with drum emulation and improved power-down power-up circuitry |
| US4161787A (en) * | 1977-11-04 | 1979-07-17 | Motorola, Inc. | Programmable timer module coupled to microprocessor system |
| US4266271A (en) * | 1978-10-10 | 1981-05-05 | Chamoff Martin E | Reconfigurable cluster of data-entry terminals |
| JPS5731018A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Power supply controlling system |
| GB2130405B (en) * | 1980-08-30 | 1984-11-21 | British Aerospace | Electronic calculator |
| JPS57106924A (en) * | 1980-12-24 | 1982-07-03 | Fujitsu Ltd | Power source controlling system for input and output equipment |
| JPS58154026A (en) * | 1982-03-08 | 1983-09-13 | Hitachi Ltd | Error processing system of information processor |
-
1985
- 1985-05-31 IL IL75374A patent/IL75374A/en unknown
- 1985-06-05 KR KR1019860700075A patent/KR860700166A/en not_active Application Discontinuation
- 1985-06-05 WO PCT/US1985/001061 patent/WO1986000154A1/en not_active Application Discontinuation
- 1985-06-05 JP JP60502710A patent/JPS61502429A/en active Pending
- 1985-06-05 EP EP19850903128 patent/EP0187159A4/en not_active Withdrawn
- 1985-06-06 CA CA000483276A patent/CA1233909A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61502429A (en) | 1986-10-23 |
| EP0187159A4 (en) | 1986-11-07 |
| IL75374A (en) | 1989-02-28 |
| IL75374A0 (en) | 1985-09-29 |
| EP0187159A1 (en) | 1986-07-16 |
| WO1986000154A1 (en) | 1986-01-03 |
| KR860700166A (en) | 1986-03-31 |
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