ES8305534A1 - Procedimiento de pasivacion de dispositivos semiconductores. - Google Patents

Procedimiento de pasivacion de dispositivos semiconductores.

Info

Publication number
ES8305534A1
ES8305534A1 ES514071A ES514071A ES8305534A1 ES 8305534 A1 ES8305534 A1 ES 8305534A1 ES 514071 A ES514071 A ES 514071A ES 514071 A ES514071 A ES 514071A ES 8305534 A1 ES8305534 A1 ES 8305534A1
Authority
ES
Spain
Prior art keywords
semiconductor device
moat
laser beam
device passivation
moved relative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES514071A
Other languages
English (en)
Other versions
ES514071A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Mobility Ltd
Original Assignee
Westinghouse Brake and Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westinghouse Brake and Signal Co Ltd filed Critical Westinghouse Brake and Signal Co Ltd
Publication of ES8305534A1 publication Critical patent/ES8305534A1/es
Publication of ES514071A0 publication Critical patent/ES514071A0/es
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Dicing (AREA)
  • Bipolar Transistors (AREA)

Abstract

PROCEDIMIENTO DE PASIVACION DE DISPOSITIVOS SEMICONDUCTORES. SE FORMA UNA RANURA ADYACENTE AL PERIMETRO DE LA REACCION ACTIVA DEL DISPOSITIVO HACIENDO UN CORTE POR MEDIO DE UN RAYO LASER QUE INCIDE EN ANGULO OBLICUO CON RESPECTO A LA SUPERFICIE DE DICHA REGION ACTIVA. SE ENSANCHA LA RANURA MEDIANTE MORDENTADO QUIMICO Y SE RECUBRE CON MATERIAL DIELECTRICO DE PASIVACION EN PELICULA DEPOSITADA A BAJA PRESION. DE APLICACION A PLACAS SEMICONDUCTORAS SOBRE LAS QUE SE FORMAN SIMULTANEAMENTE UNA PLURALIDAD DE DISPOSITIVOS Y EN DISPOSITIVOS DE VOLTAJE ELEVADO.
ES514071A 1981-07-17 1982-07-16 Procedimiento de pasivacion de dispositivos semiconductores. Granted ES514071A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8122176 1981-07-17

Publications (2)

Publication Number Publication Date
ES8305534A1 true ES8305534A1 (es) 1983-04-01
ES514071A0 ES514071A0 (es) 1983-04-01

Family

ID=10523336

Family Applications (1)

Application Number Title Priority Date Filing Date
ES514071A Granted ES514071A0 (es) 1981-07-17 1982-07-16 Procedimiento de pasivacion de dispositivos semiconductores.

Country Status (4)

Country Link
EP (1) EP0070692A3 (es)
JP (1) JPS58121673A (es)
ES (1) ES514071A0 (es)
GB (1) GB2102202A (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU570309B2 (en) * 1984-03-26 1988-03-10 Unisearch Limited Buried contact solar cell
FR2579023B1 (fr) * 1985-03-12 1988-06-24 Silicium Semiconducteur Ssc Composant semiconducteur a tenue en tension amelioree par sillons peripheriques multiples
US4748103A (en) * 1986-03-21 1988-05-31 Advanced Power Technology Mask-surrogate semiconductor process employing dopant protective region
US4962057A (en) * 1988-10-13 1990-10-09 Xerox Corporation Method of in situ photo induced evaporation enhancement of compound thin films during or after epitaxial growth
DE4114660C2 (de) * 1991-05-06 1997-09-18 Telefunken Microelectron Verfahren zur Herstellung glaspassivierter Halbleiterbauelemente
EP1601010A3 (fr) 2004-05-26 2009-01-21 St Microelectronics S.A. Formation de tranchées obliques

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3559006A (en) * 1968-04-11 1971-01-26 Tokyo Shibaura Electric Co Semiconductor device with an inclined inwardly extending groove
US4019248A (en) * 1974-06-04 1977-04-26 Texas Instruments Incorporated High voltage junction semiconductor device fabrication

Also Published As

Publication number Publication date
EP0070692A2 (en) 1983-01-26
ES514071A0 (es) 1983-04-01
JPS58121673A (ja) 1983-07-20
GB2102202A (en) 1983-01-26
EP0070692A3 (en) 1984-11-07

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