ES486103A1 - Un sistema de tratamiento de datos - Google Patents
Un sistema de tratamiento de datosInfo
- Publication number
- ES486103A1 ES486103A1 ES486103A ES486103A ES486103A1 ES 486103 A1 ES486103 A1 ES 486103A1 ES 486103 A ES486103 A ES 486103A ES 486103 A ES486103 A ES 486103A ES 486103 A1 ES486103 A1 ES 486103A1
- Authority
- ES
- Spain
- Prior art keywords
- stack
- data processing
- processing system
- machine architecture
- register machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30163—Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
Un sistema de tratamiento de datos para realizar operaciones sobre una pluralidad de datos, que comprende una memoria, un archivo de registros para fines generales que tiene una pluralidad de elementos, una memoria de columna que tiene una posición superior, y un registro de instrucciones para almacenar un primer y un segundo operandos, cada uno de los cuales incluye una parte de dirección para asignar una dirección de cada uno de dichos datos y un código de operación para designar una operación a realizar; caracterizado porque dicho sistema de tratamiento de datos incluye adicionalmente primeros medios para, hacer corresponder dicha posición superior de la columna al menos a uno de dichos elementos en el archivo de registros para fines generales, y segundos medios para controlar el funcionamiento de dicha memoria de columna, con lo cual, cuando es asignado por dicha parte de dirección dicho elemento al cual se hace corresponder dicha posición superior de la columna, dicha posición superiorde la columna es seleccionada por dichos primeros medios y el funcionamiento de dicha memoria de columna está controlado por dichos segundos medios.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14310178A JPS5569855A (en) | 1978-11-20 | 1978-11-20 | Data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
ES486103A1 true ES486103A1 (es) | 1980-06-16 |
Family
ID=15330925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES486103A Expired ES486103A1 (es) | 1978-11-20 | 1979-11-19 | Un sistema de tratamiento de datos |
Country Status (6)
Country | Link |
---|---|
US (1) | US4334269A (es) |
EP (1) | EP0011442B1 (es) |
JP (1) | JPS5569855A (es) |
CA (1) | CA1116755A (es) |
DE (1) | DE2965636D1 (es) |
ES (1) | ES486103A1 (es) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57166649A (en) * | 1981-03-30 | 1982-10-14 | Ibm | Data processing system |
JPS5880740A (ja) * | 1981-11-09 | 1983-05-14 | Nec Corp | マイクロプログラム制御装置 |
JPH0619710B2 (ja) * | 1983-12-20 | 1994-03-16 | 日本電気株式会社 | レジスタ制御方式 |
US5179734A (en) * | 1984-03-02 | 1993-01-12 | Texas Instruments Incorporated | Threaded interpretive data processor |
GB8602964D0 (en) * | 1986-02-06 | 1986-03-12 | Metaforth Computer Systems Ltd | Computer architecture |
US5042004A (en) * | 1986-03-06 | 1991-08-20 | Advanced Micro Devices, Inc. | Programmable logic device with subroutine stack and random access memory |
US5161217A (en) * | 1986-10-14 | 1992-11-03 | Bull Hn Information Systems Inc. | Buffered address stack register with parallel input registers and overflow protection |
EP0386151B1 (en) * | 1987-11-10 | 1996-06-19 | Echelon Corporation | Multiprocessor intelligent cell for a network |
US5034882A (en) * | 1987-11-10 | 1991-07-23 | Echelon Corporation | Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control |
US5321823A (en) * | 1988-07-20 | 1994-06-14 | Digital Equipment Corporation | Digital processor with bit mask for counting registers for fast register saves |
US5023828A (en) * | 1988-07-20 | 1991-06-11 | Digital Equipment Corporation | Microinstruction addressing in high-speed CPU |
US5107457A (en) * | 1989-04-03 | 1992-04-21 | The Johns Hopkins University | Stack data cache having a stack management hardware with internal and external stack pointers and buffers for handling underflow and overflow stack |
US5179691A (en) * | 1989-04-12 | 1993-01-12 | Unisys Corporation | N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M |
US5696957A (en) * | 1991-05-17 | 1997-12-09 | Ricoh Company, Ltd | Integrated circuit comprising a central processing unit for executing a plurality of programs |
JPH0527970A (ja) * | 1991-07-18 | 1993-02-05 | Seikosha Co Ltd | 演算装置 |
JP3110866B2 (ja) * | 1992-06-01 | 2000-11-20 | 株式会社東芝 | マイクロプロセッサ |
US5765014A (en) * | 1993-10-12 | 1998-06-09 | Seki; Hajime | Electronic computer system and processor element for processing in a data driven manner using reverse polish notation |
US6009508A (en) * | 1994-06-21 | 1999-12-28 | Sgs-Thomson Microelectronics Limited | System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis |
WO1996008767A2 (en) * | 1994-09-16 | 1996-03-21 | Philips Electronics N.V. | Microcontroller system with a multiple-register stacking instruction |
JP3493369B2 (ja) * | 1994-12-13 | 2004-02-03 | 株式会社ルネサステクノロジ | コンピュータ |
US5940859A (en) * | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
US6792523B1 (en) * | 1995-12-19 | 2004-09-14 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |
JP3801643B2 (ja) * | 1996-01-24 | 2006-07-26 | サン・マイクロシステムズ・インコーポレイテッド | スタックを用いる演算マシンのための命令フォールディング処理 |
US6332215B1 (en) * | 1998-12-08 | 2001-12-18 | Nazomi Communications, Inc. | Java virtual machine hardware for RISC and CISC processors |
US20050149694A1 (en) * | 1998-12-08 | 2005-07-07 | Mukesh Patel | Java hardware accelerator using microcode engine |
DE19933130A1 (de) * | 1999-07-19 | 2001-01-25 | Giesecke & Devrient Gmbh | Operandenstapelspeicher und Verfahren zum Betreiben eines Operandenstapelspeichers |
EP1197847A3 (en) * | 2000-10-10 | 2003-05-21 | Nazomi Communications Inc. | Java hardware accelerator using microcode engine |
TW591405B (en) * | 2002-04-19 | 2004-06-11 | Ind Tech Res Inst | Non-copy shared stack and register set device and dual language processor structure using the same |
WO2003091972A1 (en) * | 2002-04-26 | 2003-11-06 | Telefonaktiebolaget Lm Ericsson | Memory access register file |
US7203820B2 (en) * | 2002-06-28 | 2007-04-10 | Sun Microsystems, Inc. | Extending a register file utilizing stack and queue techniques |
US7680990B2 (en) * | 2003-05-30 | 2010-03-16 | Hewlett-Packard Development Company, L.P. | Superword memory-access instructions for data processor |
DE10329680A1 (de) * | 2003-07-01 | 2005-02-10 | Universität Stuttgart | Prozessorarchitektur für exakte Zeigeridentifizierung |
US20070061551A1 (en) * | 2005-09-13 | 2007-03-15 | Freescale Semiconductor, Inc. | Computer Processor Architecture Comprising Operand Stack and Addressable Registers |
JP7221008B2 (ja) | 2018-08-09 | 2023-02-13 | 日機装株式会社 | キャンドモータ、および、キャンドモータの製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3614741A (en) * | 1970-03-23 | 1971-10-19 | Digital Equipment Corp | Data processing system with instruction addresses identifying one of a plurality of registers including the program counter |
US3737871A (en) * | 1971-07-28 | 1973-06-05 | Hewlett Packard Co | Stack register renamer |
US3959777A (en) * | 1972-07-17 | 1976-05-25 | International Business Machines Corporation | Data processor for pattern recognition and the like |
US3810117A (en) * | 1972-10-20 | 1974-05-07 | Ibm | Stack mechanism for a data processor |
US3952289A (en) * | 1975-02-03 | 1976-04-20 | Burroughs Corporation | Controller for linking a typewriter console to a processor unit |
GB1548401A (en) * | 1975-10-08 | 1979-07-11 | Plessey Co Ltd | Data processing memory space allocation and deallocation arrangements |
JPS5255446A (en) * | 1975-10-31 | 1977-05-06 | Toshiba Corp | Information transfer control system |
-
1978
- 1978-11-20 JP JP14310178A patent/JPS5569855A/ja active Granted
-
1979
- 1979-11-07 CA CA000339317A patent/CA1116755A/en not_active Expired
- 1979-11-08 EP EP79302501A patent/EP0011442B1/en not_active Expired
- 1979-11-08 DE DE7979302501T patent/DE2965636D1/de not_active Expired
- 1979-11-09 US US06/092,859 patent/US4334269A/en not_active Expired - Lifetime
- 1979-11-19 ES ES486103A patent/ES486103A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0011442A1 (en) | 1980-05-28 |
JPS5725859B2 (es) | 1982-06-01 |
US4334269A (en) | 1982-06-08 |
CA1116755A (en) | 1982-01-19 |
JPS5569855A (en) | 1980-05-26 |
EP0011442B1 (en) | 1983-06-08 |
DE2965636D1 (en) | 1983-07-14 |
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