ES460687A1 - Un semiconductor planar perfeccionado. - Google Patents

Un semiconductor planar perfeccionado.

Info

Publication number
ES460687A1
ES460687A1 ES460687A ES460687A ES460687A1 ES 460687 A1 ES460687 A1 ES 460687A1 ES 460687 A ES460687 A ES 460687A ES 460687 A ES460687 A ES 460687A ES 460687 A1 ES460687 A1 ES 460687A1
Authority
ES
Spain
Prior art keywords
planar semiconductor
nail
filler
shaped flange
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES460687A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of ES460687A1 publication Critical patent/ES460687A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Electrodes Of Semiconductors (AREA)
ES460687A 1976-07-15 1977-07-13 Un semiconductor planar perfeccionado. Expired ES460687A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2631810A DE2631810C3 (de) 1976-07-15 1976-07-15 Planares Halbleiterbauelement

Publications (1)

Publication Number Publication Date
ES460687A1 true ES460687A1 (es) 1978-06-16

Family

ID=5983078

Family Applications (1)

Application Number Title Priority Date Filing Date
ES460687A Expired ES460687A1 (es) 1976-07-15 1977-07-13 Un semiconductor planar perfeccionado.

Country Status (6)

Country Link
JP (1) JPS6043664B2 (ref)
DE (1) DE2631810C3 (ref)
ES (1) ES460687A1 (ref)
FR (1) FR2358749A1 (ref)
GB (1) GB1535656A (ref)
NL (1) NL183000C (ref)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5649557A (en) * 1979-09-28 1981-05-06 Toshiba Corp Integrated circuit for high-frequency oscillation circuit
DE2945670C2 (de) * 1979-11-12 1982-02-11 Siemens AG, 1000 Berlin und 8000 München Elektrisch leitende Verbindung der aktiven Teile eines elektrischen Bauelements oder einer integrierten Schaltung mit Anschlußpunkten
DE3115856A1 (de) * 1980-04-22 1982-01-21 Ferranti Ltd., Gatley, Cheadle, Cheshire Elektrische schaltungsanordnung
JPS57181135A (en) * 1981-04-30 1982-11-08 Nec Home Electronics Ltd Semiconductor device
JPS59144936U (ja) * 1983-03-17 1984-09-27 オムロン株式会社 近接スイツチ
JPS6138935U (ja) * 1984-08-08 1986-03-11 日本電気株式会社 集積回路装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3450965A (en) * 1966-05-28 1969-06-17 Sony Corp Semiconductor having reinforced lead structure
GB1277333A (en) * 1969-07-31 1972-06-14 Gen Motors Corp Semiconductor devices
DE2534477C3 (de) * 1975-08-01 1979-04-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Kapazitätsarmer Kontaktierungsfleck

Also Published As

Publication number Publication date
NL183000C (nl) 1988-06-16
FR2358749A1 (fr) 1978-02-10
DE2631810B2 (de) 1978-07-06
DE2631810C3 (de) 1979-03-15
JPS6043664B2 (ja) 1985-09-30
JPS5310267A (en) 1978-01-30
GB1535656A (en) 1978-12-13
NL7707719A (nl) 1978-01-17
NL183000B (nl) 1988-01-18
DE2631810A1 (de) 1978-01-19
FR2358749B1 (ref) 1984-01-27

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971201