ES458223A1 - Un sistema de tratamiento de datos con informe o reporte de estado residual durante operaciones encadenadas de entrada- salida de interrupcion monociclica. - Google Patents

Un sistema de tratamiento de datos con informe o reporte de estado residual durante operaciones encadenadas de entrada- salida de interrupcion monociclica.

Info

Publication number
ES458223A1
ES458223A1 ES77458223A ES458223A ES458223A1 ES 458223 A1 ES458223 A1 ES 458223A1 ES 77458223 A ES77458223 A ES 77458223A ES 458223 A ES458223 A ES 458223A ES 458223 A1 ES458223 A1 ES 458223A1
Authority
ES
Spain
Prior art keywords
bus
input
cycle steal
central processor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES77458223A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES458223A1 publication Critical patent/ES458223A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
ES77458223A 1976-04-30 1977-04-27 Un sistema de tratamiento de datos con informe o reporte de estado residual durante operaciones encadenadas de entrada- salida de interrupcion monociclica. Expired ES458223A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/682,228 US4053950A (en) 1976-04-30 1976-04-30 Residual status reporting during chained cycle steal input/output operations

Publications (1)

Publication Number Publication Date
ES458223A1 true ES458223A1 (es) 1978-02-16

Family

ID=24738765

Family Applications (1)

Application Number Title Priority Date Filing Date
ES77458223A Expired ES458223A1 (es) 1976-04-30 1977-04-27 Un sistema de tratamiento de datos con informe o reporte de estado residual durante operaciones encadenadas de entrada- salida de interrupcion monociclica.

Country Status (10)

Country Link
US (1) US4053950A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS52155024A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU506571B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BR (1) BR7702816A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1103325A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CH (1) CH619308A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2719203C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
ES (1) ES458223A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1557115A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SE (1) SE431266B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5248440A (en) * 1975-10-15 1977-04-18 Toshiba Corp Memory access control system
JPS52135634A (en) * 1976-05-10 1977-11-12 Hitachi Ltd Data transfer system
US4122519A (en) * 1976-12-14 1978-10-24 Allen-Bradley Company Data handling module for programmable controller
US4168532A (en) * 1977-02-24 1979-09-18 The United States Of America As Represented By The Secretary Of The Air Force Multimode data distribution and control apparatus
US4161778A (en) * 1977-07-19 1979-07-17 Honeywell Information Systems, Inc. Synchronization control system for firmware access of high data rate transfer bus
JPS5454540A (en) * 1977-10-11 1979-04-28 Hitachi Ltd Data buscontrol system
JPS5455133A (en) * 1977-10-12 1979-05-02 Toshiba Corp Input-output control system
US4286319A (en) * 1977-12-06 1981-08-25 The Singer Company Expandable inter-computer communication system
IT1091633B (it) * 1977-12-30 1985-07-06 Olivetti C Ing E C Spa Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore
JPS5498128A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498138A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498133A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498129A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498136A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498130A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
JPS5498139A (en) * 1978-01-20 1979-08-02 Toshiba Corp Input/output control system
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4639889A (en) * 1980-02-19 1987-01-27 Omron Tateisi Electronics Company System for controlling communication between a main control assembly and programmable terminal units
US4507781A (en) * 1980-03-14 1985-03-26 Ibm Corporation Time domain multiple access broadcasting, multipoint, and conferencing communication apparatus and method
US4451884A (en) * 1982-02-02 1984-05-29 International Business Machines Corporation Cycle stealing I/O controller with programmable offline mode of operation
US4519034A (en) * 1982-06-30 1985-05-21 Elxsi I/O Bus clock
US4636939A (en) * 1982-07-16 1987-01-13 At&T Bell Laboratories Parallel bus protocol
JPS60126945A (ja) * 1983-12-14 1985-07-06 Hitachi Ltd ポ−リング方式
US4926324A (en) * 1985-02-28 1990-05-15 Hitachi, Ltd. I/O control system and method
JPS6336461A (ja) * 1986-07-31 1988-02-17 Pfu Ltd 汎用チャネル制御方式
JP2921879B2 (ja) * 1989-09-29 1999-07-19 株式会社東芝 画像データ処理装置
US5129065A (en) * 1989-10-27 1992-07-07 Sun Microsystems, Inc. Apparatus and methods for interface register handshake for controlling devices
DE69123665T2 (de) * 1990-08-31 1997-07-10 Advanced Micro Devices Inc Integrierte digitale Verarbeitungsvorrichtung
US5144230A (en) * 1990-11-26 1992-09-01 The Boeing Company Method and system for testing integrated circuits by cycle stealing
RU2322690C2 (ru) * 2006-02-09 2008-04-20 Открытое акционерное общество "Завод электроники и механики" (ОАО "ЗЭиМ") Устройство обработки данных (варианты)
US9055688B2 (en) 2010-08-20 2015-06-09 Rockwell Automation Technologies, Inc. Input/output circuits having status indicators aligned with respective terminals

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3487370A (en) * 1966-12-22 1969-12-30 Gen Electric Communications control apparatus in an information processing system
US3728693A (en) * 1972-04-28 1973-04-17 Burroughs Corp Programmatically controlled interrupt system for controlling input/output operations in a digital computer
US3836889A (en) * 1973-03-23 1974-09-17 Digital Equipment Corp Priority interruption circuits for digital computer systems
US3938101A (en) * 1973-12-26 1976-02-10 International Business Machines Corporation Computer system with post execution I/O emulation

Also Published As

Publication number Publication date
DE2719203C2 (de) 1987-01-02
DE2719203A1 (de) 1977-11-10
AU2475277A (en) 1978-11-09
SE431266B (sv) 1984-01-23
BR7702816A (pt) 1978-02-21
JPS5711445B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-03-04
SE7704961L (sv) 1977-10-31
US4053950A (en) 1977-10-11
CA1103325A (en) 1981-06-16
JPS52155024A (en) 1977-12-23
AU506571B2 (en) 1980-01-10
GB1557115A (en) 1979-12-05
CH619308A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1980-09-15

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