JPS5498130A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5498130A
JPS5498130A JP429978A JP429978A JPS5498130A JP S5498130 A JPS5498130 A JP S5498130A JP 429978 A JP429978 A JP 429978A JP 429978 A JP429978 A JP 429978A JP S5498130 A JPS5498130 A JP S5498130A
Authority
JP
Japan
Prior art keywords
channel
control
input
control system
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP429978A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Tsutomu Sakamoto
Keizo Aoyanagi
Michio Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP429978A priority Critical patent/JPS5498130A/en
Publication of JPS5498130A publication Critical patent/JPS5498130A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent information other than channel control blocks from being read out erroneously from a main memory and the needless channel control block processing from being repeated, by providing flags A and B in the data processing unit.
CONSTITUTION: The main memory of the data processing unit which has a channel for I/O control and controls peripheral devices under the control of this channel is provided with not only a channel control block, which has control information corresponding to a peripheral device, but also flags A and B corresponding to peripheral devices respectively. Then, flag A is used to indicate whether the periperipheral device is used or not, and flag B is used to indicate whether the data communication to the peripheral device is completed or not.
COPYRIGHT: (C)1979,JPO&Japio
JP429978A 1978-01-20 1978-01-20 Input/output control system Pending JPS5498130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP429978A JPS5498130A (en) 1978-01-20 1978-01-20 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP429978A JPS5498130A (en) 1978-01-20 1978-01-20 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5498130A true JPS5498130A (en) 1979-08-02

Family

ID=11580625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP429978A Pending JPS5498130A (en) 1978-01-20 1978-01-20 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5498130A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

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