JPS5498131A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5498131A
JPS5498131A JP430078A JP430078A JPS5498131A JP S5498131 A JPS5498131 A JP S5498131A JP 430078 A JP430078 A JP 430078A JP 430078 A JP430078 A JP 430078A JP S5498131 A JPS5498131 A JP S5498131A
Authority
JP
Japan
Prior art keywords
ccb
completion
processing
devices
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP430078A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Tsutomu Sakamoto
Keizo Aoyanagi
Michio Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP430078A priority Critical patent/JPS5498131A/en
Publication of JPS5498131A publication Critical patent/JPS5498131A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make the control of I/O devices possible by providing two kinds of flag corresponding to the number of I/O devices on the main memory and regarding contents of flags and setting or resetting flags.
CONSTITUTION: Channel control block CCB is provided as control information for devices. Flag A is provided for preventing information other than CCB from being read out erroneously from the main memory and the needless CCB processing from being repeated, for example, i case that data is inputted erroneously from a device which CCB is not prepared previously for or interruption is caused to CCB after the completion of the processing for this CCB. Flag B is provided for confirming the completion of the device-side output operation at a WRITE operation time, and is generated immediately after the completion of the output operation to complete the CCB processing.
COPYRIGHT: (C)1979,JPO&Japio
JP430078A 1978-01-20 1978-01-20 Input/output control system Pending JPS5498131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP430078A JPS5498131A (en) 1978-01-20 1978-01-20 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP430078A JPS5498131A (en) 1978-01-20 1978-01-20 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5498131A true JPS5498131A (en) 1979-08-02

Family

ID=11580654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP430078A Pending JPS5498131A (en) 1978-01-20 1978-01-20 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5498131A (en)

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