JPS5498128A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5498128A
JPS5498128A JP429878A JP429878A JPS5498128A JP S5498128 A JPS5498128 A JP S5498128A JP 429878 A JP429878 A JP 429878A JP 429878 A JP429878 A JP 429878A JP S5498128 A JPS5498128 A JP S5498128A
Authority
JP
Japan
Prior art keywords
channel
queue
processing unit
data processing
control block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP429878A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Tsutomu Sakamoto
Keizo Aoyanagi
Michio Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP429878A priority Critical patent/JPS5498128A/en
Publication of JPS5498128A publication Critical patent/JPS5498128A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make the level change of queue possible to give flexibility to a data processing unit, by providing a queue-NO in a channel control block in the data processing unit.
CONSTITUTION: The main memory of the data processing unit which has a channel for I/O control and controls peripheral devices under the control of this channel is provided with a channel control block which has control information corresponding to a peripheral device. Then, a queue number field where plural levels are prepared and a lower level has a priority higher than others and the priority of the termination queue interrupt corresponding to each lecel is formed is provided in this channel control block.
COPYRIGHT: (C)1979,JPO&Japio
JP429878A 1978-01-20 1978-01-20 Input/output control system Pending JPS5498128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP429878A JPS5498128A (en) 1978-01-20 1978-01-20 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP429878A JPS5498128A (en) 1978-01-20 1978-01-20 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5498128A true JPS5498128A (en) 1979-08-02

Family

ID=11580598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP429878A Pending JPS5498128A (en) 1978-01-20 1978-01-20 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5498128A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

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