ES436303A1 - Data processing apparatus - Google Patents

Abstract

Improvements in the circuit arrangements for executing subroutine jump instructions in data processing facilities, where instruction words consisting of partial words are used, which contain, where appropriate, jump criteria, which are stored according to a program in an instruction memory, and whose reading from the instruction memory is carried out by selection by means of an address instruction register, being carried out depending on a criterion for a subprogram jump instruction to execute an increase of an indicator of applet basement and by addressing using this applet basement indicator a storage of a return address from the instruction address register to a return address memory and then forging a jump address of even numbers by parts of the word of current instruction in each case and/or contents of auxiliary memories and/or a main memory in an arithmetic unit and stored in the instruction address register characterized in that for the formation of the criterion for a subroutine instruction to be executed by means of components extracted from one side of the address part of even or odd numbers of the instruction (of 20), and on the other hand the content of even or odd numbers of auxiliary registers (26), it has been provided, according to a provision (27) that links these components depending on a generation clause contained in the current instruction word in each case for the even number jump address and for the criterion, a conjunctive link (33) of the output of this provision (27) with a jump criterion . (Machine-translation by Google Translate, not legally binding)