JPS6482130A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6482130A
JPS6482130A JP24015587A JP24015587A JPS6482130A JP S6482130 A JPS6482130 A JP S6482130A JP 24015587 A JP24015587 A JP 24015587A JP 24015587 A JP24015587 A JP 24015587A JP S6482130 A JPS6482130 A JP S6482130A
Authority
JP
Japan
Prior art keywords
address
register
constant
machine word
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24015587A
Other languages
Japanese (ja)
Inventor
Masahiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24015587A priority Critical patent/JPS6482130A/en
Publication of JPS6482130A publication Critical patent/JPS6482130A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To shorten a time required for execution of a machine word instruction by adding an address register into a CPU to hold the sum of the contents of a base register and a constant contained in the machine word instruction and extracting the corresponding value out of the address register as soon as the execution is started for the machine word instruction. CONSTITUTION:A CPU includes a base register serving as an address generating register (constant value B) and an instruction register stores a machine word instruction. This instruction includes a constant used for calculation of the address of a memory. While the sum of the value B of the base register and said constant is calculated by an adder and held by the address registers more than double as much as the maximum value that can be obtained by the absolute value of the constant. When the machine word instruction which produces a memory access is carried out, the value corresponding to the constant value in the machine word instruction is taken out of those values held by the address register and used as an address. Thus it is possible to shorten the time required for execution of a machine word instruction.
JP24015587A 1987-09-24 1987-09-24 Data processor Pending JPS6482130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24015587A JPS6482130A (en) 1987-09-24 1987-09-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24015587A JPS6482130A (en) 1987-09-24 1987-09-24 Data processor

Publications (1)

Publication Number Publication Date
JPS6482130A true JPS6482130A (en) 1989-03-28

Family

ID=17055312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24015587A Pending JPS6482130A (en) 1987-09-24 1987-09-24 Data processor

Country Status (1)

Country Link
JP (1) JPS6482130A (en)

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