JPS6476340A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6476340A
JPS6476340A JP23425487A JP23425487A JPS6476340A JP S6476340 A JPS6476340 A JP S6476340A JP 23425487 A JP23425487 A JP 23425487A JP 23425487 A JP23425487 A JP 23425487A JP S6476340 A JPS6476340 A JP S6476340A
Authority
JP
Japan
Prior art keywords
cpu
word instruction
machine word
contents
address register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23425487A
Other languages
Japanese (ja)
Inventor
Masahiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23425487A priority Critical patent/JPS6476340A/en
Publication of JPS6476340A publication Critical patent/JPS6476340A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the executing time for a machine word instruction by adding an address register into a CPU to hold a value obtained by subtracting a fixed number from the sum of the contents of plural registers and taking out the corresponding value as soon as the execution is started for the machine word instruction which causes a memory access. CONSTITUTION:An address register is added to a CPU 100 to hold all conceivable combinations of registers as addresses used when the CPU 100 accesses a memory at execution of a machine word instruction in terms of the value obtained by subtracting a fixed number from the sum of the contents of plural registers set in the CPU 100. Then the contents of the address register are taken out as addresses when the machine word instruction with which the CPU 100 accesses the memory is carried out. Thus the time required for calculation of addresses can be omitted and the executing time is shortened for the machine word instruction.
JP23425487A 1987-09-18 1987-09-18 Data processor Pending JPS6476340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23425487A JPS6476340A (en) 1987-09-18 1987-09-18 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23425487A JPS6476340A (en) 1987-09-18 1987-09-18 Data processor

Publications (1)

Publication Number Publication Date
JPS6476340A true JPS6476340A (en) 1989-03-22

Family

ID=16968089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23425487A Pending JPS6476340A (en) 1987-09-18 1987-09-18 Data processor

Country Status (1)

Country Link
JP (1) JPS6476340A (en)

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