ES417338A1 - Metodo para fabricar aparatos a base de circuitos integra- dos. - Google Patents
Metodo para fabricar aparatos a base de circuitos integra- dos.Info
- Publication number
- ES417338A1 ES417338A1 ES417338A ES417338A ES417338A1 ES 417338 A1 ES417338 A1 ES 417338A1 ES 417338 A ES417338 A ES 417338A ES 417338 A ES417338 A ES 417338A ES 417338 A1 ES417338 A1 ES 417338A1
- Authority
- ES
- Spain
- Prior art keywords
- array
- programming
- testing
- electrical impulses
- proceeding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA148,232A CA948705A (en) | 1972-07-28 | 1972-07-28 | Method for making an integrated circuit apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
ES417338A1 true ES417338A1 (es) | 1976-03-01 |
Family
ID=4093989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES417338A Expired ES417338A1 (es) | 1972-07-28 | 1973-07-27 | Metodo para fabricar aparatos a base de circuitos integra- dos. |
Country Status (15)
Country | Link |
---|---|
US (1) | US3810301A (es) |
JP (1) | JPS506294A (es) |
AU (1) | AU5811273A (es) |
BE (1) | BE802822A (es) |
BR (1) | BR7305732D0 (es) |
CA (1) | CA948705A (es) |
DD (1) | DD105688A5 (es) |
DE (1) | DE2338251A1 (es) |
ES (1) | ES417338A1 (es) |
FR (1) | FR2195070A1 (es) |
GB (1) | GB1436004A (es) |
IL (1) | IL42844A (es) |
IN (1) | IN137750B (es) |
IT (1) | IT997484B (es) |
NL (1) | NL7310280A (es) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4038648A (en) * | 1974-06-03 | 1977-07-26 | Chesley Gilman D | Self-configurable circuit structure for achieving wafer scale integration |
JPS5528160B2 (es) * | 1974-12-16 | 1980-07-25 | ||
US3969670A (en) * | 1975-06-30 | 1976-07-13 | International Business Machines Corporation | Electron beam testing of integrated circuits |
US4007452A (en) * | 1975-07-28 | 1977-02-08 | Intel Corporation | Wafer scale integration system |
US4118858A (en) * | 1976-04-19 | 1978-10-10 | Texas Instruments Incorporated | Method of making an electronic calculator |
US4081898A (en) * | 1976-04-19 | 1978-04-04 | Texas Instruments Incorporated | Method of manufacturing an electronic calculator utilizing a flexible carrier |
JPS5735342A (en) * | 1980-08-13 | 1982-02-25 | Hitachi Ltd | Manufacturing method of large scale integrated circuit |
DE3122984A1 (de) * | 1981-06-10 | 1983-01-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur kennzeichnung von halbleiterchips und kennzeichenbarer helbleiterchip |
US4601019B1 (en) * | 1983-08-31 | 1997-09-30 | Texas Instruments Inc | Memory with redundancy |
US4703436A (en) * | 1984-02-01 | 1987-10-27 | Inova Microelectronics Corporation | Wafer level integration technique |
JPH084110B2 (ja) * | 1985-03-30 | 1996-01-17 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
US4719411A (en) * | 1985-05-13 | 1988-01-12 | California Institute Of Technology | Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation |
EP0240864A3 (en) * | 1986-04-03 | 1989-05-24 | Hewlett-Packard Company | High-yield semiconductor memory devices |
US4816422A (en) * | 1986-12-29 | 1989-03-28 | General Electric Company | Fabrication of large power semiconductor composite by wafer interconnection of individual devices |
US4855253A (en) * | 1988-01-29 | 1989-08-08 | Hewlett-Packard | Test method for random defects in electronic microstructures |
US5831467A (en) * | 1991-11-05 | 1998-11-03 | Monolithic System Technology, Inc. | Termination circuit with power-down mode for use in circuit module architecture |
DE69226150T2 (de) * | 1991-11-05 | 1999-02-18 | Hsu Fu Chieh | Redundanzarchitektur für Schaltungsmodul |
US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
AU4798793A (en) * | 1992-08-10 | 1994-03-03 | Monolithic System Technology, Inc. | Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration |
US6246247B1 (en) | 1994-11-15 | 2001-06-12 | Formfactor, Inc. | Probe card assembly and kit, and methods of using same |
US6624648B2 (en) * | 1993-11-16 | 2003-09-23 | Formfactor, Inc. | Probe card assembly |
US20020053734A1 (en) | 1993-11-16 | 2002-05-09 | Formfactor, Inc. | Probe card assembly and kit, and methods of making same |
US6483328B1 (en) * | 1995-11-09 | 2002-11-19 | Formfactor, Inc. | Probe card for probing wafers with raised contact elements |
US6479887B1 (en) | 1998-08-31 | 2002-11-12 | Amkor Technology, Inc. | Circuit pattern tape for wafer-scale production of chip size semiconductor packages |
JP3055104B2 (ja) * | 1998-08-31 | 2000-06-26 | 亜南半導体株式会社 | 半導体パッケ―ジの製造方法 |
US6428641B1 (en) * | 1998-08-31 | 2002-08-06 | Amkor Technology, Inc. | Method for laminating circuit pattern tape on semiconductor wafer |
US6738307B2 (en) * | 2002-05-13 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Address structure and methods for multiple arrays of data storage memory |
KR100761755B1 (ko) * | 2005-02-28 | 2007-09-28 | 삼성전자주식회사 | 입출력 비트구조를 조절할 수 있는 반도체 메모리 장치 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3423822A (en) * | 1967-02-27 | 1969-01-28 | Northern Electric Co | Method of making large scale integrated circuit |
US3715735A (en) * | 1970-12-14 | 1973-02-06 | Monolithic Memories Inc | Segmentized memory module and method of making same |
-
1972
- 1972-07-28 CA CA148,232A patent/CA948705A/en not_active Expired
- 1972-08-31 US US00285496A patent/US3810301A/en not_active Expired - Lifetime
-
1973
- 1973-07-16 AU AU58112/73A patent/AU5811273A/en not_active Expired
- 1973-07-16 IN IN1660/CAL/1973A patent/IN137750B/en unknown
- 1973-07-24 NL NL7310280A patent/NL7310280A/ unknown
- 1973-07-26 IT IT83407/73A patent/IT997484B/it active
- 1973-07-26 DD DD172543A patent/DD105688A5/xx unknown
- 1973-07-26 BE BE133891A patent/BE802822A/xx unknown
- 1973-07-27 FR FR7327679A patent/FR2195070A1/fr not_active Withdrawn
- 1973-07-27 DE DE19732338251 patent/DE2338251A1/de active Pending
- 1973-07-27 BR BR5732/73A patent/BR7305732D0/pt unknown
- 1973-07-27 GB GB3599973A patent/GB1436004A/en not_active Expired
- 1973-07-27 JP JP48084219A patent/JPS506294A/ja active Pending
- 1973-07-27 ES ES417338A patent/ES417338A1/es not_active Expired
- 1973-07-29 IL IL42844A patent/IL42844A/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE2338251A1 (de) | 1974-02-07 |
FR2195070A1 (es) | 1974-03-01 |
NL7310280A (es) | 1974-01-30 |
DD105688A5 (es) | 1974-05-05 |
US3810301A (en) | 1974-05-14 |
IN137750B (es) | 1975-09-13 |
IL42844A (en) | 1976-09-30 |
JPS506294A (es) | 1975-01-22 |
IL42844A0 (en) | 1973-10-25 |
CA948705A (en) | 1974-06-04 |
IT997484B (it) | 1975-12-30 |
GB1436004A (en) | 1976-05-19 |
AU5811273A (en) | 1975-01-16 |
BR7305732D0 (pt) | 1974-08-29 |
BE802822A (fr) | 1973-11-16 |
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