ES2130361T3 - Sistema basado sobre exploracion de contorno y metodo para comprobacion y diagnostico. - Google Patents
Sistema basado sobre exploracion de contorno y metodo para comprobacion y diagnostico.Info
- Publication number
- ES2130361T3 ES2130361T3 ES94306040T ES94306040T ES2130361T3 ES 2130361 T3 ES2130361 T3 ES 2130361T3 ES 94306040 T ES94306040 T ES 94306040T ES 94306040 T ES94306040 T ES 94306040T ES 2130361 T3 ES2130361 T3 ES 2130361T3
- Authority
- ES
- Spain
- Prior art keywords
- test
- diagnosis
- exploration
- bvm
- errors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318566—Comparators; Diagnosing the device under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Abstract
UN SISTEMA (10) PARA PROBAR UNO O MAS TABLEROS DE CIRCUITOS (121-12N) CADA UNO DE LOS CUALES CONTIENE AL MENOS UNA CADENA DE CELDAS DE EXPLORACION DE MARGENES (141-14N) QUE INCLUYE UN ORDENADOR CENTRAL DE PRUEBA Y DIAGNOSTICO DEL SISTEMA (16) PARA GESTIONAR LA PRUEBA GENERAL DEL SISTEMA FORMADO POR LOS TABLEROS DE CIRCUITOS. UNA MAQUINA DE EXPLORACION DE MARGENES VIRTUAL (BVM) (17) SE ACTIVA PARA RECIBIR UN COMANDO DE INICIACION DE UNA PRUEBA PROCEDENTE DEL ORDENADOR CENTRAL DE PRUEBA UN DIAGNOSTICO DEL SISTEMA INDEPENDIENTE DEL NUMERO O DE LA NATURALEZA DE LOS TABLEROS A PROBAR. EN RESPUESTA AL COMANDO DE PRUEBA, LA BVM (17) HACE QUE CADA TABLERO DE CIRCUITOS EJECUTE UN PROGRAMA DE PRUEBA (23) ESPECIFICO AL MISMO PARA DETERMINAR LOS ERRORES, SI LOS HUBIERA, DEL TABLERO. LOS ERRORES DE CADA TABLERO SE VUELVEN A ENVIAR A LA BVM (17) QUE A SU VEZ INTERPRETA LOS ERRORES PARA PROPORCIONAR INFORMACION SOBRE LA PRUEBA, INDICATIVA DEL FUNCIONAMIENTO DE LOS TABLEROS, QUE SE ENVIA ENTONCES AL ORDENADOR CENTRAL DE PRUEBA Y DIAGNOSTICO DEL SISTEMA (16).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/113,460 US5444716A (en) | 1993-08-30 | 1993-08-30 | Boundary-scan-based system and method for test and diagnosis |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2130361T3 true ES2130361T3 (es) | 1999-07-01 |
Family
ID=22349570
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES94306040T Expired - Lifetime ES2130361T3 (es) | 1993-08-30 | 1994-08-17 | Sistema basado sobre exploracion de contorno y metodo para comprobacion y diagnostico. |
Country Status (8)
Country | Link |
---|---|
US (1) | US5444716A (es) |
EP (1) | EP0640920B1 (es) |
JP (1) | JPH07181231A (es) |
KR (1) | KR0138225B1 (es) |
CA (1) | CA2127612C (es) |
DE (1) | DE69416471T2 (es) |
ES (1) | ES2130361T3 (es) |
TW (1) | TW276300B (es) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5774644A (en) * | 1993-12-17 | 1998-06-30 | International Business Machines Corporation | Method and apparatus for generating a pair of interoperating communications programs |
US5537052A (en) * | 1994-06-17 | 1996-07-16 | Emc Corporation | System and method for executing on board diagnostics and maintaining an event history on a circuit board |
DE69634515T2 (de) * | 1995-06-09 | 2005-09-29 | Fujitsu Ltd., Kawasaki | Verfahren, system und anordnung zur effizienten generierung binärer zahlen zum testen von spreichervorrichtungen |
US5706297A (en) * | 1995-08-24 | 1998-01-06 | Unisys Corporation | System for adapting maintenance operations to JTAG and non-JTAG modules |
CA2213966C (en) * | 1995-12-27 | 2004-10-26 | Koken Co., Ltd. | Monitoring control apparatus |
US5815510A (en) * | 1996-03-28 | 1998-09-29 | Cypress Semiconductor Corp. | Serial programming of instruction codes in different numbers of clock cycles |
US5768288A (en) * | 1996-03-28 | 1998-06-16 | Cypress Semiconductor Corp. | Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data |
US5835503A (en) * | 1996-03-28 | 1998-11-10 | Cypress Semiconductor Corp. | Method and apparatus for serially programming a programmable logic device |
US5805794A (en) * | 1996-03-28 | 1998-09-08 | Cypress Semiconductor Corp. | CPLD serial programming with extra read register |
US5668947A (en) * | 1996-04-18 | 1997-09-16 | Allen-Bradley Company, Inc. | Microprocessor self-test apparatus and method |
US5968196A (en) * | 1998-04-21 | 1999-10-19 | Atmel Corporation | Configuration control in a programmable logic device using non-volatile elements |
US6378094B1 (en) * | 1999-04-01 | 2002-04-23 | Lucent Technologies Inc. | Method and system for testing cluster circuits in a boundary scan environment |
US6557129B1 (en) | 1999-11-23 | 2003-04-29 | Janusz Rajski | Method and apparatus for selectively compacting test responses |
US9664739B2 (en) | 1999-11-23 | 2017-05-30 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
JP3845016B2 (ja) * | 1999-11-23 | 2006-11-15 | メンター・グラフィクス・コーポレーション | テスト中回路技術分野へのテストパターンの連続的な適用およびデコンプレッション |
US7493540B1 (en) | 1999-11-23 | 2009-02-17 | Jansuz Rajski | Continuous application and decompression of test patterns to a circuit-under-test |
US6353842B1 (en) * | 1999-11-23 | 2002-03-05 | Janusz Rajski | Method for synthesizing linear finite state machines |
US6327687B1 (en) * | 1999-11-23 | 2001-12-04 | Janusz Rajski | Test pattern compression for an integrated circuit test environment |
US9134370B2 (en) | 1999-11-23 | 2015-09-15 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
US6874109B1 (en) * | 1999-11-23 | 2005-03-29 | Janusz Rajski | Phase shifter with reduced linear dependency |
US6684358B1 (en) | 1999-11-23 | 2004-01-27 | Janusz Rajski | Decompressor/PRPG for applying pseudo-random and deterministic test patterns |
US8533547B2 (en) * | 1999-11-23 | 2013-09-10 | Mentor Graphics Corporation | Continuous application and decompression of test patterns and selective compaction of test responses |
US7062696B2 (en) * | 2000-01-14 | 2006-06-13 | National Semiconductor | Algorithmic test pattern generator, with built-in-self-test (BIST) capabilities, for functional testing of a circuit |
US6959257B1 (en) * | 2000-09-11 | 2005-10-25 | Cypress Semiconductor Corp. | Apparatus and method to test high speed devices with a low speed tester |
US20020093356A1 (en) * | 2000-11-30 | 2002-07-18 | Williams Thomas W. | Intelligent test vector formatting to reduce test vector size and allow encryption thereof for integrated circuit testing |
US6744256B2 (en) * | 2001-10-29 | 2004-06-01 | Agilent Technologies, Inc. | Boundary-scan testing of opto-electronic devices |
TW200401194A (en) * | 2002-07-11 | 2004-01-16 | Advanced Micro Devices Inc | Method and apparatus for determining a processor state without interrupting processor operation |
US20050159925A1 (en) * | 2004-01-15 | 2005-07-21 | Elias Gedamu | Cache testing for a processor design |
US20050172182A1 (en) * | 2004-01-15 | 2005-08-04 | Elias Gedamu | Optimal operational voltage identification for a processor design |
US20050172178A1 (en) * | 2004-01-15 | 2005-08-04 | Elias Gedamu | Cache-testable processor identification |
US7906982B1 (en) | 2006-02-28 | 2011-03-15 | Cypress Semiconductor Corporation | Interface apparatus and methods of testing integrated circuits using the same |
US8453026B2 (en) * | 2006-10-13 | 2013-05-28 | Advantest (Singapore) Pte Ltd | Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures |
US8615691B2 (en) * | 2006-10-13 | 2013-12-24 | Advantest (Singapore) Pte Ltd | Process for improving design-limited yield by localizing potential faults from production test data |
US20080239082A1 (en) * | 2007-03-29 | 2008-10-02 | Analogix Semiconductor, Inc. | HDMI format video pattern and audio frequencies generator for field test and built-in self test |
US10776233B2 (en) | 2011-10-28 | 2020-09-15 | Teradyne, Inc. | Programmable test instrument |
US9759772B2 (en) | 2011-10-28 | 2017-09-12 | Teradyne, Inc. | Programmable test instrument |
CN102520344B (zh) * | 2011-12-16 | 2014-04-02 | 大唐微电子技术有限公司 | 一种用于智能卡测试的边界扫描模块、边界扫描系统 |
CN102621483B (zh) * | 2012-03-27 | 2014-04-16 | 中国人民解放军国防科学技术大学 | 多链路并行边界扫描测试装置及方法 |
US9595350B2 (en) * | 2012-11-05 | 2017-03-14 | Nxp Usa, Inc. | Hardware-based memory initialization |
US10184980B2 (en) | 2016-09-06 | 2019-01-22 | Texas Instruments Incorporated | Multiple input signature register analysis for digital circuitry |
TWI736721B (zh) * | 2017-12-13 | 2021-08-21 | 英業達股份有限公司 | 連接器的腳位連接測試系統及其方法 |
US10515039B2 (en) * | 2018-01-05 | 2019-12-24 | Molex, Llc | Vehicle USB hub system |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4872169A (en) * | 1987-03-06 | 1989-10-03 | Texas Instruments Incorporated | Hierarchical scan selection |
US4872125A (en) * | 1987-06-26 | 1989-10-03 | Daisy Systems Corporation | Multiple processor accelerator for logic simulation |
US5029166A (en) * | 1989-05-31 | 1991-07-02 | At&T Bell Laboratories | Method and apparatus for testing circuit boards |
EP0417905B1 (en) * | 1989-08-09 | 1997-11-05 | Texas Instruments Incorporated | System scan path architecture |
US5132635A (en) * | 1991-03-05 | 1992-07-21 | Ast Research, Inc. | Serial testing of removable circuit boards on a backplane bus |
GB2260414A (en) * | 1991-10-10 | 1993-04-14 | Genrad Inc | Circuit tester with scanner path assignment |
-
1993
- 1993-08-30 US US08/113,460 patent/US5444716A/en not_active Expired - Fee Related
-
1994
- 1994-07-07 CA CA002127612A patent/CA2127612C/en not_active Expired - Fee Related
- 1994-08-10 TW TW083107398A patent/TW276300B/zh active
- 1994-08-17 DE DE69416471T patent/DE69416471T2/de not_active Expired - Fee Related
- 1994-08-17 EP EP94306040A patent/EP0640920B1/en not_active Expired - Lifetime
- 1994-08-17 ES ES94306040T patent/ES2130361T3/es not_active Expired - Lifetime
- 1994-08-29 KR KR1019940021970A patent/KR0138225B1/ko not_active IP Right Cessation
- 1994-08-29 JP JP6226018A patent/JPH07181231A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE69416471D1 (de) | 1999-03-25 |
EP0640920A1 (en) | 1995-03-01 |
CA2127612A1 (en) | 1995-03-01 |
DE69416471T2 (de) | 1999-08-05 |
US5444716A (en) | 1995-08-22 |
EP0640920B1 (en) | 1999-02-10 |
CA2127612C (en) | 1998-08-18 |
JPH07181231A (ja) | 1995-07-21 |
TW276300B (es) | 1996-05-21 |
KR950006470A (ko) | 1995-03-21 |
KR0138225B1 (ko) | 1998-06-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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