ATE94666T1 - Verfahren zur generierung einer kandidatenliste von fehlerhaften schaltungselementen und verfahren zur isolierung von fehlern in einer logischen schaltung unter verwendung dieser kandidatenliste. - Google Patents

Verfahren zur generierung einer kandidatenliste von fehlerhaften schaltungselementen und verfahren zur isolierung von fehlern in einer logischen schaltung unter verwendung dieser kandidatenliste.

Info

Publication number
ATE94666T1
ATE94666T1 AT87112000T AT87112000T ATE94666T1 AT E94666 T1 ATE94666 T1 AT E94666T1 AT 87112000 T AT87112000 T AT 87112000T AT 87112000 T AT87112000 T AT 87112000T AT E94666 T1 ATE94666 T1 AT E94666T1
Authority
AT
Austria
Prior art keywords
candidate list
generating
circuit elements
fault
isolating faults
Prior art date
Application number
AT87112000T
Other languages
English (en)
Inventor
Richard E Glackemeyer
Robert C Petty
Calvin F Page
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE94666T1 publication Critical patent/ATE94666T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Dc Digital Transmission (AREA)
  • Earth Drilling (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Control Of Turbines (AREA)
AT87112000T 1986-09-02 1987-08-18 Verfahren zur generierung einer kandidatenliste von fehlerhaften schaltungselementen und verfahren zur isolierung von fehlern in einer logischen schaltung unter verwendung dieser kandidatenliste. ATE94666T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/902,614 US4727545A (en) 1986-09-02 1986-09-02 Method and apparatus for isolating faults in a digital logic circuit
EP87112000A EP0259662B1 (de) 1986-09-02 1987-08-18 Verfahren zur Generierung einer Kandidatenliste von fehlerhaften Schaltungselementen und Verfahren zur Isolierung von Fehlern in einer logischen Schaltung unter Verwendung dieser Kandidatenliste

Publications (1)

Publication Number Publication Date
ATE94666T1 true ATE94666T1 (de) 1993-10-15

Family

ID=25416113

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87112000T ATE94666T1 (de) 1986-09-02 1987-08-18 Verfahren zur generierung einer kandidatenliste von fehlerhaften schaltungselementen und verfahren zur isolierung von fehlern in einer logischen schaltung unter verwendung dieser kandidatenliste.

Country Status (11)

Country Link
US (1) US4727545A (de)
EP (1) EP0259662B1 (de)
JP (1) JPS63132346A (de)
AT (1) ATE94666T1 (de)
AU (1) AU590110B2 (de)
CA (1) CA1273706A (de)
DE (1) DE3787431T2 (de)
DK (1) DK456087A (de)
FI (1) FI873793A (de)
IE (1) IE872345L (de)
IL (1) IL83617A0 (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996659A (en) * 1986-08-20 1991-02-26 Hitachi, Ltd. Method of diagnosing integrated logic circuit
US4829520A (en) * 1987-03-16 1989-05-09 American Telephone And Telegraph Company, At&T Bell Laboratories In-place diagnosable electronic circuit board
US4961156A (en) * 1987-10-27 1990-10-02 Nec Corporation Simulation capable of simultaneously simulating a logic circuit model in response to a plurality of input logic signals
US5029166A (en) * 1989-05-31 1991-07-02 At&T Bell Laboratories Method and apparatus for testing circuit boards
US5107497A (en) * 1989-07-28 1992-04-21 At&T Bell Laboratories Technique for producing an expert system for system fault diagnosis
US5161158A (en) * 1989-10-16 1992-11-03 The Boeing Company Failure analysis system
US5210699A (en) * 1989-12-18 1993-05-11 Siemens Components, Inc. Process for extracting logic from transistor and resistor data representations of circuits
US5146460A (en) * 1990-02-16 1992-09-08 International Business Machines Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility
US5327361A (en) * 1990-03-30 1994-07-05 International Business Machines Corporation Events trace gatherer for a logic simulation machine
US8050903B1 (en) * 1990-05-29 2011-11-01 Texas Instruments Incorporated Apparatus and method for checkpointing simulation data in a simulator
US5127012A (en) * 1991-02-19 1992-06-30 Eastman Kodak Company Diagnostic and administrative device for document production apparatus
US5633812A (en) * 1992-09-29 1997-05-27 International Business Machines Corporation Fault simulation of testing for board circuit failures
US5418974A (en) * 1992-10-08 1995-05-23 International Business Machines Corporation Circuit design method and system therefor
US5418794A (en) * 1992-12-18 1995-05-23 Amdahl Corporation Error determination scan tree apparatus and method
US5475695A (en) * 1993-03-19 1995-12-12 Semiconductor Diagnosis & Test Corporation Automatic failure analysis system
US5500940A (en) * 1994-04-25 1996-03-19 Hewlett-Packard Company Method for evaluating failure in an electronic data storage system and preemptive notification thereof, and system with component failure evaluation
US6480817B1 (en) * 1994-09-01 2002-11-12 Hynix Semiconductor, Inc. Integrated circuit I/O pad cell modeling
US5671352A (en) * 1995-07-07 1997-09-23 Sun Microsystems, Inc. Error injection to a behavioral model
WO1997016740A1 (en) * 1995-11-02 1997-05-09 Genrad, Inc. System and method of accounting for defect detection in a testing system
US6161202A (en) * 1997-02-18 2000-12-12 Ee-Signals Gmbh & Co. Kg Method for the monitoring of integrated circuits
US8489860B1 (en) * 1997-12-22 2013-07-16 Texas Instruments Incorporated Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device
US6694362B1 (en) * 2000-01-03 2004-02-17 Micromuse Inc. Method and system for network event impact analysis and correlation with network administrators, management policies and procedures
US6515483B1 (en) * 2000-08-30 2003-02-04 Micron Technology, Inc. System for partial scan testing of integrated circuits
US20050157654A1 (en) * 2000-10-12 2005-07-21 Farrell Craig A. Apparatus and method for automated discovery and monitoring of relationships between network elements
US7383191B1 (en) * 2000-11-28 2008-06-03 International Business Machines Corporation Method and system for predicting causes of network service outages using time domain correlation
US6966015B2 (en) * 2001-03-22 2005-11-15 Micromuse, Ltd. Method and system for reducing false alarms in network fault management systems
GB2373607B (en) * 2001-03-23 2003-02-12 Sun Microsystems Inc A computer system
US6744739B2 (en) * 2001-05-18 2004-06-01 Micromuse Inc. Method and system for determining network characteristics using routing protocols
US7043727B2 (en) * 2001-06-08 2006-05-09 Micromuse Ltd. Method and system for efficient distribution of network event data
US7516208B1 (en) 2001-07-20 2009-04-07 International Business Machines Corporation Event database management method and system for network event reporting system
US20050286685A1 (en) * 2001-08-10 2005-12-29 Nikola Vukovljak System and method for testing multiple dial-up points in a communications network
US6961887B1 (en) * 2001-10-09 2005-11-01 The United States Of America As Represented By The Secretary Of The Navy Streamlined LASAR-to-L200 post-processing for CASS
US7363368B2 (en) 2001-12-24 2008-04-22 International Business Machines Corporation System and method for transaction recording and playback
US7395468B2 (en) * 2004-03-23 2008-07-01 Broadcom Corporation Methods for debugging scan testing failures of integrated circuits
US7581150B2 (en) * 2004-09-28 2009-08-25 Broadcom Corporation Methods and computer program products for debugging clock-related scan testing failures of integrated circuits
US7500165B2 (en) 2004-10-06 2009-03-03 Broadcom Corporation Systems and methods for controlling clock signals during scan testing integrated circuits
US8171347B2 (en) * 2007-07-11 2012-05-01 Oracle America, Inc. Method and apparatus for troubleshooting a computer system
US8229723B2 (en) * 2007-12-07 2012-07-24 Sonics, Inc. Performance software instrumentation and analysis for electronic design automation
US8806401B1 (en) * 2013-03-15 2014-08-12 Atrenta, Inc. System and methods for reasonable functional verification of an integrated circuit design
US9940235B2 (en) 2016-06-29 2018-04-10 Oracle International Corporation Method and system for valid memory module configuration and verification
CN107219772B (zh) * 2017-05-23 2020-02-18 南方电网科学研究院有限责任公司 测试多回线故障抑制与隔离装置功能指标的方法、装置及系统
US10585995B2 (en) 2017-06-26 2020-03-10 International Business Machines Corporation Reducing clock power consumption of a computer processor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3702011A (en) * 1970-05-12 1972-10-31 Bell Telephone Labor Inc Apparatus and method for simulating logic faults
GB1389319A (en) * 1971-11-15 1975-04-03 Ibm Data processing system
JPS55153054A (en) * 1979-05-15 1980-11-28 Hitachi Ltd Logic circuit simulation system
GB8309692D0 (en) * 1983-04-09 1983-05-11 Int Computers Ltd Verifying design of digital electronic systems
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
GB8327753D0 (en) * 1983-10-17 1983-11-16 Robinson G D Test generation system
FR2567273B1 (fr) * 1984-07-03 1986-11-14 Commissariat Energie Atomique Dispositif de simulation de la defaillance ou du bon fonctionnement d'un systeme logique
US4654851A (en) * 1984-12-24 1987-03-31 Rockwell International Corporation Multiple data path simulator

Also Published As

Publication number Publication date
AU590110B2 (en) 1989-10-26
DK456087A (da) 1988-03-03
US4727545A (en) 1988-02-23
DE3787431D1 (de) 1993-10-21
DK456087D0 (da) 1987-09-01
EP0259662A2 (de) 1988-03-16
AU7714987A (en) 1988-03-10
EP0259662A3 (en) 1989-07-26
IE872345L (en) 1988-03-02
IL83617A0 (en) 1988-01-31
CA1273706A (en) 1990-09-04
FI873793A0 (fi) 1987-09-01
EP0259662B1 (de) 1993-09-15
DE3787431T2 (de) 1994-01-13
JPS63132346A (ja) 1988-06-04
FI873793A (fi) 1988-03-03

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