ES2106293T3 - Proceso de fabricacion de circuito integrado utilizando una mascara dura. - Google Patents
Proceso de fabricacion de circuito integrado utilizando una mascara dura.Info
- Publication number
- ES2106293T3 ES2106293T3 ES93309634T ES93309634T ES2106293T3 ES 2106293 T3 ES2106293 T3 ES 2106293T3 ES 93309634 T ES93309634 T ES 93309634T ES 93309634 T ES93309634 T ES 93309634T ES 2106293 T3 ES2106293 T3 ES 2106293T3
- Authority
- ES
- Spain
- Prior art keywords
- hard mask
- integrated circuit
- manufacturing process
- circuit manufacturing
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
SE UTILIZA UNA CAPA DE CRISTAL COMO MASCARA DURA PARA DISEÑAR UNA CAPA SUBYACENTE DE POLISILICIO. EL POLISILICIO DISEÑADO PUEDE UTILIZARSE EN ESTRUCTURA DE PUERTAS DE TRANSISTORES DE EFECTO DE CAMPO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/991,789 US5264076A (en) | 1992-12-17 | 1992-12-17 | Integrated circuit process using a "hard mask" |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2106293T3 true ES2106293T3 (es) | 1997-11-01 |
Family
ID=25537567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES93309634T Expired - Lifetime ES2106293T3 (es) | 1992-12-17 | 1993-12-02 | Proceso de fabricacion de circuito integrado utilizando una mascara dura. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5264076A (es) |
EP (1) | EP0602837B1 (es) |
JP (1) | JPH06216086A (es) |
DE (1) | DE69313797T2 (es) |
ES (1) | ES2106293T3 (es) |
TW (1) | TW255980B (es) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5346587A (en) * | 1993-08-12 | 1994-09-13 | Micron Semiconductor, Inc. | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation |
US5439847A (en) * | 1993-11-05 | 1995-08-08 | At&T Corp. | Integrated circuit fabrication with a raised feature as mask |
US5468342A (en) * | 1994-04-28 | 1995-11-21 | Cypress Semiconductor Corp. | Method of etching an oxide layer |
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
US5441914A (en) * | 1994-05-02 | 1995-08-15 | Motorola Inc. | Method of forming conductive interconnect structure |
US5504023A (en) * | 1995-01-27 | 1996-04-02 | United Microelectronics Corp. | Method for fabricating semiconductor devices with localized pocket implantation |
US5950106A (en) * | 1996-05-14 | 1999-09-07 | Advanced Micro Devices, Inc. | Method of patterning a metal substrate using spin-on glass as a hard mask |
US5821169A (en) * | 1996-08-05 | 1998-10-13 | Sharp Microelectronics Technology,Inc. | Hard mask method for transferring a multi-level photoresist pattern |
JP2923866B2 (ja) * | 1996-10-18 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
US5854126A (en) * | 1997-03-31 | 1998-12-29 | Siemens Aktiengesellschaft | Method for forming metallization in semiconductor devices with a self-planarizing material |
US6211034B1 (en) | 1997-04-14 | 2001-04-03 | Texas Instruments Incorporated | Metal patterning with adhesive hardmask layer |
US6057239A (en) * | 1997-12-17 | 2000-05-02 | Advanced Micro Devices, Inc. | Dual damascene process using sacrificial spin-on materials |
US5972722A (en) * | 1998-04-14 | 1999-10-26 | Texas Instruments Incorporated | Adhesion promoting sacrificial etch stop layer in advanced capacitor structures |
US6750149B2 (en) * | 1998-06-12 | 2004-06-15 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing electronic device |
US6096653A (en) * | 1998-12-07 | 2000-08-01 | Worldwide Semiconductor Manufacturing Corporation | Method for fabricating conducting lines with a high topography height |
US6376379B1 (en) | 2000-02-01 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Method of hard mask patterning |
US6737222B2 (en) | 2000-11-21 | 2004-05-18 | Advanced Micro Devices, Inc. | Dual damascene process utilizing a bi-layer imaging layer |
US6753266B1 (en) | 2001-04-30 | 2004-06-22 | Advanced Micro Devices, Inc. | Method of enhancing gate patterning properties with reflective hard mask |
US6534418B1 (en) | 2001-04-30 | 2003-03-18 | Advanced Micro Devices, Inc. | Use of silicon containing imaging layer to define sub-resolution gate structures |
US6541360B1 (en) * | 2001-04-30 | 2003-04-01 | Advanced Micro Devices, Inc. | Bi-layer trim etch process to form integrated circuit gate structures |
US6548423B1 (en) | 2002-01-16 | 2003-04-15 | Advanced Micro Devices, Inc. | Multilayer anti-reflective coating process for integrated circuit fabrication |
US6896821B2 (en) * | 2002-08-23 | 2005-05-24 | Dalsa Semiconductor Inc. | Fabrication of MEMS devices with spin-on glass |
US7538026B1 (en) | 2005-04-04 | 2009-05-26 | Advanced Micro Devices, Inc. | Multilayer low reflectivity hard mask and process therefor |
US7361588B2 (en) * | 2005-04-04 | 2008-04-22 | Advanced Micro Devices, Inc. | Etch process for CD reduction of arc material |
JP5101541B2 (ja) * | 2008-05-15 | 2012-12-19 | 信越化学工業株式会社 | パターン形成方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4244799A (en) * | 1978-09-11 | 1981-01-13 | Bell Telephone Laboratories, Incorporated | Fabrication of integrated circuits utilizing thick high-resolution patterns |
US4521274A (en) * | 1984-05-24 | 1985-06-04 | At&T Bell Laboratories | Bilevel resist |
US4683024A (en) * | 1985-02-04 | 1987-07-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Device fabrication method using spin-on glass resins |
US4935095A (en) * | 1985-06-21 | 1990-06-19 | National Semiconductor Corporation | Germanosilicate spin-on glasses |
US5100503A (en) * | 1990-09-14 | 1992-03-31 | Ncr Corporation | Silica-based anti-reflective planarizing layer |
-
1992
- 1992-12-17 US US07/991,789 patent/US5264076A/en not_active Expired - Lifetime
-
1993
- 1993-11-27 TW TW082110025A patent/TW255980B/zh active
- 1993-12-02 DE DE69313797T patent/DE69313797T2/de not_active Expired - Fee Related
- 1993-12-02 EP EP93309634A patent/EP0602837B1/en not_active Expired - Lifetime
- 1993-12-02 ES ES93309634T patent/ES2106293T3/es not_active Expired - Lifetime
- 1993-12-17 JP JP5317787A patent/JPH06216086A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE69313797T2 (de) | 1998-01-22 |
DE69313797D1 (de) | 1997-10-16 |
TW255980B (es) | 1995-09-01 |
EP0602837A1 (en) | 1994-06-22 |
EP0602837B1 (en) | 1997-09-10 |
US5264076A (en) | 1993-11-23 |
JPH06216086A (ja) | 1994-08-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES2106293T3 (es) | Proceso de fabricacion de circuito integrado utilizando una mascara dura. | |
IT1166587B (it) | Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate | |
DE69418283T2 (de) | TFT mit niedriger parasitärer Kapazität | |
KR870004325A (ko) | 박막트랜지스터 및 그 제조방법 | |
DE3880750T2 (de) | Vertikale Transistor-/Kapazitätspeicherzellen-Struktur und Herstellungsverfahren dafür. | |
IT1202764B (it) | Processo di fabbricazione di circuiti semiconduttori integrati | |
DE3855603T2 (de) | Integrierter bipolarer Hochspannungsleistungstransistor und Niederspannungs-MOS-Transistorstruktur in Emitterumschaltkonfiguration und Herstellungsverfahren | |
ATE102930T1 (de) | Heterozyklische verbindungen, deren herstellung und medikamente diese enthaltend. | |
EP0304824A3 (en) | Thin film mos transistor having pair of gate electrodes opposing across semiconductor layer | |
IT1129303B (it) | Procedimento e composizione per impedire la formazione di vetrone sulle strade | |
IT1139645B (it) | Forma galenica di somministrazione del metoclopramide,suo processo di fabbricazione e farmaco comprendente questa forma | |
ES2037975T3 (es) | Procedimiento de fabricacion de un cristal electro-conductor. | |
IT1102177B (it) | Procedimento di realizzazione di transistori ad effetto di campo di tipo mos e transistori realizzati secondo un tale procedimento | |
IT8421968A0 (it) | Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'. | |
JPS6435961A (en) | Thin film transistor | |
IT1250463B (it) | Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore. | |
JPS6422054A (en) | Manufacture of capacitor of semiconductor device | |
DE3577928D1 (de) | Rueckseitige beleuchtung fuer passive elektrooptische anzeigevorrichtungen und hiermit verwendbare transflektive schicht. | |
IT7821965A0 (it) | Procedimento per la produzione di almeno in circuito analogico integrato con almeno un circuito i alla seconda/l | |
JPS53143177A (en) | Production of field effect transistor | |
BR7703497A (pt) | Dispositivo semicondutores passivados com vidro passivador borrifado | |
JPS5516480A (en) | Insulating gate electrostatic effect transistor and semiconductor integrated circuit device | |
JPS5773965A (en) | Switched capcitor integrator | |
JPS6428950A (en) | Semiconductor storage device and manufacture thereof | |
JPS51148386A (en) | Vacant layer attaching type 4 pole semiconductor element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
Ref document number: 602837 Country of ref document: ES |