IT1102177B - Procedimento di realizzazione di transistori ad effetto di campo di tipo mos e transistori realizzati secondo un tale procedimento - Google Patents
Procedimento di realizzazione di transistori ad effetto di campo di tipo mos e transistori realizzati secondo un tale procedimentoInfo
- Publication number
- IT1102177B IT1102177B IT48972/78A IT4897278A IT1102177B IT 1102177 B IT1102177 B IT 1102177B IT 48972/78 A IT48972/78 A IT 48972/78A IT 4897278 A IT4897278 A IT 4897278A IT 1102177 B IT1102177 B IT 1102177B
- Authority
- IT
- Italy
- Prior art keywords
- transistors
- procedure
- type field
- realized according
- mos type
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7711912A FR2388410A1 (fr) | 1977-04-20 | 1977-04-20 | Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede |
Publications (2)
Publication Number | Publication Date |
---|---|
IT7848972A0 IT7848972A0 (it) | 1978-04-19 |
IT1102177B true IT1102177B (it) | 1985-10-07 |
Family
ID=9189666
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT48972/78A IT1102177B (it) | 1977-04-20 | 1978-04-19 | Procedimento di realizzazione di transistori ad effetto di campo di tipo mos e transistori realizzati secondo un tale procedimento |
Country Status (5)
Country | Link |
---|---|
US (1) | US4160683A (it) |
DE (1) | DE2817342A1 (it) |
FR (1) | FR2388410A1 (it) |
GB (1) | GB1594537A (it) |
IT (1) | IT1102177B (it) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54140483A (en) * | 1978-04-21 | 1979-10-31 | Nec Corp | Semiconductor device |
JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
US4280855A (en) * | 1980-01-23 | 1981-07-28 | Ibm Corporation | Method of making a dual DMOS device by ion implantation and diffusion |
US5202574A (en) * | 1980-05-02 | 1993-04-13 | Texas Instruments Incorporated | Semiconductor having improved interlevel conductor insulation |
US4317276A (en) * | 1980-06-12 | 1982-03-02 | Teletype Corporation | Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer |
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
FR2525389A1 (fr) * | 1982-04-14 | 1983-10-21 | Commissariat Energie Atomique | Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre |
US4830975A (en) * | 1983-01-13 | 1989-05-16 | National Semiconductor Corporation | Method of manufacture a primos device |
US4553315A (en) * | 1984-04-05 | 1985-11-19 | Harris Corporation | N Contact compensation technique |
US4818714A (en) * | 1987-12-02 | 1989-04-04 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having LDD regions with graded junctions |
US5015595A (en) * | 1988-09-09 | 1991-05-14 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask |
JP3426043B2 (ja) * | 1994-09-27 | 2003-07-14 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6933237B2 (en) * | 2002-06-21 | 2005-08-23 | Hewlett-Packard Development Company, L.P. | Substrate etch method and device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USB381501I5 (it) * | 1964-07-09 | |||
GB1187611A (en) * | 1966-03-23 | 1970-04-08 | Matsushita Electronics Corp | Method of manufacturing Semiconductors Device |
US3434021A (en) * | 1967-01-13 | 1969-03-18 | Rca Corp | Insulated gate field effect transistor |
US3837071A (en) * | 1973-01-16 | 1974-09-24 | Rca Corp | Method of simultaneously making a sigfet and a mosfet |
US3959025A (en) * | 1974-05-01 | 1976-05-25 | Rca Corporation | Method of making an insulated gate field effect transistor |
-
1977
- 1977-04-20 FR FR7711912A patent/FR2388410A1/fr active Granted
-
1978
- 1978-04-17 US US05/897,169 patent/US4160683A/en not_active Expired - Lifetime
- 1978-04-18 GB GB15315/78A patent/GB1594537A/en not_active Expired
- 1978-04-19 IT IT48972/78A patent/IT1102177B/it active
- 1978-04-20 DE DE19782817342 patent/DE2817342A1/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
FR2388410A1 (fr) | 1978-11-17 |
FR2388410B1 (it) | 1981-11-13 |
GB1594537A (en) | 1981-07-30 |
DE2817342A1 (de) | 1978-10-26 |
US4160683A (en) | 1979-07-10 |
IT7848972A0 (it) | 1978-04-19 |
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