ES2103340T3 - Generador de impulsos. - Google Patents

Generador de impulsos.

Info

Publication number
ES2103340T3
ES2103340T3 ES92301898T ES92301898T ES2103340T3 ES 2103340 T3 ES2103340 T3 ES 2103340T3 ES 92301898 T ES92301898 T ES 92301898T ES 92301898 T ES92301898 T ES 92301898T ES 2103340 T3 ES2103340 T3 ES 2103340T3
Authority
ES
Spain
Prior art keywords
signal
latched
latch
generating
responsive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92301898T
Other languages
English (en)
Inventor
Rajiv M Hattangadi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2103340T3 publication Critical patent/ES2103340T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Saccharide Compounds (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

UN GENERADOR DE PULSO PARA GENERAR UN PULSO DE SALIDA QUE SE SINCRONIZA A UN PULSO DE RELOJ INTERNO QUE INCLUYE UN CIRCUITO DETECTOR DE PESTILLO (24) , UN PESTILLO MAESTRO (12), UN PESTILLO DE RELOJ (14), UN PRIMER MEDIO -PESTILLO DE RELOJ (16), Y UN CIRCUITO LOGICO DE SALIDA (18). EL PESTILLO DETECTOR (24) RESPONDE SOLO AL BORDE POSITIVO DEL PULSO SINCRONOMO DE UN ANCHO VARIANTE PARA GENERAR UNA SEÑAL DE DISPARO QUE SE CIERRA A UN NIVEL LOGICO BAJO. EL PESTILLO MAESTRO (12) RESPONDE A LA SEÑAL DE DISPARO PARA GENERAR UNA PRIMERA SEÑAL CERRADA QUE SE CIERRA A UN NIVEL LOGICO ALTO. EL MEDIO DE PESTILLO DE RELOJ (14) RESPONDE A LA PRIMERA SEÑAL CERRADA Y A UNA PRIMERA SEÑAL DE PULSO DE RELOJ INTERNO PARA GENERAR UNA SEGUNDA SEÑAL CERRADA QUE SE CIERRA A UN NIVEL LOGICO ALTO. EL PRIMER MEDIO-PESTILLO DE RELOJ (16) RESPONDE A LA SEGUNDA SEÑAL CERRADA Y A UNA SEGUNDA SEÑAL DE PULSO DE RELOJ INTERNO PARA GENERAR UNA SEÑAL DE CONTROL. EL CIRCUITO LOGICO DE SALIDA (18) RESPONDE A LA PRIMERA SEÑAL DE PULSO DE RELOJ INTERNO Y A LA SEÑAL DE CONTROL PARA GENERAR UNA SEÑAL DE PULSO DE SALIDA QUE SE SINCRONIZA A LA PRIMERA SEÑAL DE PULSO DE RELOJ INTERNO CUANDO LA SEÑAL DE CONTROL ESTA EN EL NIVEL LOGICO BAJO. SE PROPORCIONA UN CIRCUITO DESCARGADOR (19) Y RESPONDE A LA SEÑAL DE CONTROL Y A LA PRIMERA SEÑAL DE PULSO DE RELOJ INTERNO PARA GENERAR UNA SEÑAL DE DESCARGA QUE REAJUSTA LA PRIMERA SEÑAL CERRADA A UN NIVEL LOGICO BAJO EN LA SALIDA DEL PESTILLO MAESTRO.
ES92301898T 1991-03-07 1992-03-05 Generador de impulsos. Expired - Lifetime ES2103340T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/666,101 US5087835A (en) 1991-03-07 1991-03-07 Positive edge triggered synchronized pulse generator

Publications (1)

Publication Number Publication Date
ES2103340T3 true ES2103340T3 (es) 1997-09-16

Family

ID=24672827

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92301898T Expired - Lifetime ES2103340T3 (es) 1991-03-07 1992-03-05 Generador de impulsos.

Country Status (6)

Country Link
US (1) US5087835A (es)
EP (1) EP0502732B1 (es)
JP (1) JPH07202686A (es)
AT (1) ATE154992T1 (es)
DE (1) DE69220592T2 (es)
ES (1) ES2103340T3 (es)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280203A (en) * 1992-05-15 1994-01-18 Altera Corporation Look-ahead asynchronous register set/reset in programmable logic device
US5343096A (en) * 1992-05-19 1994-08-30 Hewlett-Packard Company System and method for tolerating dynamic circuit decay
JPH07297684A (ja) * 1994-04-28 1995-11-10 Ando Electric Co Ltd 同期データ列発生回路
JP3375504B2 (ja) * 1996-12-17 2003-02-10 富士通株式会社 パルス発生回路および半導体記憶装置
US6753705B1 (en) * 2000-07-27 2004-06-22 Sigmatel, Inc. Edge sensitive detection circuit
US7339955B2 (en) * 2000-09-25 2008-03-04 Pulse-Link, Inc. TDMA communication method and apparatus using cyclic spreading codes
US7031371B1 (en) * 2000-09-25 2006-04-18 Lakkis Ismail A CDMA/TDMA communication method and apparatus for wireless communication using cyclic spreading codes
US8045935B2 (en) * 2001-12-06 2011-10-25 Pulse-Link, Inc. High data rate transmitter and receiver
US7406647B2 (en) * 2001-12-06 2008-07-29 Pulse-Link, Inc. Systems and methods for forward error correction in a wireless communication network
US7317756B2 (en) * 2001-12-06 2008-01-08 Pulse-Link, Inc. Ultra-wideband communication apparatus and methods
US7391815B2 (en) * 2001-12-06 2008-06-24 Pulse-Link, Inc. Systems and methods to recover bandwidth in a communication system
US7483483B2 (en) * 2001-12-06 2009-01-27 Pulse-Link, Inc. Ultra-wideband communication apparatus and methods
US20050053121A1 (en) * 2001-12-06 2005-03-10 Ismail Lakkis Ultra-wideband communication apparatus and methods
US7403576B2 (en) 2001-12-06 2008-07-22 Pulse-Link, Inc. Systems and methods for receiving data in a wireless communication network
US7450637B2 (en) * 2001-12-06 2008-11-11 Pulse-Link, Inc. Ultra-wideband communication apparatus and methods
US7352806B2 (en) * 2001-12-06 2008-04-01 Tensorcom, Inc. Systems and methods for transmitting data in a wireless communication network
US20050201473A1 (en) * 2001-12-06 2005-09-15 Ismail Lakkis Systems and methods for receiving data in a wireless communication network
US7349439B2 (en) * 2001-12-06 2008-03-25 Pulse-Link, Inc. Ultra-wideband communication systems and methods
US7257156B2 (en) * 2001-12-06 2007-08-14 Pulse˜Link, Inc. Systems and methods for equalization of received signals in a wireless communication network
US7289494B2 (en) * 2001-12-06 2007-10-30 Pulse-Link, Inc. Systems and methods for wireless communication over a wide bandwidth channel using a plurality of sub-channels
US20050152483A1 (en) * 2001-12-06 2005-07-14 Ismail Lakkis Systems and methods for implementing path diversity in a wireless communication network
KR100866134B1 (ko) * 2006-12-28 2008-10-31 주식회사 하이닉스반도체 펄스 발생 회로
DE102014212288A1 (de) * 2014-06-26 2015-12-31 Dr. Johannes Heidenhain Gmbh Vorrichtung und Verfahren zum Erzeugen eines Triggersignals in einer Positionsmesseinrichtung und Positionsmesseinrichtung hierzu

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2127944A1 (de) * 1971-06-04 1972-12-14 Siemens Ag Integrierbare Schaltungsanordnung zum Umwandeln asynchroner Eingangssignale in mit einem systemeigenen Takt synchronisierte Signale
DE2246590A1 (de) * 1972-09-22 1974-03-28 Philips Patentverwaltung Schaltungsanordnung zum synchronisieren von eingangsimpulsen mit einem taktpuls
US4317053A (en) * 1979-12-05 1982-02-23 Motorola, Inc. High speed synchronization circuit
DE3105905C2 (de) * 1981-02-18 1982-11-04 Eurosil GmbH, 8000 München Schaltungsanordnung zum Umwandeln von Eingangsimpulsen in prellfreie und mit einem vorgegebenen Takt synchrone Ausgangsimpulse
US4864158A (en) * 1988-01-28 1989-09-05 Amtech Corporation Rapid signal validity checking apparatus

Also Published As

Publication number Publication date
ATE154992T1 (de) 1997-07-15
US5087835A (en) 1992-02-11
DE69220592T2 (de) 1998-02-05
EP0502732B1 (en) 1997-07-02
DE69220592D1 (de) 1997-08-07
JPH07202686A (ja) 1995-08-04
EP0502732A1 (en) 1992-09-09

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