ES2101214T3 - Circuito de conversion de nivel. - Google Patents

Circuito de conversion de nivel.

Info

Publication number
ES2101214T3
ES2101214T3 ES93201711T ES93201711T ES2101214T3 ES 2101214 T3 ES2101214 T3 ES 2101214T3 ES 93201711 T ES93201711 T ES 93201711T ES 93201711 T ES93201711 T ES 93201711T ES 2101214 T3 ES2101214 T3 ES 2101214T3
Authority
ES
Spain
Prior art keywords
transistor
conversion circuit
vss
level conversion
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93201711T
Other languages
English (en)
Inventor
Daniel Sallaerts
Leon Cloetens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Original Assignee
Alcatel Bell NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Bell NV filed Critical Alcatel Bell NV
Application granted granted Critical
Publication of ES2101214T3 publication Critical patent/ES2101214T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

SE DESCUBRE UN CIRCUITO DE CONVERSION DE NIVEL QUE CONVIERTE UNA SEÑAL DE ENTRADA DIGITAL QUE VARIA ENTRE UNOS NIVELES DE VOLTAJE PRIMERO (VSS) Y SEGUNDO (VDD1) EN UNA SEÑAL DE SALIDA DIGITAL QUE VARIA ENTRE EL PRIMER NIVEL DE VOLTAJE (VSS) Y UN TERCER NIVEL DE VOLTAJE (VDD2). INCLUYE, ENTRE LOS POLOS PRIMERO (VDD2) Y SEGUNDO (VSS) DE UNA FUENTE DE CORRIENTE CONTINUA, LA SERIE DE CONEXIONES DE UNA IMPEDANCIA DE CARGA (P2/P3/N3) Y LAS VIAS PRINCIPALES DE UN PRIMER TRANSISTOR (N2) Y DE UN SEGUNDO TRANSISTOR (N1) HACIA EL ELECTRODO DE CONTROL DEL QUE SE APLICA LA SEÑAL DE ENTRADA. EL PRIMER TRANSISTOR Y EL SEGUNDO SON DE UN MISMO PRIMER TIPO DE CONDUCTIVIDAD. UN TERCER TRANSISTOR (P1) DE UN SEGUNDO TIPO DE CONDUCTIVIDAD ESTA CONECTADO EN PARALELO AL SEGUNDO TRANSISTOR (N1). EL ELECTRODO DE CONTROL DE LOS TRANSISTORES TERCERO (P1) Y PRIMERO (N2) ESTAN POLARIZADOS POR UN VOLTAJE DE POLARIZACION CONSTANTE DE CORRIENTE CONTINUA (VBIAS1A/VBIAS1B) Y EL PUNTO DE UNION DE LA IMPEDANCIA DE CARGA (P2/P3/N3) Y LA CONEXION EN SERIE CONSTITUYE UNA TERMINAL DE SALIDA (OUT) DEL CIRCUITO DE CONVERSION DE NIVEL.
ES93201711T 1993-06-15 1993-06-15 Circuito de conversion de nivel. Expired - Lifetime ES2101214T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93201711A EP0630110B1 (en) 1993-06-15 1993-06-15 Level conversion circuit

Publications (1)

Publication Number Publication Date
ES2101214T3 true ES2101214T3 (es) 1997-07-01

Family

ID=8213899

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93201711T Expired - Lifetime ES2101214T3 (es) 1993-06-15 1993-06-15 Circuito de conversion de nivel.

Country Status (6)

Country Link
US (1) US5479116A (es)
EP (1) EP0630110B1 (es)
JP (1) JP3492765B2 (es)
CA (1) CA2125827A1 (es)
DE (1) DE69310162T2 (es)
ES (1) ES2101214T3 (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668483A (en) * 1995-06-21 1997-09-16 Micron Quantum Devices, Inc. CMOS buffer having stable threshold voltage
US5760655A (en) * 1995-06-21 1998-06-02 Micron Quantum Devices, Inc. Stable frequency oscillator having two capacitors that are alternately charged and discharged
US5583454A (en) * 1995-12-01 1996-12-10 Advanced Micro Devices, Inc. Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function
US5892371A (en) * 1996-02-12 1999-04-06 Advanced Micro Devices, Inc. Gate oxide voltage limiting devices for digital circuits
US5874836A (en) * 1996-09-06 1999-02-23 International Business Machines Corporation High reliability I/O stacked fets
SE510612C2 (sv) * 1996-11-08 1999-06-07 Ericsson Telefon Ab L M Förfarande och anordning för att Likströmsmässigt anpassa en första krets till minst en andra krets
US5914617A (en) * 1996-12-23 1999-06-22 Lsi Logic Corporation Output driver for sub-micron CMOS
US5896044A (en) * 1997-12-08 1999-04-20 Lucent Technologies, Inc. Universal logic level shifting circuit and method
US6140846A (en) * 1998-10-30 2000-10-31 International Business Machines Corporation Driver circuit configured for use with receiver
US6353524B1 (en) 2000-03-17 2002-03-05 International Business Machines Corporation Input/output circuit having up-shifting circuitry for accommodating different voltage signals
US6373284B1 (en) 2000-08-14 2002-04-16 Semiconductor Components Industries Llc Voltage level shifting circuit for bidirectional data
US20060152255A1 (en) * 2005-01-13 2006-07-13 Elite Semiconductor Memory Technology Inc. Gate oxide protected I/O circuit
JP5008032B2 (ja) * 2007-08-30 2012-08-22 ソニーモバイルディスプレイ株式会社 遅延回路、半導体制御回路、表示装置、および電子機器
US20100321083A1 (en) * 2009-06-22 2010-12-23 International Business Machines Corporation Voltage Level Translating Circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4697101A (en) * 1983-08-30 1987-09-29 Kabushiki Kaisha Toshiba Read/write control circuit
US4631426A (en) * 1984-06-27 1986-12-23 Honeywell Inc. Digital circuit using MESFETS
US4958091A (en) * 1988-06-06 1990-09-18 Micron Technology, Inc. CMOS voltage converter
EP0388074A1 (en) * 1989-03-16 1990-09-19 STMicroelectronics, Inc. Cmos level shifting circuit
US4963766A (en) * 1989-06-28 1990-10-16 Digital Equipment Corporation Low-voltage CMOS output buffer
US5172016A (en) * 1991-06-28 1992-12-15 Digital Equipment Corporation Five-volt tolerant differential receiver
US5321324A (en) * 1993-01-28 1994-06-14 United Memories, Inc. Low-to-high voltage translator with latch-up immunity

Also Published As

Publication number Publication date
DE69310162T2 (de) 1997-09-25
JP3492765B2 (ja) 2004-02-03
US5479116A (en) 1995-12-26
CA2125827A1 (en) 1994-12-16
DE69310162D1 (de) 1997-05-28
JPH07142990A (ja) 1995-06-02
EP0630110B1 (en) 1997-04-23
EP0630110A1 (en) 1994-12-21

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