ES2066773T3 - Aparato para conmutar dinamicamente la fuente de reloj de un sistema de proceso de datos. - Google Patents

Aparato para conmutar dinamicamente la fuente de reloj de un sistema de proceso de datos.

Info

Publication number
ES2066773T3
ES2066773T3 ES88110123T ES88110123T ES2066773T3 ES 2066773 T3 ES2066773 T3 ES 2066773T3 ES 88110123 T ES88110123 T ES 88110123T ES 88110123 T ES88110123 T ES 88110123T ES 2066773 T3 ES2066773 T3 ES 2066773T3
Authority
ES
Spain
Prior art keywords
clock signals
central
central system
signals
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88110123T
Other languages
English (en)
Inventor
Jaime Calle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of ES2066773T3 publication Critical patent/ES2066773T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Electric Clocks (AREA)
  • Information Transfer Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Multi Processors (AREA)

Abstract

UN SISTEMA DE PROCESO DE DATOS INCLUYE UN PRIMER Y UN SEGUNDO SISTEMACENTRAL EN DONDE LA UNIDAD CENTRAL DE PROCESO (CPU) DEL PRIMER SISTEMA CENTRAL ESTA CONECTADA A LA UNIDAD DE CONTROL DEL SISTEMA (SCU) DEL SEGUNDO SISTEMA CENTRAL Y LA CPU DEL SEGUNDO SISTEMA CENTRAL ESTA CONECTADA A LA SCU DEL PRIMER SISTEMA CENTRAL, CADA SISTEMA CENTRAL INCLUYE UN PROCESADOR DE SERVICIO Y UN SUBSISTEMA TEMPORIZADOR PARA SUMINISTRAR SEÑALES DE RELOJ. CADA SISTEMA CENTRAL INCLUYE UN APARATO PARA DISTRIBUIR LAS SEÑALES DE RELOJ DE TAL MANERA QUE CADA SISTEMA CENTRAL SE TEMPORIZA A PARTIR DE SEÑALES PREDETERMINADAS DE TEMPORIZACION EN RESPUESTA A LAS SEÑALES DE CONTROL DEL PROCESADOR DE SERVICIOS. EL APARATO PERMITE QUE LA DISTRIBUCCION DE LAS SEÑALES DE TEMPORIZACION SEA DINAMICAMENTE CONMUTADA MIENTRAS LOS SISTEMAS CENTRALES ESTAN FUNCIONANDO, LA CONMUTACION DE LAS SEÑALES DE RELOJ SE REALIZA SIN AFECTAR EL FUNCIONAMIENTO DE LOS SISTEMAS CENTRALES. EL APARATO COMPRENDE UN ELEMENTO GENERADOR PARA GENERAR SEÑALES DE RELOJ LOCALES. UN PRIMER ELEMENTO LOGICO GENERA UNA SEÑAL DE ALTO EN UN MOMENTO PREDETERMINADO CON RELACION A LAS SEÑALES DE RELOJ LOCALES EN RESPUESTA A PREDETERMINADAS SEÑALES DE CONTROL. UN ELEMENTO CONMUTADOR DA SALIDA EN FORMA CONDICIONAL A LAS SEÑALES DE RELOJ LOCALES EN RESPUESTA A LA SEÑAL DE ALTO. UN SELECTOR QUE RECIBE SEÑALES DE RELOJ REMOTAS DESDE EL SUBSISTEMA DE TEMPORIZACION DEL OTRO SISTEMA CENTRAL DA SALIDA SELECTIVAMENTE A LAS SEÑALES DE RELOJ LOCALES O A LAS SEÑALES DE RELOJ REMOTAS EN RESPUESTA A LAS SEÑALES DE CONTROL PREDETERMINADAS, LAS SEÑALES DE CONTROL SON MODIFICADAS DURANTE UN PERIODO DE TIEMPO MIENTRAS LA SEÑAL DE ALTO ESTA ACTIVO, PERMITIENDO ASI AL SELECTOR SELECCIONAR SEÑALES DE RELOJ ALTERNAS ANTES DE QUE LA SEÑAL DE ALTO SE VUELVA INACTIVA CONMUTANDO DE ESTA FORMA LA FUENTE DE LAS SEÑALES DE RELOJ QUE ESTAN TEMPORIZANDO LOS SISTEMAS CENTRALES SIN PERTURBAR LAS TAREAS QUE ESTAN SIENDO EJECUTADAS EN LOS SISTEMAS CENTRALES.
ES88110123T 1987-06-26 1988-06-24 Aparato para conmutar dinamicamente la fuente de reloj de un sistema de proceso de datos. Expired - Lifetime ES2066773T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/066,689 US4823262A (en) 1987-06-26 1987-06-26 Apparatus for dynamically switching the clock source of a data processing system

Publications (1)

Publication Number Publication Date
ES2066773T3 true ES2066773T3 (es) 1995-03-16

Family

ID=22071061

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88110123T Expired - Lifetime ES2066773T3 (es) 1987-06-26 1988-06-24 Aparato para conmutar dinamicamente la fuente de reloj de un sistema de proceso de datos.

Country Status (8)

Country Link
US (1) US4823262A (es)
EP (1) EP0296617B1 (es)
AU (1) AU596013B2 (es)
CA (1) CA1302583C (es)
DE (1) DE3852721T2 (es)
DK (1) DK351288A (es)
ES (1) ES2066773T3 (es)
NO (1) NO882795L (es)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
JPH0276056A (ja) * 1988-09-13 1990-03-15 Toshiba Corp 情報処理装置
US6727903B1 (en) 1989-04-20 2004-04-27 Hitachi, Ltd. Microprocessor, and graphics processing apparatus and method using the same
JPH02278475A (ja) * 1989-04-20 1990-11-14 Hitachi Ltd 図形処理装置およびその使用方法ならびにマイクロプロセッサ
US5220661A (en) * 1989-09-15 1993-06-15 Digital Equipment Corporation System and method for reducing timing channels in digital data processing systems
US5313619A (en) * 1991-05-16 1994-05-17 Gerard J. Severance External clock unit for a computer
JPH06502264A (ja) * 1990-10-12 1994-03-10 インテル・コーポレーション 動的に切替え自在な多周波数クロック発生器
GB2252432B (en) * 1991-02-01 1994-09-28 Intel Corp Method and apparatus for operating a computer bus using selectable clock frequencies
EP0602422A1 (en) * 1992-12-15 1994-06-22 International Business Machines Corporation Dynamic frequency shifting with divide by one clock generators
US5517638A (en) * 1993-05-13 1996-05-14 Texas Instruments Incorporated Dynamic clock switching circuitry and method
US5406061A (en) * 1993-06-19 1995-04-11 Opticon Inc. Bar code scanner operable at different frequencies
US5649177A (en) * 1993-06-21 1997-07-15 International Business Machines Corporation Control logic for very fast clock speeds
US5479648A (en) * 1994-08-30 1995-12-26 Stratus Computer, Inc. Method and apparatus for switching clock signals in a fault-tolerant computer system
US5604452A (en) * 1995-04-03 1997-02-18 Exar Corporation Clock generator using a state machine to switch between two offset clocks
US5659789A (en) * 1995-12-15 1997-08-19 Compaq Computer Corporation Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU
US6055362A (en) * 1996-03-29 2000-04-25 Bull Hn Information Systems Inc. Apparatus for phase synchronizing clock signals in a fully redundant computer system
US6718474B1 (en) 2000-09-21 2004-04-06 Stratus Technologies Bermuda Ltd. Methods and apparatus for clock management based on environmental conditions
US7308592B2 (en) * 2005-02-11 2007-12-11 International Business Machines Corporation Redundant oscillator distribution in a multi-processor server system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648252A (en) * 1969-11-03 1972-03-07 Honeywell Inc Multiprogrammable, multiprocessor computer system
US3715729A (en) * 1971-03-10 1973-02-06 Ibm Timing control for a multiprocessor system
JPS56111928A (en) * 1980-02-07 1981-09-04 Nec Corp Clock source switching system
US4354229A (en) * 1980-03-10 1982-10-12 International Business Machines Corporation Loop initialization mechanism for a peer-to-peer communication system
US4468734A (en) * 1982-03-26 1984-08-28 International Business Machines Corporation Method of purging erroneous signals from closed ring data communication networks capable of repeatedly circulating such signals
US4677433A (en) * 1983-02-16 1987-06-30 Daisy Systems Corporation Two-speed clock scheme for co-processors
US4709347A (en) * 1984-12-17 1987-11-24 Honeywell Inc. Method and apparatus for synchronizing the timing subsystems of the physical modules of a local area network
US4703421A (en) * 1986-01-03 1987-10-27 Gte Communication Systems Corporation Ready line synchronization circuit for use in a duplicated computer system

Also Published As

Publication number Publication date
DE3852721T2 (de) 1995-08-24
EP0296617A2 (en) 1988-12-28
AU1830788A (en) 1989-01-05
EP0296617A3 (en) 1990-06-13
US4823262A (en) 1989-04-18
AU596013B2 (en) 1990-04-12
NO882795D0 (no) 1988-06-23
EP0296617B1 (en) 1995-01-11
NO882795L (no) 1988-12-27
CA1302583C (en) 1992-06-02
DE3852721D1 (de) 1995-02-23
DK351288A (da) 1988-12-27
DK351288D0 (da) 1988-06-24

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