ES2048188T3 - Procedimiento para la determinacion de una tension de activacion de un oscilador controlado por tension en un circuito regulador de fases. - Google Patents

Procedimiento para la determinacion de una tension de activacion de un oscilador controlado por tension en un circuito regulador de fases.

Info

Publication number
ES2048188T3
ES2048188T3 ES88119595T ES88119595T ES2048188T3 ES 2048188 T3 ES2048188 T3 ES 2048188T3 ES 88119595 T ES88119595 T ES 88119595T ES 88119595 T ES88119595 T ES 88119595T ES 2048188 T3 ES2048188 T3 ES 2048188T3
Authority
ES
Spain
Prior art keywords
clock signals
voltage
controlled oscillator
oscillator
determination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88119595T
Other languages
English (en)
Inventor
Eduard Dipl-Ing Fh Zwack
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of ES2048188T3 publication Critical patent/ES2048188T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

EL CIRCUITO REGLADOR DE FASE ESTA FORMADO A TRAVES LA CONEXION DE SERIE DE UN CONTADOR (ZS),DE UN REGISTRO (R) DE UNA INSTALACION ARITMETICA (AE), DE UN FILTRO DE PASO BAJA FRECUENCIA O DE (TP, PIF) TANTO COMO UN OSCILADOR GOBERNADO POR TENSION (VCO). LAS SEÑALES RITMICAS (ITS) INTERNAS, DIGITALES PRODUCIDAS DEL OSCILADOR (VCO), SE CUENTA EN UN CONTADOR Y EN TIEMPO DETERMINADOS A TRAVES SEÑALES RITMICAS DE INTERVALOS DE TIEMPO (ZTS), SE RECIBE Y ACUMULA LAS CUALES COMO VALOR DEL CONTADOR EN EL REGISTRO (R). LAS SEÑALES RITMICAS DE INTERVALOS DE TIEMPO (ZTS) SE CONSIGUE, POR EJEMPLO POR MEDIO DE UNA INSTALACION DE DIVISIONAR (DIV) DESDE SEÑALES RITMICAS DE REFERENCIA (NTS), Y MUESTRAN UNA FRECUENCIA MAS BAJA QUE LAS SEÑALES RITMICAS (ITS) INTERNAS. EN LA INSTALACION ARITMETICA (AE) SE AVERIGUA POR MEDIO DEL VALOR DEL CONTADOR ACTUAL DEL VALOR DEL CONTADOR DEL INTERVALO ANALIZADOR ANTERIOR Y UN VALOR DE REGIMEN, UNA SEÑAL DE MANDO (AS) EN FORMA DIGITAL. ESTA SEÑAL DE MANDO (AS) LLEGA SOBRE UN FILTRO DE PASO BAJA FRECUENCIA Y DE (TP, PIF) Y UN TRANSFORMADOR-A/D (AD) A LA ENTRADA DE MANDO (SE) DEL OSCILADOR (VCO) Y GOBERNA EL CUAL DE TAL MODO, AUE LAS SEÑALES RITMICAS DE REFERENCIA (NTS) COINCIDE EN RESPECTO A SU FASE CON LAS SEÑALES RITMICAS INTERNAS (ITS),
ES88119595T 1987-12-22 1988-11-24 Procedimiento para la determinacion de una tension de activacion de un oscilador controlado por tension en un circuito regulador de fases. Expired - Lifetime ES2048188T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3743631 1987-12-22

Publications (1)

Publication Number Publication Date
ES2048188T3 true ES2048188T3 (es) 1994-03-16

Family

ID=6343316

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88119595T Expired - Lifetime ES2048188T3 (es) 1987-12-22 1988-11-24 Procedimiento para la determinacion de una tension de activacion de un oscilador controlado por tension en un circuito regulador de fases.

Country Status (6)

Country Link
US (1) US4864253A (es)
EP (1) EP0321725B1 (es)
AT (1) ATE100982T1 (es)
DE (1) DE3887486D1 (es)
ES (1) ES2048188T3 (es)
FI (1) FI91820C (es)

Families Citing this family (21)

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Publication number Priority date Publication date Assignee Title
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
JP2554705B2 (ja) * 1988-04-25 1996-11-13 三菱電機株式会社 位相同期回路
US5055800A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Fractional n/m synthesis
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
CA2130871C (en) * 1993-11-05 1999-09-28 John M. Alder Method and apparatus for a phase-locked loop circuit with holdover mode
US5457428A (en) * 1993-12-09 1995-10-10 At&T Corp. Method and apparatus for the reduction of time interval error in a phase locked loop circuit
KR970001855B1 (ko) * 1994-06-30 1997-02-17 현대전자산업 주식회사 저속 데이타 전용 단말지구국의 기준 발진기 제어장치
JPH0879059A (ja) * 1994-08-31 1996-03-22 Aiwa Co Ltd 基準クロック発生回路
US5552750A (en) * 1995-09-05 1996-09-03 Motorola, Inc. Method and apparatus for determining an instantaneous phase difference between two signals
DK132895A (da) * 1995-11-24 1997-05-25 Dsc Communications As Fremgangsmåde til regulering af et digitalt faselåst kredsløb, og et digitalt faselåst kredsløb med en spændingsstyret oscillator
US5926515A (en) * 1995-12-26 1999-07-20 Samsung Electronics Co., Ltd. Phase locked loop for improving a phase locking time
US5886583A (en) * 1996-03-26 1999-03-23 Nec Corporation Oscillator control circuit including a phase difference change-detecting circuit
FR2756685A1 (fr) * 1996-12-03 1998-06-05 Philips Electronics Nv Synthetiseur de frequence programmable a faible sensibilite au bruit de phase
DE19653129C2 (de) * 1996-12-19 1999-01-28 Siemens Ag Verfahren zum Erzeugen eines Ansteuersignals für einen spannungsgesteuerten Oszillator in einem Phasenregelkreis
WO2000043849A2 (de) * 1999-01-21 2000-07-27 Infineon Technologies Ag Elektronischer phasenregelkreis (pll)
US6124764A (en) * 1999-01-22 2000-09-26 Telefonaktiebolaget Lm Ericsson Stable low-power oscillator
DE10042587B4 (de) * 2000-08-30 2007-04-12 Infineon Technologies Ag Filteranordnung und Verfahren zur Filterung eines Analogsignals
US6459253B1 (en) * 2000-09-05 2002-10-01 Telefonaktiebolaget Lm Ericsson (Publ) Bandwidth calibration for frequency locked loop
US7242229B1 (en) 2001-05-06 2007-07-10 Altera Corporation Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
US7663415B2 (en) * 2005-12-30 2010-02-16 Stmicroelectronics Pvt. Ltd. Phase locked loop (PLL) method and architecture
US11283586B1 (en) 2020-09-05 2022-03-22 Francis Tiong Method to estimate and compensate for clock rate difference in acoustic sensors

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1762746A1 (de) * 1967-08-21 1970-08-20 Synchron Druzstov Pro Vyvoj A Verfahren zur Syntonisation genauer Oszillatoren und Anordnung zum Durchfuehren dieses Verfahrens
DE2735011B1 (de) * 1977-08-03 1978-03-16 Siemens Ag Schaltungsanordnung zum UEberwachen von Eingangssignalen eines Phasenregelkreises
DE2735053C3 (de) * 1977-08-03 1980-05-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Digitaler Phasenregelkreis
FR2484104A1 (fr) * 1980-06-06 1981-12-11 Chomette Andre Boucle d'asservissement a microprocesseur
DE3025358A1 (de) * 1980-07-04 1982-01-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Regelsystem zum einstellen einer physikalischen groesse
US4418318A (en) * 1981-03-10 1983-11-29 Frederick Electronics Corporation Digital phase-locked loop circuit
US4458214A (en) * 1981-09-28 1984-07-03 The Bendix Corporation Fast sampling phase locked loop frequency synthesizer
FR2546691B1 (fr) * 1983-05-27 1985-07-05 Cit Alcatel Base de temps asservie

Also Published As

Publication number Publication date
US4864253A (en) 1989-09-05
ATE100982T1 (de) 1994-02-15
FI885908A (fi) 1989-06-23
DE3887486D1 (de) 1994-03-10
EP0321725A2 (de) 1989-06-28
FI91820B (fi) 1994-04-29
EP0321725A3 (en) 1990-04-25
FI91820C (fi) 1994-08-10
EP0321725B1 (de) 1994-01-26

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