ES2044872T3 - Memoria semicionductora. - Google Patents
Memoria semicionductora.Info
- Publication number
- ES2044872T3 ES2044872T3 ES87108924T ES87108924T ES2044872T3 ES 2044872 T3 ES2044872 T3 ES 2044872T3 ES 87108924 T ES87108924 T ES 87108924T ES 87108924 T ES87108924 T ES 87108924T ES 2044872 T3 ES2044872 T3 ES 2044872T3
- Authority
- ES
- Spain
- Prior art keywords
- trench
- longitudinal axis
- disposed
- major surface
- storage means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
Landscapes
- Semiconductor Memories (AREA)
- Micro-Organisms Or Cultivation Processes Thereof (AREA)
- Semiconductor Integrated Circuits (AREA)
- Medicines Containing Material From Animals Or Micro-Organisms (AREA)
- Immobilizing And Processing Of Enzymes And Microorganisms (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Image Processing (AREA)
Abstract
UNA MEMORIA INCLUYE UN SUSTRATO DE SEMICONDUCTOR (26) QUE TIENE UNA SUPERFICIE PRINCIPAL Y UNA ZANJA (24) DISPUESTA EN SU INTERIOR, QUE TIENE UN EJE LONGITUDINAL, MEDIOS DE ALMACENAMIENTO (16,16'') DISPUESTOS SOBRE UNA DETERMINADA PARED LATERAL DE LA ZANJA, MEDIOS DE INTERRUPCION (12,12'') QUE TIENEN UN ELEMENTO DE CONTROL Y UN ELEMENTO DE TRANSPORTE DE CORRIENTE DISPUESTO SOBRE LA PARED LATERAL DE DICHA ZANJA ENTRE LOS MEDIOS DE ALMACENAMIENTO Y LA SUPERFICIE PRINCIPAL DEL SUSTRATO, Y ACOPLADOS A LOS MEDIOS DE ALMACENAMIENTO UNA PRIMERA LINEA ELECTRICA CONDUCTORA (40,40'') DISPUESTA SOBRE DICHA PARED LATERAL EN CONTACTO CON EL ELEMENTO DE CONTROL Y TIENE UN EJE LONITUDINAL DISPUESTO PARALELAMENTE AL EJE DE LA ZANJA, Y UNA SEGUNDA LINEA CONDUCTORA (22,22'') DISPUESTA SOBRE LA SUPERFICIE PRINCIPAL DEL SUSTRATO CONDUCTOR EN CONTACTO CON EL ELECTRODO QUE TRANSPORTA LA CORRIENTE DESDE LOS MEDIOS DE INTERRUPCION Y TIENE UN EJE LONGITUDINAL DISPUESTO ORTOGONALMENTE AL EJE LONGITUDINAL DE LA ZANJA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/885,618 US4769786A (en) | 1986-07-15 | 1986-07-15 | Two square memory cells |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2044872T3 true ES2044872T3 (es) | 1994-01-16 |
Family
ID=25387321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES87108924T Expired - Lifetime ES2044872T3 (es) | 1986-07-15 | 1987-06-23 | Memoria semicionductora. |
Country Status (11)
Country | Link |
---|---|
US (1) | US4769786A (es) |
EP (1) | EP0254046B1 (es) |
JP (1) | JPH07101731B2 (es) |
AT (1) | ATE95632T1 (es) |
AU (1) | AU594169B2 (es) |
BR (1) | BR8703296A (es) |
CA (1) | CA1283480C (es) |
DE (1) | DE3787687T2 (es) |
DK (1) | DK365487A (es) |
ES (1) | ES2044872T3 (es) |
NO (1) | NO172714C (es) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0682800B2 (ja) * | 1985-04-16 | 1994-10-19 | 株式会社東芝 | 半導体記憶装置 |
US4751558A (en) * | 1985-10-31 | 1988-06-14 | International Business Machines Corporation | High density memory with field shield |
US4811067A (en) * | 1986-05-02 | 1989-03-07 | International Business Machines Corporation | High density vertically structured memory |
USRE33972E (en) * | 1986-07-15 | 1992-06-23 | International Business Machines Corporation | Two square memory cells |
JPS63245954A (ja) * | 1987-04-01 | 1988-10-13 | Hitachi Ltd | 半導体メモリ |
US4812885A (en) * | 1987-08-04 | 1989-03-14 | Texas Instruments Incorporated | Capacitive coupling |
US5109259A (en) * | 1987-09-22 | 1992-04-28 | Texas Instruments Incorporated | Multiple DRAM cells in a trench |
JPH01125858A (ja) * | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JPH07105477B2 (ja) * | 1988-05-28 | 1995-11-13 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5008214A (en) * | 1988-06-03 | 1991-04-16 | Texas Instruments Incorporated | Method of making crosspoint dynamic RAM cell array with overlapping wordlines and folded bitlines |
US4926224A (en) * | 1988-06-03 | 1990-05-15 | Texas Instruments Incorporated | Crosspoint dynamic ram cell for folded bitline array |
US4977436A (en) * | 1988-07-25 | 1990-12-11 | Motorola, Inc. | High density DRAM |
US5001525A (en) * | 1989-03-27 | 1991-03-19 | International Business Machines Corporation | Two square memory cells having highly conductive word lines |
US4989055A (en) * | 1989-06-15 | 1991-01-29 | Texas Instruments Incorporated | Dynamic random access memory cell |
US5064777A (en) * | 1990-06-28 | 1991-11-12 | International Business Machines Corporation | Fabrication method for a double trench memory cell device |
US5034787A (en) * | 1990-06-28 | 1991-07-23 | International Business Machines Corporation | Structure and fabrication method for a double trench memory cell device |
US5365097A (en) * | 1992-10-05 | 1994-11-15 | International Business Machines Corporation | Vertical epitaxial SOI transistor, memory cell and fabrication methods |
US5641694A (en) * | 1994-12-22 | 1997-06-24 | International Business Machines Corporation | Method of fabricating vertical epitaxial SOI transistor |
US6074909A (en) * | 1998-07-31 | 2000-06-13 | Siemens Aktiengesellschaft | Apparatus and method for forming controlled deep trench top isolation layers |
US6730540B2 (en) * | 2002-04-18 | 2004-05-04 | Tru-Si Technologies, Inc. | Clock distribution networks and conductive lines in semiconductor integrated circuits |
US20070082454A1 (en) * | 2005-10-12 | 2007-04-12 | Infineon Technologies Ag | Microelectronic device and method of manufacturing a microelectronic device |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387286A (en) * | 1967-07-14 | 1968-06-04 | Ibm | Field-effect transistor memory |
US3811076A (en) * | 1973-01-02 | 1974-05-14 | Ibm | Field effect transistor integrated circuit and memory |
US3841926A (en) * | 1973-01-02 | 1974-10-15 | Ibm | Integrated circuit fabrication process |
US4225945A (en) * | 1976-01-12 | 1980-09-30 | Texas Instruments Incorporated | Random access MOS memory cell using double level polysilicon |
US4222062A (en) * | 1976-05-04 | 1980-09-09 | American Microsystems, Inc. | VMOS Floating gate memory device |
US4462040A (en) * | 1979-05-07 | 1984-07-24 | International Business Machines Corporation | Single electrode U-MOSFET random access memory |
US4271418A (en) * | 1979-10-29 | 1981-06-02 | American Microsystems, Inc. | VMOS Memory cell and method for making same |
JPS5681968A (en) * | 1979-12-07 | 1981-07-04 | Toshiba Corp | Manufacture of semiconductor device |
US4295924A (en) * | 1979-12-17 | 1981-10-20 | International Business Machines Corporation | Method for providing self-aligned conductor in a V-groove device |
US4335450A (en) * | 1980-01-30 | 1982-06-15 | International Business Machines Corporation | Non-destructive read out field effect transistor memory cell system |
KR920010461B1 (ko) * | 1983-09-28 | 1992-11-28 | 가부시끼가이샤 히다찌세이사꾸쇼 | 반도체 메모리와 그 제조 방법 |
JPS60136378A (ja) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH0648719B2 (ja) * | 1984-01-20 | 1994-06-22 | 株式会社日立製作所 | 半導体記憶装置 |
DE3565339D1 (en) * | 1984-04-19 | 1988-11-03 | Nippon Telegraph & Telephone | Semiconductor memory device and method of manufacturing the same |
US4672410A (en) * | 1984-07-12 | 1987-06-09 | Nippon Telegraph & Telephone | Semiconductor memory device with trench surrounding each memory cell |
US4673962A (en) * | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
JPH0682800B2 (ja) * | 1985-04-16 | 1994-10-19 | 株式会社東芝 | 半導体記憶装置 |
JPH0680805B2 (ja) * | 1985-05-29 | 1994-10-12 | 日本電気株式会社 | Mis型半導体記憶装置 |
US4673963A (en) * | 1985-08-27 | 1987-06-16 | Texas Instruments Incorporated | High well capacity CCD imager |
-
1986
- 1986-07-15 US US06/885,618 patent/US4769786A/en not_active Ceased
-
1987
- 1987-05-18 JP JP62119156A patent/JPH07101731B2/ja not_active Expired - Lifetime
- 1987-06-23 ES ES87108924T patent/ES2044872T3/es not_active Expired - Lifetime
- 1987-06-23 AT AT87108924T patent/ATE95632T1/de not_active IP Right Cessation
- 1987-06-23 DE DE87108924T patent/DE3787687T2/de not_active Expired - Fee Related
- 1987-06-23 EP EP87108924A patent/EP0254046B1/en not_active Expired - Lifetime
- 1987-06-29 BR BR8703296A patent/BR8703296A/pt not_active IP Right Cessation
- 1987-06-29 NO NO872721A patent/NO172714C/no unknown
- 1987-07-06 AU AU75248/87A patent/AU594169B2/en not_active Ceased
- 1987-07-07 CA CA000541434A patent/CA1283480C/en not_active Expired - Fee Related
- 1987-07-14 DK DK365487A patent/DK365487A/da not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
AU7524887A (en) | 1988-01-21 |
JPS6321866A (ja) | 1988-01-29 |
DK365487A (da) | 1988-01-16 |
US4769786A (en) | 1988-09-06 |
AU594169B2 (en) | 1990-03-01 |
DK365487D0 (da) | 1987-07-14 |
EP0254046A1 (en) | 1988-01-27 |
CA1283480C (en) | 1991-04-23 |
NO172714B (no) | 1993-05-18 |
DE3787687D1 (de) | 1993-11-11 |
NO872721D0 (no) | 1987-06-29 |
ATE95632T1 (de) | 1993-10-15 |
DE3787687T2 (de) | 1994-05-05 |
JPH07101731B2 (ja) | 1995-11-01 |
BR8703296A (pt) | 1988-03-15 |
NO872721L (no) | 1988-01-18 |
EP0254046B1 (en) | 1993-10-06 |
NO172714C (no) | 1993-08-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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