ES2035027T3 - Sistema de computador que tiene arbitraje de acceso directo a memoria de canales multiples. - Google Patents
Sistema de computador que tiene arbitraje de acceso directo a memoria de canales multiples.Info
- Publication number
- ES2035027T3 ES2035027T3 ES198787118545T ES87118545T ES2035027T3 ES 2035027 T3 ES2035027 T3 ES 2035027T3 ES 198787118545 T ES198787118545 T ES 198787118545T ES 87118545 T ES87118545 T ES 87118545T ES 2035027 T3 ES2035027 T3 ES 2035027T3
- Authority
- ES
- Spain
- Prior art keywords
- dma
- channel
- computer system
- direct access
- multiple channels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
UN SISTEMA DE ORDENADOR EN EL QUE EL NUMERO DE CANALES PERIFERICOS ES MAS GRANDE QUE EL NUMERO DE CANALES DMA PROVISTOS EN EL SISTEMA PUEDEN TODOS TENER ACCESO DMA. ALGUNO DE LOS CANALES DMA ESTAN DERIVADOS A UNOS DE LOS PERIFERICOS, MIENTRAS OTROS SON COMPARTIDOS PARA PERMANECER CON UNO DE LOS PERIFERICOS. CADA PERIFERIA QUE TIENEN ACCESO DMA TIENE UN VALOR PRIORITARIO DEL CANAL. CUANDO UN PERIFERIO QUIERE ACCESO DMA, TRANSMITE SU VALOR PRIORITARIO DE CANAL HACIA UN BUS DE ARBITRAJE. EL VALOR PRIORITARIO DE CANAL GANADO ES ENTONCES COMPARADO CON LOS VALORES DE ASIGNACION DE CANAL DMA PRESTADO. SI LA COMPARACION ES AFORTUNADA, EL PERIFERIO CORRESPONDIENTE AL VALOR DE ASIGNACION DE CANAL DMA CON EL QUE LA COMPARACION FUE AFORTUNADA
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/030,786 US4901234A (en) | 1987-03-27 | 1987-03-27 | Computer system having programmable DMA control |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2035027T3 true ES2035027T3 (es) | 1993-04-16 |
Family
ID=21856024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES198787118545T Expired - Lifetime ES2035027T3 (es) | 1987-03-27 | 1987-12-15 | Sistema de computador que tiene arbitraje de acceso directo a memoria de canales multiples. |
Country Status (17)
Country | Link |
---|---|
US (1) | US4901234A (es) |
EP (1) | EP0288607B1 (es) |
JP (1) | JPS63244158A (es) |
KR (1) | KR950008227B1 (es) |
CN (1) | CN1013068B (es) |
AR (1) | AR240681A1 (es) |
AT (1) | ATE81220T1 (es) |
BE (1) | BE1000819A3 (es) |
DE (3) | DE3782045T2 (es) |
ES (1) | ES2035027T3 (es) |
FR (1) | FR2613095A1 (es) |
GB (1) | GB2202977B (es) |
GR (1) | GR3006676T3 (es) |
HK (2) | HK33692A (es) |
IT (1) | IT1216132B (es) |
NL (1) | NL185106C (es) |
SG (1) | SG13092G (es) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5185864A (en) * | 1989-06-16 | 1993-02-09 | International Business Machines Corporation | Interrupt handling for a computing system with logical devices and interrupt reset |
US5307468A (en) * | 1989-08-23 | 1994-04-26 | Digital Equipment Corporation | Data processing system and method for controlling the latter as well as a CPU board |
DE3928481C2 (de) * | 1989-08-29 | 1994-09-22 | Diehl Gmbh & Co | Prioritätsorientiertes dezentrales Busvergabesystem |
EP0453863A2 (en) * | 1990-04-27 | 1991-10-30 | National Semiconductor Corporation | Methods and apparatus for implementing a media access control/host system interface |
US5519684A (en) * | 1990-05-14 | 1996-05-21 | Casio Computer Co., Ltd. | Digital recorder for processing in parallel data stored in multiple tracks |
US5974015A (en) * | 1990-05-14 | 1999-10-26 | Casio Computer Co., Ltd. | Digital recorder |
EP0473280B1 (en) * | 1990-08-31 | 1996-04-17 | Advanced Micro Devices, Inc. | Communication control system for a computer and peripheral devices |
US5581530A (en) * | 1990-09-06 | 1996-12-03 | Casio Computer Co., Ltd. | Digital recorder for processing of parallel data stored in multiple tracks and using cross-fade processing |
WO1992015060A1 (en) * | 1991-02-19 | 1992-09-03 | International Business Machines Corporation | Channel selection arbitration |
US5530901A (en) * | 1991-11-28 | 1996-06-25 | Ricoh Company, Ltd. | Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively |
US6026443A (en) * | 1992-12-22 | 2000-02-15 | Sun Microsystems, Inc. | Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface |
US5640598A (en) * | 1994-07-12 | 1997-06-17 | Mitsubishi Denki Kabushiki Kaisha | Data transfer processing system |
US5495614A (en) * | 1994-12-14 | 1996-02-27 | International Business Machines Corporation | Interface control process between using programs and shared hardware facilities |
JP3320233B2 (ja) * | 1995-02-06 | 2002-09-03 | キヤノン株式会社 | 記録装置 |
US5664197A (en) * | 1995-04-21 | 1997-09-02 | Intel Corporation | Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller |
US5761534A (en) * | 1996-05-20 | 1998-06-02 | Cray Research, Inc. | System for arbitrating packetized data from the network to the peripheral resources and prioritizing the dispatching of packets onto the network |
US6154793A (en) * | 1997-04-30 | 2000-11-28 | Zilog, Inc. | DMA with dynamically assigned channels, flexible block boundary notification and recording, type code checking and updating, commands, and status reporting |
US6092137A (en) * | 1997-11-26 | 2000-07-18 | Industrial Technology Research Institute | Fair data bus arbitration system which assigns adjustable priority values to competing sources |
US6473780B1 (en) * | 1998-04-01 | 2002-10-29 | Intel Corporation | Scheduling of direct memory access |
US6260081B1 (en) * | 1998-11-24 | 2001-07-10 | Advanced Micro Devices, Inc. | Direct memory access engine for supporting multiple virtual direct memory access channels |
US7089344B1 (en) * | 2000-06-09 | 2006-08-08 | Motorola, Inc. | Integrated processor platform supporting wireless handheld multi-media devices |
JP2003006003A (ja) * | 2001-06-18 | 2003-01-10 | Mitsubishi Electric Corp | Dmaコントローラおよび半導体集積回路 |
JP4245852B2 (ja) * | 2002-03-19 | 2009-04-02 | 富士通マイクロエレクトロニクス株式会社 | ダイレクトメモリアクセス装置 |
US7062582B1 (en) * | 2003-03-14 | 2006-06-13 | Marvell International Ltd. | Method and apparatus for bus arbitration dynamic priority based on waiting period |
US20050038946A1 (en) * | 2003-08-12 | 2005-02-17 | Tadpole Computer, Inc. | System and method using a high speed interface in a system having co-processors |
US7533195B2 (en) * | 2004-02-25 | 2009-05-12 | Analog Devices, Inc. | DMA controller for digital signal processors |
US7240129B2 (en) * | 2004-02-25 | 2007-07-03 | Analog Devices, Inc. | DMA controller having programmable channel priority |
US7130982B2 (en) * | 2004-03-31 | 2006-10-31 | International Business Machines Corporation | Logical memory tags for redirected DMA operations |
US8006001B2 (en) * | 2004-09-22 | 2011-08-23 | Lsi Corporation | Method and apparatus for manipulating direct memory access transfers |
US7386642B2 (en) * | 2005-01-28 | 2008-06-10 | Sony Computer Entertainment Inc. | IO direct memory access system and method |
US7680972B2 (en) * | 2005-02-04 | 2010-03-16 | Sony Computer Entertainment Inc. | Micro interrupt handler |
JP2006216042A (ja) * | 2005-02-04 | 2006-08-17 | Sony Computer Entertainment Inc | 割り込み処理のためのシステムおよび方法 |
US7483422B2 (en) * | 2005-02-10 | 2009-01-27 | International Business Machines Corporation | Data processing system, method and interconnect fabric for selective link information allocation in a data processing system |
US7395361B2 (en) * | 2005-08-19 | 2008-07-01 | Qualcomm Incorporated | Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth |
US20090259789A1 (en) * | 2005-08-22 | 2009-10-15 | Shuhei Kato | Multi-processor, direct memory access controller, and serial data transmitting/receiving apparatus |
JP4499008B2 (ja) * | 2005-09-15 | 2010-07-07 | 富士通マイクロエレクトロニクス株式会社 | Dma転送システム |
US7689732B2 (en) * | 2006-02-24 | 2010-03-30 | Via Technologies, Inc. | Method for improving flexibility of arbitration of direct memory access (DMA) engines requesting access to shared DMA channels |
CN106294233B (zh) * | 2015-06-29 | 2019-05-03 | 华为技术有限公司 | 一种直接内存访问的传输控制方法及装置 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE622921A (es) * | 1961-10-06 | |||
US3766526A (en) * | 1972-10-10 | 1973-10-16 | Atomic Energy Commission | Multi-microprogrammed input-output processor |
IT971304B (it) * | 1972-11-29 | 1974-04-30 | Honeywell Inf Systems | Sistema di accesso a priorita variabile dinamicamente |
US4075691A (en) * | 1975-11-06 | 1978-02-21 | Bunker Ramo Corporation | Communication control unit |
US4400771A (en) * | 1975-12-04 | 1983-08-23 | Tokyo Shibaura Electric Co., Ltd. | Multi-processor system with programmable memory-access priority control |
US4090238A (en) * | 1976-10-04 | 1978-05-16 | Rca Corporation | Priority vectored interrupt using direct memory access |
US4257095A (en) * | 1978-06-30 | 1981-03-17 | Intel Corporation | System bus arbitration, circuitry and methodology |
US4437157A (en) * | 1978-07-20 | 1984-03-13 | Sperry Corporation | Dynamic subchannel allocation |
US4558412A (en) * | 1978-12-26 | 1985-12-10 | Honeywell Information Systems Inc. | Direct memory access revolving priority apparatus |
CA1132265A (en) * | 1978-12-26 | 1982-09-21 | Minoru Inoshita | Direct memory access revolving priority apparatus |
US4281381A (en) * | 1979-05-14 | 1981-07-28 | Bell Telephone Laboratories, Incorporated | Distributed first-come first-served bus allocation apparatus |
US4371932A (en) * | 1979-07-30 | 1983-02-01 | International Business Machines Corp. | I/O Controller for transferring data between a host processor and multiple I/O units |
US4516199A (en) * | 1979-10-11 | 1985-05-07 | Nanodata Computer Corporation | Data processing system |
IT1209338B (it) * | 1980-07-24 | 1989-07-16 | Sits Soc It Telecom Siemens | Disposizione circuitale per il trasferimento di dati tra la memoria di un elaboratore elettronico e le unita' di interfaccia delle periferiche ad esso collegate. |
JPS58223833A (ja) * | 1982-06-23 | 1983-12-26 | Fujitsu Ltd | ダイレクト・メモリ・アクセス制御方式 |
US4528626A (en) * | 1984-03-19 | 1985-07-09 | International Business Machines Corporation | Microcomputer system with bus control means for peripheral processing devices |
US4688166A (en) * | 1984-08-03 | 1987-08-18 | Motorola Computer Systems, Inc. | Direct memory access controller supporting multiple input/output controllers and memory units |
JPS61131153A (ja) * | 1984-11-30 | 1986-06-18 | Toshiba Corp | Dma転送制御方式 |
JPS61133461A (ja) * | 1984-12-04 | 1986-06-20 | Fujitsu Ltd | Dma転送制御方式 |
US4847750A (en) * | 1986-02-13 | 1989-07-11 | Intelligent Instrumentation, Inc. | Peripheral DMA controller for data acquisition system |
-
1987
- 1987-03-27 US US07/030,786 patent/US4901234A/en not_active Expired - Lifetime
- 1987-11-27 FR FR8716750A patent/FR2613095A1/fr not_active Withdrawn
- 1987-12-04 BE BE8701395A patent/BE1000819A3/fr not_active IP Right Cessation
- 1987-12-10 GB GB8728927A patent/GB2202977B/en not_active Revoked
- 1987-12-15 DE DE8787118545T patent/DE3782045T2/de not_active Expired - Fee Related
- 1987-12-15 ES ES198787118545T patent/ES2035027T3/es not_active Expired - Lifetime
- 1987-12-15 AT AT87118545T patent/ATE81220T1/de not_active IP Right Cessation
- 1987-12-15 EP EP87118545A patent/EP0288607B1/en not_active Expired - Lifetime
- 1987-12-25 JP JP62327583A patent/JPS63244158A/ja active Granted
-
1988
- 1988-02-25 CN CN88100962A patent/CN1013068B/zh not_active Expired
- 1988-02-27 KR KR1019880002038A patent/KR950008227B1/ko not_active IP Right Cessation
- 1988-03-18 IT IT8819827A patent/IT1216132B/it active
- 1988-03-23 AR AR31037988A patent/AR240681A1/es active
- 1988-03-23 NL NLAANVRAGE8800715,A patent/NL185106C/xx not_active IP Right Cessation
- 1988-03-25 DE DE8804104U patent/DE8804104U1/de not_active Expired
- 1988-03-25 DE DE3810231A patent/DE3810231A1/de active Granted
-
1992
- 1992-02-11 SG SG130/92A patent/SG13092G/en unknown
- 1992-05-07 HK HK336/92A patent/HK33692A/xx unknown
- 1992-12-24 GR GR920403114T patent/GR3006676T3/el unknown
-
1997
- 1997-09-24 HK HK97101822A patent/HK1000295A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
NL8800715A (nl) | 1988-10-17 |
HK33692A (en) | 1992-05-15 |
JPS63244158A (ja) | 1988-10-11 |
KR950008227B1 (ko) | 1995-07-26 |
IT1216132B (it) | 1990-02-22 |
EP0288607B1 (en) | 1992-09-30 |
GR3006676T3 (es) | 1993-06-30 |
DE8804104U1 (de) | 1988-06-30 |
JPH0467224B2 (es) | 1992-10-27 |
GB8728927D0 (en) | 1988-01-27 |
IT8819827A0 (it) | 1988-03-18 |
AR240681A1 (es) | 1990-08-31 |
BE1000819A3 (fr) | 1989-04-11 |
KR880011675A (ko) | 1988-10-29 |
GB2202977A (en) | 1988-10-05 |
NL185106B (nl) | 1989-08-16 |
SG13092G (en) | 1992-04-16 |
NL185106C (nl) | 1990-01-16 |
FR2613095A1 (fr) | 1988-09-30 |
DE3782045D1 (de) | 1992-11-05 |
CN1013068B (zh) | 1991-07-03 |
DE3782045T2 (de) | 1993-04-15 |
US4901234A (en) | 1990-02-13 |
HK1000295A1 (en) | 1998-02-20 |
ATE81220T1 (de) | 1992-10-15 |
GB2202977B (en) | 1991-07-24 |
CN88100962A (zh) | 1988-12-14 |
DE3810231A1 (de) | 1988-10-06 |
DE3810231C2 (es) | 1989-10-26 |
EP0288607A1 (en) | 1988-11-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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