EP3977519A1 - Leistungstransistorzelle und leistungstransistor - Google Patents

Leistungstransistorzelle und leistungstransistor

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Publication number
EP3977519A1
EP3977519A1 EP20727950.6A EP20727950A EP3977519A1 EP 3977519 A1 EP3977519 A1 EP 3977519A1 EP 20727950 A EP20727950 A EP 20727950A EP 3977519 A1 EP3977519 A1 EP 3977519A1
Authority
EP
European Patent Office
Prior art keywords
power transistor
areas
regions
trench
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20727950.6A
Other languages
German (de)
English (en)
French (fr)
Inventor
Klaus Heyers
Alberto MARTINEZ-LIMIA
Jan-Hendrik Alsmeier
Wolfgang Feiler
Stephan Schwaiger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3977519A1 publication Critical patent/EP3977519A1/de
Withdrawn legal-status Critical Current

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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
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    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0843Source or drain regions of field-effect devices
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    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
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    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/1608Silicon carbide
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0692Surface layout
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    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the invention relates to a power transistor cell and a power transistor.
  • Silicon carbide transistors are used for applications in which a high blocking strength and a low forward resistance are required at the same time. These are those that occur with a high reverse voltage
  • Document US 7,700,971 B2 describes p-doped regions arranged in the drift region, arranged at regular intervals in a horizontal direction and located below a trench MOSFET structure, being connected to the source potential via a contact structure.
  • the source regions of the component are arranged laterally next to the trenches, while the contact structures are realized by metallizing the surface of an exposed part of the buried p-regions that lie outside the gate-trench structure regions after the SiC material has been etched.
  • the document US 9306061 A describes a p-doped region arranged in the drift region, which is connected to the source potential via a contact region is.
  • the source regions and the contact regions are arranged laterally next to the trenches, the contact regions crossing or piercing the source regions.
  • the source areas directly adjoin the trenches at the side.
  • the contact regions are arranged laterally spaced apart from the trenches and touch the source regions. The sequence of the source regions and the contact regions remains along the length of the trenches
  • the disadvantage here is that the lateral dimensions of the power transistor are large transversely to the longitudinal extension of the trenches.
  • the object of the invention is to overcome these disadvantages.
  • the power transistor cell comprises a layer arrangement which has a front side and a rear side. The front is opposite the back. Starting from the front side, a trench extends along a first direction into the layer arrangement and extends at least into a current spreading layer. The trench extends along a second direction that is perpendicular to the first direction. Field shielding areas are arranged at least in some areas in the current spreading layer.
  • source regions and field shield contact regions are arranged alternately along the second direction, a part or strip of the body region being arranged between each source region and each field shield contact region.
  • Field shielding contact areas connect the field shielding areas to first metal areas on the front side, the
  • Field shielding contact areas touch side surfaces of the trench at least in areas.
  • the source regions and the field shield contact regions are arranged alternately in the direction of propagation of the trench, the source regions and the
  • Field shielding contact areas indirectly follow one another. That means they are each separated from one another by a part or strip of the body area.
  • the source areas in this case extend from one trench to the next trench along a third direction which is arranged perpendicular to the first direction and to the second direction, at least in regions without interruption.
  • the advantage here is that the dimensions of the power transistor cell are small.
  • the field shielding areas are within the
  • the advantage here is that high vertical and lateral current conduction is possible with a low switch-on resistance.
  • the field shielding areas are at a greater distance from the front side than a floor of the trench. In other words, viewed from the front, they are lower than the bottom of the trench.
  • the current spreading layer is lateral to the
  • the advantage here is that the current flow is not impaired by the field shielding areas, since the field shielding areas are at a lateral distance from the trench.
  • the current spreading layer is designed to be rectangular laterally to the field shielding areas.
  • body contact areas are arranged within the body areas in areas below the source areas, the body contact areas being connected to the first metal areas of the front side of the layer arrangement via the field shielding contact areas.
  • the advantage here is that body contact is improved. That means the behavior of the flyback diode improves.
  • the field shielding areas are rounded in the direction of the trench and / or the rear.
  • the layer arrangement comprises a
  • the semiconductor substrate has silicon carbide or
  • Gallium nitride Gallium nitride
  • the power transistor according to the invention comprises a plurality of
  • Power transistor cells which have a layer arrangement with a front side and a rear side. The front is opposite the back. Starting from the front side, a trench extends along a first direction into the layer arrangement and extends at least into one Current spreading layer. The trench extends along a second direction that is perpendicular to the first direction. Field shielding areas are arranged at least in some areas in the current spreading layer.
  • source regions and field shield contact regions are arranged alternately along the second direction, a part or strip of the body region being arranged between each source region and each field shield contact region.
  • Field shielding contact areas connect the field shielding areas to first metal areas on the front side, the
  • Field shielding contact areas touch side surfaces of the trench at least in areas.
  • the advantage here is that the power transistor has a low pitch, which reduces the forward resistance.
  • Figure la is a plan view of a power transistor cell
  • FIG. 1b shows a detail of a sectional view along a plane AA 'of the power transistor cell
  • Figure lc shows a detail of a sectional view along the plane BB ' of
  • FIG. 1d shows a sectional view along the plane CC 'in FIG
  • FIG. 2a shows a plan view of a front power transistor half cell
  • Figure 2b shows a sectional view along the plane AA ' through the front
  • Figure 2c shows a sectional view along the plane BB ‘through the front
  • FIG. 2d shows a rear view of the front power transistor half-cell
  • FIG. 3a shows a plan view of another front one
  • FIG. 3b shows a sectional view along the plane AA ' through the further front power transistor half-cell
  • FIG. 3c shows a sectional view along the plane BB ‘through the further front power transistor half-cell
  • Figure 3d shows a rear view of the further front
  • Figure 4a is a plan view of another front one
  • FIG. 4b shows a sectional view along the plane AA ' through the further front power transistor half-cell
  • FIG. 4c shows a sectional view along the plane BB ‘through the further front power transistor half-cell
  • Figure 4d is a rear view of the other front
  • Figure 5a is a plan view of another front
  • FIG. 5b shows a sectional view along plane AA ' through the further front power transistor half-cell
  • FIG. 5c shows a sectional view along plane BB' through the further front power transistor half-cell
  • Figure 5d is a rear view of the other front
  • Figure 6a is a plan view of another front one
  • FIG. 6b shows a sectional view along the plane AA ' through the further front power transistor half-cell
  • FIG. 6c shows a sectional view along the plane BB ‘through the further front power transistor half-cell
  • Figure 6d is a rear view of the other front
  • FIG. 7a shows a plan view of two power transistor cells
  • FIG. 7b shows a plan view of a further power transistor cell
  • FIG. 8a a first hexagonal cell geometry
  • FIG. 8b a second hexagonal cell geometry
  • FIG. 8c a third hexagonal cell geometry
  • FIG. 9a a first square cell geometry
  • FIG. 9b shows a second square cell geometry
  • FIG. 9c a third square cell geometry
  • Figure la shows a plan view of a power transistor cell 100. Die
  • Power transistor cell 100 comprises a front power transistor half-cell 102 and a rear power transistor half-cell 103, which are arranged one after the other along a second direction 107.
  • the power transistor half-cell 102 and the rear power transistor half-cell 103 are constructed identically, being arranged in a mirror-inverted manner along the second direction 107. This means the contacting surfaces of the front power transistor half cell 102 and the rear
  • Power transistor half cells 103 are the same.
  • the power transistor cell 100 comprises a layer arrangement 101.
  • the layer arrangement 101 comprises a semiconductor substrate 115, a buffer layer 116, a drift layer 117, a current spreading layer 106, field shielding regions 108, source regions 109, body regions 110 and field shielding contacting regions 111.
  • the buffer layer 116 is arranged on the semiconductor substrate 115 .
  • the drift layer 117 is arranged in the buffer layer 116.
  • the current spreading layer 106 is arranged on the drift layer 117.
  • Source regions 109 and body regions 110 are arranged in regions on current spreading layer 106.
  • first metal regions 112 for contacting the source regions 109 and the body regions 110 are arranged.
  • ohmic contacts are formed between the first metal regions 112 and the source regions 109 or the first
  • the field shielding regions 108 are arranged at least in regions in the current spreading layer 106. You are here via field shielding contact areas 111 with the first
  • a second metal region 114 is arranged below the semiconductor substrate 115. It acts as a drain metallization. An ohmic contact is formed between the semiconductor substrate 115 and the second metal region 114.
  • a trench 104 extends in a first direction 105 at least into the
  • the trench 104 expands in the second direction 107, which is arranged perpendicular to the first direction 105.
  • the second direction 107 corresponds to the direction of propagation or Longitudinal direction of the trench 104.
  • the trench 104 has a field oxide 118 on the bottom and a gate oxide 119 on the side walls.
  • the field oxide 118 can have a greater layer thickness than the gate oxide 119.
  • the trench 104 is made of a highly doped n- or p-polysilicon backfilled.
  • Source regions 109 and the field shield contact regions 111 are arranged alternately along the direction of propagation of the trench 104.
  • a strip-shaped part of the body region 110 is arranged in each case in the field shielding contact region 111. This means that along the length of the trench of a power transistor cell 100 there is a source region 109, a part of the body region 110, in the upper region of the trench
  • Field shielding contact region 111 part of a further body region 110 and a further source region 109 are arranged.
  • the source regions 109 and the body regions 110 directly adjoin the side wall of the trench 104.
  • the field shielding contact areas 111 likewise directly adjoin the side wall of the trench 104 in areas and touch the side wall of the trench 104. Furthermore, they border
  • the current spreading layer 106 and the drift layer 117 on the side walls of the trench 104 are different.
  • surfaces of the field shielding regions 108 are arranged at a smaller distance from the front side than the bottom of the trench 104, as seen from the front side of the layer arrangement 101.
  • the field shielding regions 108 here extend from the current spreading layer 106 into the drift layer 117.
  • the semiconductor substrate 115 is highly n-doped and the buffer layer 116 is n-doped.
  • the drift layer 117 and the current spreading layer 106 are n-doped, the current spreading layer 106 having a higher doping concentration than the drift layer 117. This leads to better current conduction below the channel region and thus to a low forward resistance.
  • Souce regions 109 are highly n-doped and the body regions 110 that
  • Field shielding regions 108 and the field shielding contact regions 111 are p-doped.
  • the semiconductor substrate 115 may include silicon, silicon carbide, gallium nitride, or gallium oxide.
  • the field shield contact areas 111 are made with the aid of
  • Figure lb shows a detail of a sectional view along a plane AA ' through the power transistor cell 100.
  • the detail shows the section along the plane AA ' through the front power transistor half-cell 102
  • Line AA ' is arranged parallel to the plane from the first direction
  • Drift layer 117 field oxide 118, gate metallization 120 and the first
  • Figure 1c shows a detail of a sectional view along a plane BB 'through the power transistor cell 100.
  • the detail shows the section along the plane BB ' through the front power transistor half-cell 102.
  • the plane BB ' is arranged parallel to the plane from the first direction 105 and the second direction 107 is spanned and runs along the third direction 121 laterally spaced between the trench 104 and the first metal layer 112.
  • Figure lc shows the second metal layer 114, the
  • the depth of the field shielding contact region 111 along the second direction 107 is indicated by the reference symbol WPz and the depth of the front
  • Power transistor half-cell 102 along the second direction 107 is identified by the reference symbol CPz.
  • Figure ld shows a sectional view along the plane CC ' of
  • Power transistor cell 100 The section shows the rear view of the front Power transistor half-cell 102 of power transistor cell 100.
  • the section through power transistor cell 100 is parallel to the plane that is spanned by first direction 105 and third direction 121. In the second direction 107, the section runs through the point half the length of the trench.
  • the reference symbols in FIG. 1d correspond to those in FIG. 1 a and describe the same components.
  • the field shield contact regions 111 and source regions 109 alternate along the direction of propagation of the trench 104. It can be seen that the field shielding contact regions 111 neither adjoin the source regions 109 nor pierce or traverse them.
  • FIG. 2a shows a top view of a front power transistor half-cell 202.
  • the two rear digits of the reference symbols in FIG. 2a which correspond to the same rear reference symbols in FIG. La, describe the same components as in FIG.
  • the difference from FIG. 1 a is that the field shielding regions 208 are at a greater distance from the front side of the layer arrangement 201 than the trench bottom. In other words, the field shielding regions 208, viewed from the front, lie lower than the trench bottom. This creates a field shield that is used on
  • Trench bottom has a field-reducing effect.
  • FIG. 2b shows a sectional view along the plane AA ' through the front power transistor half-cell 202 of the power transistor cell 200.
  • the two rear positions of the reference symbols in FIG. 2b which correspond to the same rear reference symbols in FIG. 1b, describe the same components as in FIG.
  • the difference from FIG. 1b is that in FIG. 2b the current spreading layer 206 is arranged between the drift layer 217 and the field oxide 218. In other words, the trench is completely in the current spreading layer 206.
  • FIG. 2c shows a sectional view along the plane BB 'through the front power transistor half-cell 202 of the power transistor cell 200.
  • the two rear positions of the reference numerals in FIG. 2c which correspond to the same rear reference numerals in FIG. 1c, describe the same components as in FIG.
  • the difference to the figure lc is that the Current spreading layer 206, starting from the front side of the layer arrangement, extends deeper into the layer arrangement 201. That is to say, with the same overall height as in FIG. 1c, the drift zone 217 has a lower height than the drift zone 117 in FIG. 1c.
  • FIG. 2d shows the rear view of the front power transistor half-cell 202.
  • the field shielding contact areas 211 have a gradual profile below the trench 204. That means they have an inhomogeneous depth in the first direction 205, if one considers the course of the boundary of the
  • Field shield contacting regions 211 to current spreading layer 206 along third direction 221 follows.
  • the current spreading layer 206 is bell-shaped or arrow-shaped.
  • the current spreading layer 206 becomes larger. This leads to better current conduction below the channel region in the vertical or first direction 205, in the lateral or second direction 207 and the third direction 221.
  • Figure 3a shows a plan view of another front one
  • Power transistor half-cell 302. The two rear digits of the reference symbols in FIG. 3a, which correspond to the same rear reference symbols in FIG. 2a, describe the same components as in FIG. 2a.
  • the top view of the further front power transistor half cell 302 in FIG. 3a does not differ from the top view of the front power transistor half cell 202 in FIG. 2a.
  • FIG. 3b shows a sectional view along plane AA ' through the further front power transistor half-cell 302.
  • FIG. 3b does not differ from FIG. 2b.
  • FIG. 3c shows a sectional view along the plane BB ‘through the further front power transistor half-cell 202.
  • FIG. 3c does not differ from FIG. 2c.
  • Figure 3d shows a rear view of the further front
  • the current spreading layer 306 has a rectangular shape. This places the current spreading layer 306 below the trench 304 expanded uniformly or uniformly. This leads to an improved current conduction below the trench 304 along the second direction 307 and the third direction 321.
  • FIG. 4a shows a plan view of a further front power transistor cell 402.
  • the two rear positions of the reference symbols in FIG. 4a which correspond to the same rear reference symbols in FIG. 2a, describe the same components as in FIG. 2a.
  • the difference from FIG. 2a is that FIG. 4a additionally has body contact regions 413 which contact the body regions 410.
  • the body contact regions 413 are arranged below the source regions 409.
  • the body contact regions 413 are electrically connected to the field shield contact regions 411.
  • the body contact regions 413 lead to the
  • FIG. 4b shows a sectional view along plane AA ' through the further front power transistor half-cell 402.
  • FIG. 4b does not differ from FIG. 2b.
  • FIG. 4c shows a sectional view along the plane BB ‘through the further front power transistor half-cell 402.
  • the two rear positions of the reference symbols in FIG. 4c which correspond to the same rear reference symbols in FIG. 2c, describe the same components as in FIG. 2c.
  • the difference to Figure 2c is that Figure 4c is also
  • the body contact regions 413 are flat.
  • FIG. 4d shows a rear view of the further front power transistor half-cell 402.
  • the two rear positions of the reference symbols in FIG. 4d which denote the The same rear reference numerals correspond to FIG. 2d, describe the same components as in FIG. 2d.
  • Figure 4d shows the
  • FIG. 5a shows a top view of a further front power transistor cell 502.
  • the difference to Figure 4a is that the current spreading layer 506 from the front of the
  • the layer arrangement 501 extends deeper into the layer arrangement 501 than the current spreading layer 406 in FIG. 4a.
  • the trench bottom 504 and the field shielding regions 508 lie completely within the current spreading layer 506 and are at a distance from the drift layer 517. This counteracts the JFET effect between adjacent field shielding regions 508 along the third direction 521, so that a smaller one
  • Semiconductor substrate 515 be rounded.
  • FIG. 5b shows a sectional view along plane AA ' through the further front power transistor half-cell 502.
  • the two rear positions of the reference symbols in FIG. 5b which correspond to the same rear reference symbols in FIG. 4b, describe the same components as in FIG. 4b.
  • FIG. 5b differs from FIG. 4b in that the current spreading layer 506, starting from the front side of the layer arrangement 501, extends deeper than the current spreading layer 406 of FIG. 4b.
  • FIG. 5c shows a sectional view along the plane BB 'through the further front power transistor half cell 502.
  • the two rear positions of the reference symbols in FIG. 5c which correspond to the same rear reference symbols in FIG. 4c, describe the same components as in FIG. 4c.
  • FIG. 5c differs from FIG. 4c in that the current spreading layer 506, starting from the front side of the layer arrangement 501, extends deeper than the current spreading layer 406 in FIG. 4c.
  • FIG. 5d shows the rear view of the further front power transistor half cell 502.
  • the two rear positions of the reference symbols in FIG. 5d which correspond to the same rear reference symbols in FIG. 4d, describe the same components as in FIG. 4d. Starting from the front side of the layer arrangement, the current spreading layer 506 extends deeper into the
  • FIG. 6a shows a plan view of a further front power transistor cell 602.
  • the two rear positions of the reference symbols in FIG. 6a which correspond to the same rear reference symbols in FIG. 5a, describe the same components as in FIG. 5a.
  • the difference from FIG. 5a is that a width of the source regions 609, the body regions 610 and the field shielding contact regions 611 over the width of the
  • Power transistor cell 600 varies.
  • the extension of the field shielding contact areas 611 along the second direction 607 is not constant over the width of the power transistor cell 600, but rather at a maximum in the central area between the trenches, ie. H. when, for example, two power transistor cells are butted together along the third direction 621.
  • the expansion of the source regions 609 behaves in the opposite manner. The expansion is minimal in the region between the central trenches and maximally along the side wall of the trench 604. This means that the boundary between
  • the transistor cell runs in the shape of a triangle, the base side or wider side of the triangle adjoining the side wall of the trench 604.
  • Figure 6b shows a sectional view along the plane AA ' through the further front power transistor half-cell 602.
  • FIG. 6c shows a sectional view along the plane BB ‘through the further front power transistor half-cell 602.
  • the two rear positions of the reference symbols in FIG. 6c which correspond to the same rear reference symbols in FIG. 5c, describe the same components as in FIG. 5c.
  • FIG. 6c differs from FIG. 5c in that the source regions 609, the body regions 610 and the field shielding regions 611 do not have a constant width along the width of the power transistor cell 600.
  • FIG. 6d shows the rear view of the further front power transistor half cell 602.
  • the two rear positions of the reference symbols in FIG. 6d which correspond to the same rear reference symbols in FIG. 5d, describe the same components as in FIG. 5d.
  • the width of the source regions 609, the body regions 610 and the field shielding regions 611 varies along the width of the power transistor cell.
  • FIG. 7 a shows a plan view of two power transistor cells 700 which are arranged along the second direction 707.
  • Body areas 710 and the field shielding contact areas 711 are designed to be rectangular. That means the width of the source regions 709, the width of the body regions 710 and the width of the
  • Field shield contact areas 711 are across the width of the
  • Power transistor cell 700 the same.
  • the source regions 709, the body regions 710 and the field shielding contact regions 711 each extend from the side surface of the trench to the power transistor cell edge.
  • FIG. 7b shows a plan view of a further power transistor cell 700.
  • Field shielding contact areas 711 have a different width along the third direction 721.
  • a power transistor comprises a plurality of power transistor cells 700.
  • the power transistor cells 700 are along the second direction 707 and the third direction 721 joined together. Preferably be doing this
  • Power transistor cells of the same construction joined together. However, different power transistor cells can also be joined together.
  • Power transistor cells the power transistor cells are arranged in a nested manner, so that a field shielding contact area is present in one strip and none or only part of the area in the adjacent strip
  • FIGS. 8a, 8b and 8c show three hexagonal and FIGS. 9a, 9b and 9c three square cell arrangements in a schematic plan view.
  • the source regions 809 and 909 and the field shielding contact regions 811 and 911 as well as the gate oxides 819 and 919 can be seen.
  • the source metallization is not shown.
  • the field shielding areas 808 and 908 within the layer arrangement are shown as regions surrounded by dashed lines.
  • the dual p-channel component constructed for this purpose is also intended to be described by this application. In this case, all n-doping must be exchanged for p-doping and the signs of the voltages reversed.
  • Source potential is used as a reference potential for the following explanations.
  • Gate metallization has a positive gate potential and the second
  • Metal area, d. H. the drain connection has a small positive drain potential of a few volts. If the gate potential is below the threshold voltage Vth, then only a small current flows from the drain connection to the source connection.
  • the power transistor cell or the component with one or a plurality of power transistor cells is thus able to carry a high current density.
  • the gate voltage has a lower value than that
  • the drain voltage has a positive voltage value. As the drain voltage increases, the space charge zones of the reverse voltage absorbing pn junctions expand between the p-doped ones
  • the shielding effect of the field shielding contact areas is more effective and the forward resistance is higher. If the ratio goes to zero, it is
  • a ratio of approximately 0.5 is therefore preferred.
  • the field shielding areas and the field shielding contact areas function in the
  • Gate voltage has a value smaller than the threshold voltage and the drain voltage has a negative voltage.
  • a compromise between low forward resistance and electrical connection of the field shielding areas can be made via the ratio of the extent of the field shielding contact areas along the second direction to the extent of the power transistor cell in the second direction. If the value of the ratio approaches the value 1, it is
  • the power transistors can be in inverters for industrial drives, inverters for regenerative energy generation such as wind turbines, automotive inverters for electric vehicles and hybrid vehicles, train drives or

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EP20727950.6A 2019-05-31 2020-05-18 Leistungstransistorzelle und leistungstransistor Withdrawn EP3977519A1 (de)

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DE102019208010 2019-05-31
DE102019210681.1A DE102019210681A1 (de) 2019-05-31 2019-07-19 Leistungstransistorzelle und Leistungstransistor
PCT/EP2020/063821 WO2020239501A1 (de) 2019-05-31 2020-05-18 Leistungstransistorzelle und leistungstransistor

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EP (1) EP3977519A1 (ja)
JP (1) JP7291807B2 (ja)
KR (1) KR20220016134A (ja)
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DE (1) DE102019210681A1 (ja)
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JP3158973B2 (ja) * 1995-07-20 2001-04-23 富士電機株式会社 炭化けい素縦型fet
JP2007005657A (ja) * 2005-06-24 2007-01-11 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2008177335A (ja) 2007-01-18 2008-07-31 Fuji Electric Device Technology Co Ltd 炭化珪素絶縁ゲート型半導体装置。
JP2012069797A (ja) * 2010-09-24 2012-04-05 Toyota Motor Corp 絶縁ゲート型トランジスタ
US9306061B2 (en) 2013-03-13 2016-04-05 Cree, Inc. Field effect transistor devices with protective regions
US20180366569A1 (en) * 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
JP6880669B2 (ja) * 2016-11-16 2021-06-02 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
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CN114175266A (zh) 2022-03-11
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TW202114214A (zh) 2021-04-01
DE102019210681A1 (de) 2020-12-03

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