EP3721314A1 - Techniques de référence et de compensation de tension à compensation de courbure analogique de second ordre à coefficient de température programmable pour circuits de référence de tension - Google Patents

Techniques de référence et de compensation de tension à compensation de courbure analogique de second ordre à coefficient de température programmable pour circuits de référence de tension

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Publication number
EP3721314A1
EP3721314A1 EP18829584.4A EP18829584A EP3721314A1 EP 3721314 A1 EP3721314 A1 EP 3721314A1 EP 18829584 A EP18829584 A EP 18829584A EP 3721314 A1 EP3721314 A1 EP 3721314A1
Authority
EP
European Patent Office
Prior art keywords
current
coupled
voltage
fet
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18829584.4A
Other languages
German (de)
English (en)
Other versions
EP3721314B1 (fr
Inventor
Umanath R. KAMATH
John K. Jennings
Edward Cullen
Ionut C. CICAL
Darragh WALSH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/832,515 external-priority patent/US10290330B1/en
Priority claimed from US15/848,357 external-priority patent/US10120399B1/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of EP3721314A1 publication Critical patent/EP3721314A1/fr
Application granted granted Critical
Publication of EP3721314B1 publication Critical patent/EP3721314B1/fr
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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • Examples of the present disclosure generally relate to electronic circuits and, in particular, to a programmable temperature coefficient analog second- order curvature compensated voltage reference and to trim techniques for voltage reference circuits.
  • ICs such as System-on-Chip (SoC) ICs.
  • Voltage references are required for various purposes, such as for analog-to-digitai converters (ADCs), power management, and the like. Generation of a voltage that is dependent on temperature is also useful in some applications, such as to compensate for temperature effects on circuits.
  • ADC analog-to-digitai converter
  • circuits for generating voltage references typically use bipolar junction transistors (BJTs).
  • BJTs are parasitic devices in the complementary metal oxide semiconductor (CMOS) process used to fabricate ICs BJT performance degrades as the CMOS technology scales, which is driven by digital logic.
  • CMOS complementary metal oxide semiconductor
  • a voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
  • a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate
  • an integrated circuit includes: one or more circuits; and a voltage reference circuit that supplies at least one voltage to the one or more circuits.
  • the voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
  • a reference circuit comprising
  • a method of generating a voltage reference includes: generating a proportional-to-temperature current and corresponding first control voltage in a first circuit of a reference circuit; generating a complementary-to- temperature current and corresponding second control voltage in a second circuit of the reference circuit; generating a sum current of the proportional-to- temperature current and the complementary-to-temperature current in a first current source in response to the first and second control voltages; generating a zero temperature coefficient (Tempco) voltage from the sum current in a first load circuit coupled to the first current source; generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in a second current source in response to the first and second control voltages; and generating a negative Tempco voltage from the sum current and the complementary-to-temperature current in a second load circuit coupled to the second current source.
  • Tempco zero temperature coefficient
  • a method of trimming a voltage reference in an integrated circuit includes: at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage; measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values; at a second temperature, sequencing through a second plurality of trim codes for the reference circuit; measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values; and selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.
  • an apparatus for trimming a voltage reference in an integrated circuit includes: a memory; and a processor configured to execute code stored in the memory to: at a first temperature, sequence through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a
  • Fig. 1 is a block diagram depicting an integrated circuit (IC) according to an example.
  • Fig. 2 is a block diagram depicting a voltage reference circuit according to an example.
  • Fig. 3 is a schematic diagram depicting a reference circuit according to an example.
  • Fig. 4 is a schematic diagram depicting a resistor ladder according to example.
  • Fig. 5A is a schematic diagram depicting a zero temperature coefficient (Tempco) circuit according to an example.
  • Fig. 5B is a schematic diagram depicting a curvature correction circuit according to an example.
  • Fig. 5C is a schematic diagram depicting another portion of the zero Tempco circuit of Fig. 5A according to an example.
  • Fig. 6 is a graph illustrating the dependence of reference voltage on temperature.
  • Fig. 7 is a schematic diagram depicting a negative Tempco circuit according to an example.
  • Fig. 8 is a schematic diagram depicting a positive Tempco circuit according to an example.
  • Fig. 9 is a flow diagram depicting a method of generating a voltage reference according to an example.
  • Fig. 10 is a block diagram depicting a test system according to an example.
  • Fig. 1 1 is a flow diagram depicting a method of setting trim codes in a voltage reference circuit according to an example.
  • Fig. 12A is a graph 800 depicting flat trim codes versus output voltage at different temperatures according to an example.
  • Fig. 12B is a graph 801 depicting ref trim codes versus output voltage at a particular temperature according to an example.
  • Fig. 13 is a flow diagram depicting a method of setting trim codes in a voltage reference circuit according to another example.
  • Fig. 14A is a graph depicting measurements of a reference trim code at two different temperatures according to an example.
  • Fig. 14B is a graph depicting a lookup of the flat trim code according to an example.
  • Fig. 15 is a block diagram depicting a programmable IC in which the voltage reference circuit described herein can be used according to an example.
  • Fig. 16 illustrates a field programmable gate array (FPGA) implementation of the programmable IC of Fig. 15.
  • FPGA field programmable gate array
  • Fig. 1 is a block diagram depicting an integrated circuit (IC) 100 according to an example.
  • the IC 100 includes a voltage reference circuit 200, a control circuit 1 14, and circuits 102.
  • the voltage reference circuit 200 is coupled between a supply node 1 10, which supplies a voltage Vcc, and a ground node 1 12, which supplies a ground voltage (e.g., 0 volts).
  • the voltage Vcc may be provided by a voltage supply (not shown) either within the IC 100 or external to the IC 100.
  • the voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 104, each of which supplies a zero temperature coefficient (Tempco) voltage.
  • Tempco zero temperature coefficient
  • the voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 106, each of which supplies a negative Tempco voltage.
  • the voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 108, each of which supplies a positive Tempco voltage.
  • the voltage reference circuit 200 generates zero Tempco voltage(s), negative Tempco voltage(s), and positive Tempco voltage(s).
  • the control circuit 1 14 supplies control signals to the voltage reference circuit 200 for trimming voltages and/or currents as described in detail below.
  • Fig. 2 is a block diagram depicting the voltage reference circuit 200 according to an example.
  • the voltage reference circuit 200 includes a reference circuit 202, a zero Tempco circuit 204, a negative Tempco circuit 206, and a positive Tempco circuit 208.
  • a node 210 couples one output of the reference circuit 202 to each of the Tempco circuits 204...208.
  • a node 212 couples another output of the reference circuit 202 to each of the Tempco circuits 204...208.
  • the nodes 210 and 212 supply control voltages to the Tempco circuits 204...208.
  • the reference circuit 202 generates a proportional-to- temperature current (referred to as Iptat) and a complementary-to-temperature current (referred to as lctat), as described further below.
  • the control voltages on the nodes 210 and 212 control current sources in the Tempco circuits 204...208 to mirror the currents Iptat and lctat, respectively.
  • the negative Tempco circuit 206 converts the current Iztat into one or more negative Tempco voltages at the nodes 106.
  • the positive Tempco circuit 208 converts the current Iztat into one or more positive Tempco voltages at the nodes 108.
  • Fig. 3 is a schematic diagram depicting the reference circuit 202 according to an example.
  • the reference circuit 202 includes p-channel field effect transistors (FETs) 302, 304, and 306, such as p-type metal oxide semiconductor FETs (MOSFETs).
  • FETs field effect transistors
  • MOSFETs metal oxide semiconductor FETs
  • a p-channel FET is a FET that uses holes as the majority carrier to carry its channel current.
  • the reference circuit 202 further includes an operational amplifier 308, an operational amplifier 316, a multiplexer 320, a resistor 310, a resistor ladder 318, a bipolar junction transistor (BJT) 312, and a BJT 314.
  • the BJTs 312 and 314 are PNP transistors.
  • a source of the FET 302 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 302 is coupled to a node 324.
  • a gate of the FET 302 is coupled to the node 210 that supplies a control voltage Vp.
  • a source of the FET 304 is coupled to the node 1 10.
  • a drain of the FET 304 is coupled to a node 326.
  • a gate of the FET 304 is coupled to the node 210.
  • a source of the FET 306 is coupled to the node 1 10.
  • a gate of the FET 306 is coupled to the node 212 that supplies a control voltage Vc.
  • a drain of the FET 306 is coupled to a node 330.
  • the resistor ladder 318 having a total resistance R2, is coupled between the node 330 and the ground node 1 12.
  • Fig. 4 is a schematic diagram depicting a resistor ladder 400 according to example.
  • the resistor ladder 400 can be used as the resistor ladder 318 or any other resistor ladder described herein.
  • the resistor ladder 400 includes a resistor string 408, e.g., resistors 408 I ...408 K , where K is an integer greater than one.
  • the resistors 408 I ...408 K are coupled in series between a node 410 and a node 412.
  • the resistor ladder 400 further includes a multiplexer 402. Inputs of the multiplexer 402 are respectively coupled to a plurality of taps, e.g., taps
  • Each tap 404i ...404 is coupled to a respective node of the resistor string 408, where the resistor string 408 includes one or more resistors between each pair of nodes.
  • the multiplexer 402 includes a control input 414 for receiving a signal Ctrl that selects one of the taps 404.
  • the signal Ctrl is a digital signal having ceiling[log2(J)] bits.
  • the multiplexer 402 includes an output coupled to a node 406.
  • the resistor ladder 400 provides an effective resistance R between the node 406 and the node 412 (shown in phantom for purposes of illustration), which depends on the code value of the Ctrl signal.
  • a node 328 is coupled to a selected tap of the resistor ladder 318 based on the value of a Flat Trim code. This effectively splits the resistor ladder 318 into a resistance 3181 between the node 330 and the node 328, and a resistance 3182 between the node 328 and the ground node 1 12.
  • the resistance 3181 has a value R2’, and the resistance 3182 has a value R2”.
  • An inverting input of the operational amplifier 308 is coupled to the node 324.
  • a non-inverting input of the operational amplifier 308 is coupled to the node 326.
  • An output of the operational amplifier 308 is coupled to the node 210.
  • An inverting input of the operational amplifier 316 is coupled to the node 324.
  • a non-inverting input of the operational amplifier 316 is coupled to a node 328.
  • An output of the operational amplifier 316 is coupled to the node 212.
  • the resistor 310 having a resistance R1 , is coupled between the node 326 and an emitter of the BJT 314.
  • Each of a base and a collector of the BJT 314 is coupled to the ground node 1 12.
  • the BJT 314 is a diode-connected BJT having an anode coupled to the resistor 310 and a cathode coupled to the ground node 1 12.
  • An emitter of the BJT 312 is coupled to the node 324.
  • Each of a base and a collector of the BJT 312 is coupled to the ground node 1 12.
  • the BJT 312 is a diode-connected BJT having an anode coupled to the node 324 and a cathode coupled to the ground node 1 12.
  • the BJT 314 has N times the emitter area as the BJT 312, where N is an integer greater than one.
  • the operational amplifier 308 is self-biasing and sets the control voltage V P to turn on the FETs 302 and 304.
  • the operational amplifier 308 applies negative feedback so that the voltage at the node 324 equals the voltage at the node 326.
  • the voltage at the node 324 is a voltage VEBI , which is the voltage between the emitter and base of the BJT 312.
  • the voltage VEBI is complementary to temperature (i.e., has a negative Tempco).
  • the voltage at the emitter of the BJT 314 is V EB 2, which is the voltage between the emitter and base of the BJT 314.
  • the voltage V EB 2 is complementary to temperature.
  • the ideality factor n is assumed to be one and is omitted from subsequent expressions.
  • the thermal voltage V T KT/q, where T is the temperature in Kelvin, K is the Boltzmann constant, and q is the electron charge in coulombs.
  • AV BE is proportional to temperature (i.e., has a positive Tempco).
  • the current Iptat can be
  • Iptat AV BE /R1 , which is also proportional to temperature.
  • V P at the node 210 controls current sources in the Tempco circuits to mirror the current Iptat.
  • the operational amplifier 316 applies negative feedback through adjustment of the control voltage Vc to equalize the voltage at node 328 and the voltage at node 324 (e.g., V EBI ).
  • V EBI the voltage at node 330 into the resistor ladder 3128
  • lctat V EBI /R2
  • V EBI complementary to temperature
  • lctat also complementary to temperature.
  • the voltage Vc at the node 212 controls current sources in the Tempco circuits to mirror the current lctat.
  • the current lctat can be trimmed by varying the Flat Trim code. The flat trim balances the
  • Fig. 5A is a schematic diagram depicting the zero Tempco circuit 204 according to an example.
  • the zero Tempco circuit 204 includes p-channel FETs 502, 504, 506, and 508 (e.g., p-type MOSFETs).
  • the zero Tempco circuit 204 further includes a curvature correction circuit 510, a resistor ladder 512, and a resistor ladder 554.
  • a source of the FET 502 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 502 is coupled to a node 530.
  • a gate of the FET 502 is coupled to the node 212 that supplies the control voltage Vc.
  • a source of the FET 504 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 504 is coupled to a node 530.
  • a gate of the FET 504 is coupled to the node 210 that supplies the control voltage Vp.
  • a source of the FET 506 is coupled to the node 1 10.
  • a drain of the FET 506 is coupled to a node 532.
  • a gate of the FET 506 is coupled to the node 212 that supplies the control voltage Vc.
  • a source of the FET 508 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 508 is coupled to the node 532.
  • a gate of the FET 508 is coupled to the node 210 that supplies the control voltage Vp.
  • the FETs 502 and 504 form a current source 514i that mirrors lctat and Iptat.
  • the FETs 506 and 508 form a current source 514 2 that mirrors lctat and Iptat.
  • the resistor ladder 512 having a resistance RLOADI , is coupled between the node 530 and the ground node 1 12.
  • a node 556 is coupled to a selected tap of the resistor ladder 512 based on the value of the Ref1 Trim code. Selection of the tap results in a resistance 512i coupled between the node 530 an the node 556, and a resistance 512 2 coupled between the node 556 and the ground node 1 12.
  • the resistance 512i has a value RLOADI’, and the resistance 512 2 has a value RLOADI”.
  • the curvature correction circuit 510 is coupled to the node 556 to supply a current lcor, as described further below.
  • the resistor ladder 554 having a resistance RLOAD2, is coupled between the node 532 and the ground node 1 12.
  • a node 558 is coupled to a selected tap of the resistor ladder 554 based on the value of the Ref2 Trim code. Selection of the tap results in a resistance 554i coupled between the node 532 and the node 558, and a resistance 554 2 coupled between the node 558 and the ground node 1 12.
  • the resistance 554i has a value RLOAD2’, and the resistance 554 2 has a value RLOAD2”.
  • control voltage Vc controls the FETs 502 and 506 to supply the current lctat.
  • the control voltage VP controls the FETs 504 and 508 to supply the current Iptat.
  • the currents lctat and Iptat feed the node 530.
  • the control circuit 1 14 sets the Ref1 Trim to control values of RLOADI ⁇ and RLOADI”.
  • the curvature correction circuit 510 supplies a current lcor to the resistor ladder 512 such that, in steady state condition, the sum of the currents Iztat and lcor conducts through the resistance RLOADI”.
  • the node 556 supplies a voltage that is proportional to Iztat+lcor, which is referred to as V refi .
  • the voltage V refi has a zero Tempco.
  • the currents lctat and Iptat feed the node 532.
  • the control circuit 1 14 controls sets Ref2 Trim to control values for RLOAD2’ and RLOAD2”.
  • the node 558 supplies a voltage, V rei 2, which is proportional to Iztat.
  • the voltage V ref 2 has a zero Tempco.
  • the voltage output by the LPF 538 is proportional to Iztat.
  • the operational amplifier 540, the resistor 544, the resistor 546, and the resistor 552 are configured as a non-inverting amplifier that applies a configured amount of gain to the voltage output by the LPF 538.
  • the gain is determined by the resistance values of the resistors 544, 546, and 552.
  • the node 542 supplies a zero Tempco voltage V ref 2.
  • the resistors 544, 548, and 552 form a voltage divider that supplies a fraction of V ref 2 at the node 550 (e.g., half of the voltage to generate V ref2 /2).
  • the Ref1 Trim and Ref2 Trim codes set a direct current (DC) level of the corresponding pre-gain voltages at the nodes 556 and 558, respectively.
  • Gain circuits can be used to amplifier or attenuate the pre-gain voltages.
  • Voltage dividers can then provide one or more fractions of the post-gain reference voltage.
  • the zero Tempco circuit 204 includes two current sources 514 for mirroring lctat and Iptat to generate three zero Tempco voltages.
  • the zero Tempco circuit 204 can include less or more than two current sources 514 for generating any number of zero Tempco voltages.
  • one or both of the gain circuits 516 can be omitted.
  • another current source 514 can feed another resistor ladder that supplies a pre- gain output voltage.
  • Fig. 5B is a schematic diagram depicting the curvature correction circuit 510 according to an example.
  • the curvature correction circuit 510 includes p- channel FETs 564, 566, and 568 (e.g., p-type MOSFETs).
  • the curvature correction circuit 510 further includes PNP BJTs 570 and 572, as well as a trans- conductance circuit 578.
  • Sources of the FETs 564, 566, and 568 are coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 564 is coupled to the node 574, and a gate of the FET 564 is coupled to the node 212 that supplies the control voltage Vc.
  • Drains of the FETs 566 and 568 are coupled to the node 5576.
  • a gate of the FET 566 is coupled to the node 212 that supplies the control voltage Vc.
  • a gate of the FET 568 is coupled to the node 210 that supplies the control voltage Vp.
  • the width of the FETs 566 and 568 are half that of the FET 564.
  • the FET 564 supplies a mirror of the current lctat
  • the FET 566 supplies a mirror of the current lctat/2
  • the FET 568 supplies a mirror of the current lptat/2.
  • An emitter of the BJT 570 is coupled to the node 574 to provide the voltage V EB 3.
  • An emitter of the BJT 572 is coupled to the node 576 to provide the voltage VEB 4 .
  • Bases and collectors of the BJTs 570 and 572 are coupled to the ground node 1 12.
  • the BJTs 570 and 572 are diode-connected BJTs coupled between the node 574 and the ground node 1 12, and between the node 576 and the ground node 1 12, respectively.
  • the BJT 572 has N’ times the emitter area as the BJT 570, where N’ is an integer greater than one.
  • Inputs of the trans-conductance circuit 578 are coupled to the nodes 574 and 576.
  • An output of the trans-conductance circuit 578 is coupled to the node 556 and supplies the current lcor.
  • Fig. 6 is a graph 600 illustrating the dependence of V refi on temperature.
  • the graph 600 includes an axis 602 representing temperature, and an axis 606 representing the voltage V re n in volts.
  • V refi has a convex bow with respect to temperature. That is, V refi increases with increasing temperature until reaching a maximum value and then decreases with further increases in temperature.
  • the curvature correction circuit 510 applies second- order correction to Iztat to mitigate the temperature dependence of V refi due to first-order error in lctat.
  • the 6 includes an axis 604 representing AV BE 2 in volts. As shown by a curve 608, the voltage AV BE 2 has a concave bow with respect to temperature. That is, AV BE 2 decreases with increasing temperature until reaching a minimum value and then increases with further increases in temperature.
  • the trans-conductance circuit 578 converts the differential voltage AV BE 2 into the current lcor, which has the same concave curvature over temperature.
  • the trans-conductance circuit 578 injects the current lcor into the node 556. As temperature varies, the current lctat + lcor is substantially constant due to the second-order curvature correction.
  • Fig. 5C is a schematic diagram depicting another portion 204A of the zero Tempco circuit 204 according to an example.
  • the portion 204A of the zero Tempco circuit 204 includes p-channel FETs 580 and 582, as well as a resistor ladder 586.
  • a source of the FET 580 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 580 is coupled to a node 584.
  • a gate of the FET 580 is coupled to the node 212 that supplies the control voltage Vc.
  • a source of the FET 582 is coupled to the node 1 10 that supplies Vcc.
  • a drain of the FET 582 is coupled to the node 584.
  • a gate of the FET 582 is coupled to the node 210 that supplies the control voltage Vp.
  • the FETs 580 and 582 form a current source 514 3 that mirrors lctat and Iptat.
  • the resistor ladder 586 having a resistance RLOAD3, is coupled between the node 584 and the ground node 1 12.
  • a node 588 is coupled to a selected tap of the resistor ladder 586 based on the value of the Ref3 Trim code. Selection of the tap results in a resistance 586i coupled between the node 584 and the node 588, and a resistance 586 2 coupled between the node 588 and the ground node 1 12.
  • the resistance 586i has a value RLOAD3’, and the resistance 586 2 has a value RLOAD3”.
  • the node 588 supplies a voltage Vref3 that is a pre-gain zero Tempco voltage.
  • Fig. 7 is a schematic diagram depicting the negative Tempco circuit 206 according to an example.
  • the negative Tempco circuit 206 includes six p- channel FETs 702...712 and resistor ladders 718, 720, 728, and 730. Sources of the FETs 702...712 are coupled to the node 1 10 that supplies Vcc. Drains of the FETs 702 and 704 are coupled to a node 714. A drain of the FET 706 is coupled to a node 724. Drains of the FETs 708 and 710 are coupled to a node 716. A drain of the FET 712 is coupled to a node 736.
  • Gates of the FETs 702 and 708 are coupled to the node 210 that supplies the control voltage Vp. Gates of the FETs 704, 706, 710, and 712 are coupled to the node 212 that supplies the control voltage Vc.
  • the FETs 702, 704, and 706 form a first current source 715i, and the FETs 708, 710, and 712 form a second current source 715 2 .
  • the resistor ladder 718 having a resistance R3, is coupled between the node 714 and a node 726.
  • the resistor ladder 720 having a resistance R4, is coupled between the node 726 and the ground node 1 12.
  • the resistor ladders 718 and 720 are coupled in series between the node 714 and the ground node 1 12.
  • a selected tap of the resistor ladder 718, as determined by the code Neg1 Trim generated by the control circuit 1 14, is coupled to a node 722.
  • the resistor ladder 718 is effectively split between a resistance 718 1 and a resistance 718 2 , where the resistance 718 1 has a value R3’ and the resistance 718 2 has a value R3”.
  • a selected tap of the resistor ladder 720 is coupled to the node 724.
  • the resistor ladder 720 is effectively split between a resistance 720i and a resistance 720 2 , where the resistance 720i has a value R4’ and the resistance 720 2 has a value R4”.
  • the resistor ladder 728 having a resistance R5
  • the resistor ladder 730 having a resistance R6, is coupled between the node 734 and the ground node 1 12.
  • the resistor ladders 728 and 730 are coupled in series between the node 716 and the ground node 1 12.
  • a selected tap of the resistor ladder 728, as determined by the code Neg2 Trim generated by the control circuit 1 14, is coupled to a node 732.
  • the resistor ladder 728 is effectively split between a resistance 728i and a resistance 728 2 , where the resistance 728i has a value R5’ and the resistance 728 2 has a value R5”.
  • a selected tap of the resistor ladder 730 is coupled to the node 736.
  • the resistor ladder 730 is effectively split between a resistance 730i and a resistance 730 2 , where the resistance 730i has a value R6’ and the resistance 730 2 has a value R6”.
  • the FETs 702 and 704 supply a current Iztat (i.e., Ictat+lptat) through the series combination of the resistor ladder 718 and the resistor ladder 720.
  • the FET 706 supplies a mirror of lctat through the resistance 720 2 .
  • the voltage V negi has a zero Temoco component lztat * (R3+R4) and a negative Tempco component I ctat * R4”.
  • the voltage V negi has a negative Tempco.
  • the control circuit 1 14 sets the code Neg1 Slope Trim to control the slope of the negative Tempco for the voltage V negi .
  • the control circuit 1 14 sets the code Neg1 Trim to control the DC level of the voltage V negi given the code used for Neg1 Slope Trim.
  • the FETs 708 and 710 supply a current Iztat (i.e. , lctat+lptat) through the series combination of the resistor ladder 728 and the resistor ladder 730.
  • the FET 712 supplies a mirror of lctat through the resistance 730 2 .
  • the voltage V neg 2 has a zero Temoco component lztat * (R5+R6) and a negative Tempco component lctat * R6”.
  • the voltage V neg 2 has a negative Tempco.
  • the control circuit 1 14 sets the code Neg2 Slope Trim to control the slope of the negative Tempco for the voltage V neg 2.
  • the control circuit 1 14 sets the code Neg2 Trim to control the DC level of the voltage V neg 2 given the code used for Neg2 Slope Trim.
  • the voltage V neg 2 is set independent of the voltage V negi .
  • the negative Tempco circuit 206 can include any number of current sources 715, each coupled to a pair of resistor ladders as shown in Fig. 7. In this manner, the negative Tempco circuit can supply any number of
  • gain circuits are omitted from Fig. 7, in some examples, one or both of the pre-gain voltage outputs can be coupled to a gain circuit, similar to the configuration shown in Fig. 5A.
  • Fig. 8 is a schematic diagram depicting the positive Tempco circuit 208 according to an example.
  • the positive Tempco circuit 208 includes p-channel FETs 802 and 804, a resistor ladder 824, switches 808 and 810, and digital-to- analog (DAC) current sources 816 and 820.
  • Sources of the FETs 802 and 804 are coupled to the node 1 10 that supplies the voltage Vcc.
  • Drains of the FET s 802 and 804 are coupled to a node 806.
  • a gate of the FET 802 is coupled to the node 212 that supplies the control voltage Vc.
  • a gate of the FET 804 is coupled to the node 210 that supplies the control voltage Vp.
  • the resistor ladder 824 having a resistance R7, is coupled between the node 806 and the ground node 1 12.
  • the resistor ladder 824 is effectively split into a resistance 824i and a resistance 824 2 , having values R7’ and R7”, respectively.
  • the resistance 824i is coupled between the node 806 and the node 826.
  • the resistance 824 2 is coupled between the node 826 and the ground node 1 12.
  • the node 826 supplies a voltage VBLK.
  • One terminal of the switch 808 is coupled to the node 210 that supplies the control voltage Vp. Another terminal of the switch 808 is coupled to a node 812. A reference voltage input of the current DAC 816 is coupled to the node 812. The current DAC 816 includes a digital control input coupled to a bus 818 that supplies a digital signal Blk_p. A current output of the current DAC 816 is coupled to the node 806. A supply voltage input of the current DAC 816 is coupled to the node 1 10 that supplies the voltage Vcc.
  • One terminal of the switch 810 is coupled to the node 212 that supplies the control voltage Vc. Another terminal of the switch 810 is coupled to a node 814.
  • a reference voltage input of the current DAC 820 is coupled to the node 814.
  • the current DAC 820 includes a digital control input coupled to a bus 822 that supplies a digital signal Blk_c.
  • a current output of the current DAC 820 is coupled to the ground node 1 12.
  • a supply voltage input of the current DAC 820 is coupled to the node 806.
  • the voltage VBLK lztat * R7” + ldac * R7”.
  • the current Idac which flows into the node 806, depends on the state of the switches 808 and 810. If both switches 808 and 810 are open, the current Idac is zero. If the switch 808 is closed and the switch 810 is open, the current DAC 816 receives the voltage V P .
  • the current DAC 816 provides a ratio of the current Iptat based on the code supplied by the digital signal Blk_p.
  • the current DAC 816 outputs a current ldac_p.
  • the current Idac equals the current ldac_p supplied by the current DAC 816.
  • the voltage VBLK includes a zero Tempco component lztat * R7” and a positive Tempco component ldac_p * R7”.
  • the current DAC 820 receives the voltage Vc.
  • the current DAC 820 sinks a ratio of the current lctat based on the code supplied by the digital signal Blk_C.
  • the current DAC 820 sinks a current ldac_c.
  • the current Idac equals the -ldac_c supplied by the current DAC 820.
  • the voltage V BLK includes a zero Tempco component lztat * R7” and a positive Tempco component -ldac_c * R7”.
  • the current Idac ldac_p - ldac_c.
  • the voltage V BLK includes a zero Tempco component lztat * R7” and a positive Tempco component (ldac_p-ldac_c) * R7”.
  • control circuit 1 14 generates control signals Blk Ptat and Blk Ctat to open and close the switches 808 and 810 in an alternating sequence.
  • the control circuit 1 14 controls the magnitude of the oscillation using the digital signals Blk_p and Blk_c.
  • the control circuit 1 14 controls the DC level of the voltage V BLK using the Blk T rim code. While a single current source 815 and load (resistor ladder 824 and current DACs 816, 820) are shown, it is to be understood that the positive Tempco circuit 208 can include more than one current source 815 and associated load to generate more than one positive Tempco voltage.
  • the pre-gain voltage V BLK can be coupled to a gain circuit to provide a positive Tempco voltage with gain.
  • Fig. 9 is a flow diagram depicting a method 900 of generating a voltage reference according to an example.
  • the method 900 begins at block 902, where the reference circuit 202 generates Iptat and the control voltage Vp.
  • the reference circuit 202 generates lctat and the control voltage Vc.
  • one or more current sources generate a sum current of Iptat and lctat in response to the control voltages Vp and Vc.
  • the zero Tempco circuit 204 generates a zero Tempco voltage from the sum current.
  • the negative Tempco circuit 206 generates a negative Tempco voltage from the sum current.
  • the positive Tempco circuit 208 generates a positive Tempco voltage from the sum current.
  • Fig. 10 is a block diagram depicting a test system 1000 according to an example.
  • the test system 1000 includes automatic test equipment (ATE) 1002 and a wafer 1004 having a plurality of ICs 1 100.
  • the ATE 1002 includes a central processing unit (CPU) 1008, a memory 1012, input/output (IO) circuits 1010, and support circuits 1006.
  • the CPU 1008 can be any type of general- purpose processor, such as an x86-based processor, ARM®-based processor, or the like.
  • the CPU 1008 can include one or more cores and associated circuitry (e.g., cache memories, memory management units (MMUs), interrupt controllers, etc.).
  • MMUs memory management units
  • the CPU 1008 is configured to execute program code that perform one or more operations described herein and which can be stored in the memory 1012.
  • the support circuits 1006 include various devices that cooperate with the CPU 608.
  • the support circuits 1006 can include a chipset (e.g., a north bridge, south bridge, platform host controller, etc.), voltage regulators, firmware (e.g., a BIOS), and the like.
  • the CPU 1008 can be a System-in-Package (SiP), System-on-Chip (SoC), or the like, which absorbs all or a substantial portion of the functionality of the chipset (e.g., north bridge, south bridge, etc.).
  • the IO circuits 1010 include various circuits configured for communication with the ICs 1 100.
  • the memory 1012 is a device allowing information, such as executable instructions and data, to be stored and retrieved.
  • the memory 1012 can include, for example, one or more random access memory (RAM) modules, such as double-data rate (DDR) dynamic RAM (DRAM).
  • RAM random access memory
  • DDR double-data rate dynamic RAM
  • the ATE 1002 can include various other devices, including local storage devices (e.g., one or more hard disks, flash memory modules, solid state disks, and optical disks) and/or a storage interface that enables the test system 1000 to communicate with one or more network data storage systems.
  • Fig. 1 1 is a flow diagram depicting a method 1 100 of setting trim codes in a voltage reference circuit according to an example.
  • the method 1 100 can be performed by the ATE 1002 for setting the Flat Trim in the reference circuit 202, and the Ref_x Trim (e.g., Ref1 Trim, Ref2 Trim, etc.) in the circuit 500A, for each IC 100 on the wafer 604.
  • the Ref_x Trim e.g., Ref1 Trim, Ref2 Trim, etc.
  • the method 1 100 begins at step 1 102, where the wafer 1004 is disposed in a 0 degree Celsius (0C) environment and the ATE 1002 sequences through trim codes for the Flat T rim and measures Vrefl .
  • the ATE 1002 obtains a plurality of Vrefl values for a corresponding plurality of trim codes of the Flat Trim.
  • the ATE 1002 fits the Vrefl values obtained at step 1 102 to a polynomial curve having one or more coefficients (e.g., three coefficients).
  • the ATE 1002 stores the values of the coefficients in the IC 100 (e.g., in the control circuit 1 14 using, for example, an electronic fuse (e-fuse) or the like type memory element).
  • FIG. 12A is a graph 1200 depicting flat trim codes versus output voltage at different temperatures according to an example.
  • the horizontal axis represents flat trim code and the vertical axis represents output voltage.
  • the wafer 1004 is disposed in a 100 degree Celsius (100C) environment and the ATE 1002 sequences through trim codes for the Flat T rim and measures Vrefl .
  • the ATE 1002 obtains a plurality of Vrefl values for a corresponding plurality of trim codes of the Flat Trim.
  • the ATE 1002 fits the Vrefl values obtained at step 1 106 to a polynomial curve having the same order as that used in step 1 104.
  • a curve 1204 represents the polynomial curve determined at step 1 108.
  • the ATE 1002 determines an intersection between the Vrefl curve at 0C and the Vrefl curve at 100C.
  • the ATE 1002 can generate the Vrefl curve at 0C by obtaining the coefficients stored by the control circuit 1 14 in the IC 100.
  • the ATE 1002 generates the Vrefl curve at 100C in step 1 108.
  • the ATE 1002 determines a trim setting for the Flat Trim corresponding to the intersection between the Vrefl curve at 0C and the Vrefl curve at 100C. As shown in the graph 1200, the intersection of the curve 1202 and 1204 results in the determined flat trim code value.
  • T T2
  • the horizontal axis represents ref trim code and the vertical axis represents output voltage.
  • a curve 1206 represents ref trim code versus output voltage and an output voltage of 1 V results in the determined ref trim code value.
  • Fig. 13 is a flow diagram depicting a method 1300 of setting trim codes in a voltage reference circuit according to an example.
  • the method 1300 can be performed by the ATE 1002 for setting the Flat Trim in the reference circuit 202, and the Ref_x Trim (e.g., Ref1 Trim, Ref2 Trim, etc.) in the circuit 500A, for each IC 100 on the wafer 1004.
  • the Ref_x Trim e.g., Ref1 Trim, Ref2 Trim, etc.
  • the method 1300 begins at step 902, where the ATE 1002 selects an approximate trim code for the Flat Trim.
  • the approximate trim code for the Flat Trim can be set based on simulations of the voltage reference circuit.
  • the wafer 1004 is disposed in a 0C environment and the ATE 1002 selects a trim code for the Ref1 Trim that sets Vrefl to a desired value (e.g., 1 V).
  • the ATE 1002 can adjust the Refl Trim and measure Vrefl until Vrefl obtains the desired value.
  • the ATE 1002 stores the selected trim code for Ref1 Trim in the IC 100 (e.g., in the control circuit 1 14 using, for example, an electronic fuse (e-fuse) or the like type memory element).
  • the wafer 1004 is disposed in a 100C environment and the ATE 1002 selects a trim code for the Ref1 Trim that sets Vrefl to the desired value (e.g., 1 V).
  • the ATE 1002 determines the slope of the Ref1 Trim code over temperature. For example, the ATE 1002 can compute the difference between the Ref1 Trim code values at 0C and at 100C.
  • Fig. 14A is a graph 1400 depicting measurements of the Ref1 Trim Code at two different temperatures according to an example. In the graph 1400, the horizontal axis represents temperature and the vertical axis represents Ref1 Trim Code value. At temperature T 1 , codel is obtained. At temperature T2, code2 is obtained.
  • the ATE 1002 determines the slope of curve 1002 at step 1310.
  • the ATE 1002 obtains a trim code value for the Flat Trim from a lookup table based on the Ref1 Trim code slope determined at step 1310.
  • the lookup table can include a plurality of trim code values for the Flat T rim for a corresponding plurality of Ref1 Trim code slope values.
  • Fig. 14B is a graph 1001 depicting a lookup of the flat trim code given a slope of Ref1 Trim according to an example.
  • the horizontal axis represents flat trim code and the vertical axis represents the slope of the curve 1402 shown in Fig. 10A.
  • the temperature coefficient determined in step 1310 from the curve 1402 is corrected by changing the flat trim code setting based on a curve 1404.
  • Fig. 15 is a block diagram depicting a programmable IC 1 according to an example in which the voltage reference circuit 200 described herein can be used.
  • the programmable IC 1 includes programmable logic 3, configuration logic 25, and configuration memory 26.
  • the programmable IC 1 can be coupled to external circuits, such as nonvolatile memory 27, DRAM 28, and other circuits 29.
  • the programmable logic 3 includes logic cells 30, support circuits 31 , and programmable interconnect 32.
  • the logic cells 30 include circuits that can be configured to implement general logic functions of a plurality of inputs.
  • the support circuits 31 include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like.
  • the logic cells and the support circuits 31 can be interconnected using the programmable interconnect
  • the programmable IC 1 includes a processing system 2.
  • the processing system 2 can include microprocessor(s), memory, support circuits, IO circuits, and the like.
  • Fig. 16 illustrates a field programmable gate array (FPGA) implementation of the programmable IC 1 that includes a large number of different
  • programmable tiles including transceivers 37, configurable logic blocks (“CLBs”)
  • the FPGA can also include PCIe interfaces 40, analog-to-digital converters (ADC) 38, and the like.
  • each programmable tile can include at least one programmable interconnect element (“I NT”) 43 having connections to input and output terminals 48 of a programmable logic element within the same tile, as shown by examples included at the top of Fig. 1 1.
  • Each programmable interconnect element 43 can also include connections to interconnect segments 49 of adjacent programmable interconnect element(s) in the same tile or other tile(s).
  • Each programmable interconnect element 43 can also include
  • the general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments 50) and switch blocks (not shown) for connecting interconnect segments.
  • the interconnect segments of the general routing resources e.g., interconnect segments 50
  • the programmable interconnect elements 43 taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.
  • a CLB 33 can include a configurable logic element (“CLE”) 44 that can be programmed to implement user logic plus a single programmable interconnect element (“I NT”) 43.
  • a BRAM 34 can include a BRAM logic element (“BRL”) 45 in addition to one or more programmable interconnect elements.
  • BRAM logic element BRAM logic element
  • the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used.
  • a DSP tile 35 can include a DSP logic element (“DSPL”) 46 in addition to an appropriate number of programmable interconnect elements.
  • DSPL DSP logic element
  • An IOB 36 can include, for example, two instances of an input/output logic element (“IOL”) 47 in addition to one instance of the programmable interconnect element 43.
  • IOL input/output logic element
  • the actual I/O pads connected, for example, to the I/O logic element 47 typically are not confined to the area of the input/output logic element 47.
  • a horizontal area near the center of the die (shown in Fig. 16) is used for configuration, clock, and other control logic.
  • Vertical columns 51 extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.
  • Some FPGAs utilizing the architecture illustrated in Fig. 1 1 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA.
  • the additional logic blocks can be programmable blocks and/or dedicated logic.
  • Fig. 16 is intended to illustrate only an exemplary FPGA architecture.
  • the numbers of logic blocks in a row the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the
  • interconnect/logic implementations included at the top of Fig. 1 1 are purely exemplary.
  • more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.
  • a voltage reference circuit may be provided.
  • Such a voltage reference circuit my include: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a
  • a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
  • Some such voltage reference circuit may further include: a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the complementary-to- temperature current in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to- temperature current.
  • the third current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage.
  • FET field effect transistor
  • the third load circuit may include: a first current digital-to-analog converter (DAC), switchably coupled to receive the first control voltage, and configured to supply a first positive temperature coefficient (Tempco) current; a second current DAC, switchably coupled to receive the second control voltage, and configured to supply a second positive Tempco current; and a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage.
  • DAC current digital-to-analog converter
  • the first current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage
  • the first load circuit may include a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.
  • Some such voltage reference circuit may include: a curvature
  • the curvature compensation circuit configured to inject a correction current into the resistor ladder to combine with the sum current
  • the curvature compensation circuit comprising: a third FET and a fourth FET having a second common source and a second common drain, a gate of the third FET coupled to receive the first control voltage and a gate of the third FET coupled to receive the second control voltage; a fifth FET having a gate coupled to receive the second control voltage; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the fifth FET and the ground node; a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node; and a trans-conductance circuit configured to convert a voltage between the drain of the fifth FET and the second common drain to the correction current.
  • BJT bipolar junction transistor
  • the second current source may include: a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and a third FET having a gate coupled to the second control voltage; and wherein the second load circuit may include: a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.
  • FET field effect transistor
  • the reference circuit may include: a first field effect transistor (FET) and a second FET having a first common source and a first common gate; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node; a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node; a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate; a third FET having a source coupled to the common source; a resistor ladder coupled between a drain of the third FET and the ground node; and a second operational amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.
  • FET field effect transistor
  • BJT bipolar
  • an integrated circuit may be provided.
  • Such an integrated circuit may include: one or more circuits; and a voltage reference circuit that supplies at least one voltage to the one or more circuits, the voltage reference circuit comprising: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a
  • a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.
  • the voltage reference circuit further include: a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to-temperature current.
  • the third current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage.
  • FET field effect transistor
  • the third load circuit may include: a first current digital-to-analog converter (DAC), switchably coupled to receive the first control voltage, and configured to supply a first positive temperature coefficient (Tempco) current; a second current DAC, switchably coupled to receive the second control voltage, and configured to supply a second positive Tempco current; and a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage.
  • DAC current digital-to-analog converter
  • the first current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage
  • the first load circuit may include a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.
  • Some such integrated circuit may further include: a curvature compensation circuit configured to inject a correction current into the resistor ladder to combine with the sum current, the curvature compensation circuit comprising: a third FET and a fourth FET having a second common source and a second common drain, a gate of the third FET coupled to receive the first control voltage and a gate of the third FET coupled to receive the second control voltage; a fifth FET having a gate coupled to receive the second control voltage; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the fifth FET and the ground node; a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node; and a trans- conductance circuit configured to convert a voltage between the drain of the fifth FET and the second common drain to the correction current.
  • a curvature compensation circuit configured to inject a correction current into the resistor ladder to combine with the sum current
  • the curvature compensation circuit comprising: a third FET and
  • the second current source may include: a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and a third FET having a gate coupled to the second control voltage; and wherein the second load circuit may include: a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.
  • FET field effect transistor
  • the reference circuit may include: a first field effect transistor (FET) and a second FET having a first common source and a first common gate; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node; a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node; a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate; a third FET having a source coupled to the common source; a resistor ladder coupled between a drain of the third FET and the ground node; and a second operational amplifier having an inverting input coupled to the drain of the first FET, a non- inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.
  • FET field effect transistor
  • BJT bipolar
  • a method of generating a voltage reference may include: generating a proportional-to-temperature current and corresponding first control voltage in a first circuit of a reference circuit; generating a complementary-to-temperature current and corresponding second control voltage in a second circuit of the reference circuit; generating a sum current of the proportional-to-temperature current and the complementary- to-temperature current in a first current source in response to the first and second control voltages; generating a zero temperature coefficient (Tempco) voltage from the sum current in a first load circuit coupled to the first current source; generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in a second current source in response to the first and second control voltages; and generating a negative Tempco voltage from the sum current and the complementary-to-temperature current in a second load circuit coupled to the second current source.
  • Tempco zero temperature coefficient
  • Some such method may further include: generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in a third current source response to the first and second control voltages; and generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to- temperature current in a third load circuit coupled to the third current source.
  • the step of generating the positive Tempco voltage may include: supplying a first positive Tempco current from a first current digital-to- analog converter (DAC) switchably coupled to receive the first control voltage; supplying a second positive Tempco current from a second current DAC switchably coupled to receive the second control voltage; and
  • DAC digital-to- analog converter
  • Some such method may further include: injecting a correction current into the first load circuit to combine with the sum current.
  • a method of trimming a voltage reference in an integrated circuit may be provided. Such a method may include: at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to- temperature current and a corresponding first control voltage, and a
  • Some such method may further include: fitting the first voltage output values to a polynomial; and storing one or more first coefficients of the polynomial in the IC.
  • Some such method may further include: fitting the second voltage output values to the polynomial to generate one or more second coefficients; and determining an intersection between a first curve generated using the one or more first coefficients and a second curve generated using the one or more second coefficients.
  • the step of selecting the trim code may include determining the trim code from the intersection between the first curve and the second curve.
  • Some such method may further include: adjusting trim of a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage.
  • Tempco temperature coefficient
  • the reference circuit may include: a first field effect transistor (FET) and a second FET having a first common source and a first common gate; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node; a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node; a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate; a third FET having a source coupled to the common source; a resistor ladder coupled between a drain of the third FET and the ground node; and a second operational amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.
  • FET field effect transistor
  • BJT bipolar
  • the voltage reference may include: a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to- temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to- temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to- temperature current.
  • the first current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage
  • the first load circuit may include a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.
  • the second current source may include: a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and a third FET having a gate coupled to the second control voltage; and wherein the second load circuit may include: a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.
  • FET field effect transistor
  • the voltage reference may include: a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the complementary-to- temperature current in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to- temperature current.
  • an apparatus for trimming a voltage reference in an integrated circuit may include: a memory; and a processor configured to execute code stored in the memory to: at a first temperature, sequence through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to- temperature current and a corresponding first control voltage, and a
  • the processor is further configured to execute the code to: fit the first voltage output values to a polynomial; and store one or more first coefficients of the polynomial in the IC.
  • the processor is further configured to execute the code to: fit the second voltage output values to the polynomial to generate one or more second coefficients; and determine an intersection between a first curve generated using the one or more first coefficients and a second curve generated using the one or more second coefficients.
  • the processor selects the trim code by determining the trim code from the intersection between the first curve and the second curve.
  • the processor is further configured to execute the code to: adjust trim of a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage.
  • Tempco temperature coefficient
  • the reference circuit may include: a first field effect transistor (FET) and a second FET having a first common source and a first common gate; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node; a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node; a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate; a third FET having a source coupled to the common source; a resistor ladder coupled between a drain of the third FET and the ground node; and a second operational amplifier having an inverting input coupled to the drain of the first FET, a non- inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.
  • FET field effect transistor
  • BJT bipolar
  • the voltage reference may include: a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to- temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to- temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to- temperature current.
  • the first current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage
  • the first load circuit may include a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.
  • the second current source may include: a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and a third FET having a gate coupled to the second control voltage; and wherein the second load circuit may include: a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.
  • the voltage reference may include: a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the
  • the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to-temperature current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

L'invention concerne un circuit de référence de tension donné à titre d'exemple, comprenant : un circuit de référence (202) comprenant un premier circuit (308) conçu pour générer un courant proportionnel à la température et une première tension de commande correspondante et un second circuit (316) conçu pour générer un courant complémentaire à la température et une seconde tension de commande correspondante; une première source de courant (514i) couplée à un premier circuit de charge (512), la première source de courant générant un courant de somme du courant proportionnel à la température et du courant complémentaire à la température en réponse aux première et seconde tensions de commande, le premier circuit de charge générant une tension à coefficient de température (Tempco) nul à partir du courant de somme; et une seconde source de courant (715i) couplée à un second circuit de charge (718, 720), la seconde source de courant générant le courant de somme du courant proportionnel à la température et du courant complémentaire à la température en réponse aux première et seconde tensions de commande, le second circuit de charge générant une tension à Tempco négatif à partir du courant de somme et du courant complémentaire à la température.
EP18829584.4A 2017-12-05 2018-12-04 Techniques de référence et de compensation de tension à compensation de courbure analogique de second ordre à coefficient de température programmable pour circuits de référence de tension Active EP3721314B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/832,515 US10290330B1 (en) 2017-12-05 2017-12-05 Programmable temperature coefficient analog second-order curvature compensated voltage reference
US15/848,357 US10120399B1 (en) 2017-12-20 2017-12-20 Trim techniques for voltage reference circuits
PCT/US2018/063911 WO2019113111A1 (fr) 2017-12-05 2018-12-04 Techniques de référence et de compensation de tension à compensation de courbure analogique de second ordre à coefficient de température programmable pour circuits de référence de tension

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EP3721314A1 true EP3721314A1 (fr) 2020-10-14
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CN114115423B (zh) * 2021-12-17 2022-12-20 贵州振华风光半导体股份有限公司 一种带数字控制的带隙基准电流源电路
CN115793769B (zh) * 2023-01-29 2023-06-02 江苏润石科技有限公司 带隙基准滑动温度补偿电路及方法

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JPH0618012B2 (ja) * 1983-01-25 1994-03-09 セイコーエプソン株式会社 定電圧回路
JP3586073B2 (ja) * 1997-07-29 2004-11-10 株式会社東芝 基準電圧発生回路
US6265857B1 (en) * 1998-12-22 2001-07-24 International Business Machines Corporation Constant current source circuit with variable temperature compensation
JP4380343B2 (ja) 2004-01-30 2009-12-09 ソニー株式会社 バンドギャップレファレンス回路及び同回路を有する半導体装置
US7127368B2 (en) * 2004-11-19 2006-10-24 Stmicroelectronics Asia Pacific Pte. Ltd. On-chip temperature sensor for low voltage operation
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JP2007065831A (ja) * 2005-08-30 2007-03-15 Sanyo Electric Co Ltd 定電流回路
CN100593768C (zh) * 2007-12-05 2010-03-10 西安标新电子科技有限责任公司 一种输出可调正、负或零温度系数电流、电压基准的电路
US8106707B2 (en) * 2009-05-29 2012-01-31 Broadcom Corporation Curvature compensated bandgap voltage reference
TWI399631B (zh) * 2010-01-12 2013-06-21 Richtek Technology Corp 可快速啟動的低電壓能隙參考電壓產生器
JP5554134B2 (ja) * 2010-04-27 2014-07-23 ローム株式会社 電流生成回路およびそれを用いた基準電圧回路
CN102880220B (zh) * 2011-07-12 2016-01-06 联咏科技股份有限公司 温度系数电流触发产生器及温度系数电流触发产生模块
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KR20200096586A (ko) 2020-08-12
CN111448531A (zh) 2020-07-24
KR102600881B1 (ko) 2023-11-09
CN111448531B (zh) 2022-09-09
JP2021506006A (ja) 2021-02-18
JP7281464B2 (ja) 2023-05-25
WO2019113111A1 (fr) 2019-06-13

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