EP3506341A1 - Übertragungsverfahren einer nutzschicht auf ein trägersubstrat - Google Patents
Übertragungsverfahren einer nutzschicht auf ein trägersubstrat Download PDFInfo
- Publication number
- EP3506341A1 EP3506341A1 EP18213125.0A EP18213125A EP3506341A1 EP 3506341 A1 EP3506341 A1 EP 3506341A1 EP 18213125 A EP18213125 A EP 18213125A EP 3506341 A1 EP3506341 A1 EP 3506341A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- donor substrate
- zone
- substrate
- cavity
- useful layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 200
- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000003313 weakening effect Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 230000000737 periodic effect Effects 0.000 claims description 8
- -1 silicon ions Chemical class 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910013641 LiNbO 3 Inorganic materials 0.000 claims description 3
- 239000007790 solid phase Substances 0.000 claims description 3
- 230000005484 gravity Effects 0.000 claims 1
- 241000894007 species Species 0.000 description 22
- 241001644893 Entandrophragma utile Species 0.000 description 13
- 230000001681 protective effect Effects 0.000 description 9
- 230000005587 bubbling Effects 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- 230000005764 inhibitory process Effects 0.000 description 7
- 238000004070 electrodeposition Methods 0.000 description 6
- 239000012071 phase Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 238000001953 recrystallisation Methods 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910003327 LiNbO3 Inorganic materials 0.000 description 2
- 229910012463 LiTaO3 Inorganic materials 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- FHHJDRFHHWUPDG-UHFFFAOYSA-N peroxysulfuric acid Chemical compound OOS(O)(=O)=O FHHJDRFHHWUPDG-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/005—Bulk micromachining
- B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0116—Thermal treatment for structural rearrangement of substrate atoms, e.g. for making buried cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/85—Piezoelectric or electrostrictive active materials
- H10N30/853—Ceramic compositions
- H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
Definitions
- the invention relates to the technical field of transfer of a useful layer, belonging to a donor substrate, on a support substrate.
- the donor substrate and / or the support substrate is provided with at least one surface cavity.
- the invention finds particular application in the manufacture of a membrane on the cavity, used for mechanical microsystems (MEMS), for example in a pressure sensor, a resonator, a microphone or a biochemical sensor.
- MEMS mechanical microsystems
- the transferred useful layer can also be used as a protective cover, for example for a component, or as a hermetic encapsulation means.
- Such a method of the state of the art makes it possible to obtain a satisfactory control of the thickness of the transferred useful layer as well as a good uniformity of the thickness on the support substrate.
- a method of the state of the art is not entirely satisfactory insofar as D1 teaches that the thickness of the useful layer, denoted t, defines a theoretical maximum width of the cavity, denoted W lim , which is proportional to t 2 .
- W lim a theoretical maximum width of the cavity
- a width of the cavity greater than W lim will lead to a failure of the useful layer transferred to the support substrate, which is related to the bubbling formation (" blistering "in English) of the species implanted in the cavity.
- the skilled person seeks, for a fixed thickness of the useful layer, to push the limits of the maximum width of the cavity beyond which there is a failure of the useful layer transferred to the support substrate.
- such a method according to the invention makes it possible, by virtue of the presence of such an amorphous zone, to push back the limits of the maximum width of the cavity beyond which a failure of the useful layer transferred onto the substrate is observed. support.
- such an amorphous zone makes it possible to locally inhibit the bubbling of the implanted species, caused by the gas resulting from the recombination of said species.
- this inhibition of the bubbling of the implanted species makes it possible to transfer a thin useful layer, without fearing its mechanical failure, even his break. Inhibition of the bubbling of implanted species is increased when the amorphous zone is completely opposite the cavity at the end of step b).
- such an amorphous zone has a lower Young's modulus than a monocrystalline structure (for example of the order of 20% lower for amorphous silicon compared with monocrystalline silicon), which makes it possible to reduce the risks. propagation of a crack during step c).
- the fact that the amorphous zone extends parallel to the weakening zone allows a fracture of the donor substrate during step c) which operates parallel to the cavity.
- the method according to the invention may comprise one or more of the following characteristics.
- the cavity is formed at the first surface of the support substrate; and the bonding of step b) takes place between the first surface of the donor substrate and the first surface of the support substrate.
- the support substrate comprises pillars, extending to the first surface of the support substrate, and partially delimiting the cavity; and the bonding of step b) takes place between the first surface of the donor substrate and the pillars of the support substrate.
- the donor substrate provided during step a) comprises pillars, extending to the first surface of the donor substrate, and partially delimiting the cavity; and the bonding of step b) takes place between the pillars of the donor substrate and the first surface of the support substrate.
- the support substrate comprises pillars, extending to the first surface of the support substrate, and partially delimiting a first cavity;
- the donor substrate provided in step a) comprises pillars, extending to the first surface of the donor substrate, and partially delimiting a second cavity; and the bonding of step b) takes place between the pillars of the donor substrate and the pillars of the support substrate so as to join the first and second cavities and form the cavity.
- the method comprises a step d) of recrystallizing the amorphous zone, step d) being carried out after step c); step d) being preferably performed by solid phase epitaxial resumption.
- the amorphous zone is recrystallized during step d) in order to reconstruct the crystalline structure of the useful layer, and this from the crystalline material surrounding the amorphous zone.
- Step d) is essential when it is desired to form an electronic device from the useful layer.
- step a 1 ) consists in implanting ionized species into the donor substrate, through the first surface of the donor substrate, said ionized species preferably comprising at least one of the species selected from H + , He + , B + .
- step a 2 consists in implanting species into the useful layer, through the first surface of the donor substrate, said species being preferably silicon ions or germanium ions.
- an advantage obtained is to easily obtain a "buried" amorphous zone, that is to say located at a distance from the first surface of the donor substrate, which is not possible with a deposition technique.
- step a 2 is performed so that the amorphous region extends away from the first surface of the donor substrate.
- an advantage provided by such a buried amorphous zone, closer to the weakening zone, is to improve the effectiveness of the inhibition of the bubbling of the implanted species, caused by the gas resulting from the recombination of said species.
- a buried amorphous zone makes it possible to improve the quality of the recrystallization during step d).
- another advantage provided by such a buried amorphous zone is that it can be suppressed simply by sacrificial oxidation or thinning.
- the useful layer of the donor substrate provided during step a) has a density density, denoted ⁇ 1 ; and step 2) is performed so that the amorphous region has a bulk density, denoted ⁇ 2, ⁇ 2 ⁇ ⁇ satisfying 1/10.
- an advantage provided is to improve the effectiveness of the inhibition of bubbling implanted species.
- the useful layer of the donor substrate provided in step a) has a thickness, denoted t, defining a theoretical maximum width of the cavity, denoted W lim , which is proportional to t 2 ; and step a 2 ) is performed so that the amorphous region forms a periodic grating with a pitch, denoted p, satisfying p ⁇ W lim , the periodic grating extending parallel to the first surface of the donor substrate.
- an advantage provided by such a periodic network is to be able to obtain excellent inhibition of the bubbling of the implanted species, and without having to have an amorphous zone extending completely opposite the cavity at the end of the step b) - involving an alignment that can be tricky to operate.
- step c) is performed by applying thermal annealing to the assembly obtained at the end of step b).
- the thermal annealing temperature is the plateau value of the heating temperature.
- semiconductor is meant that the material has an electrical conductivity at 300 K of between 10 8 S / cm and 10 3 S / cm.
- the cavity or cavities 200 are formed at the first surface 20 of the support substrate 2, preferably by photolithography and etching steps.
- the support substrate 2 comprises a second surface 21, opposite to the first surface 20.
- the first surface 20 of the support substrate 2 may be covered with an oxide layer.
- the oxide layer may be a thermal oxide.
- the first surface 20 of the support substrate 2 may be covered with a metal layer.
- the metal layer is made of a metallic material, preferably selected from Au, Cu, Ti, W.
- the first surface 30 of the donor substrate 3 is advantageously covered with an oxide layer in order to promote hydrophilic bonding during step b) .
- the first surface 30 of the donor substrate 3 is advantageously covered with a metal layer, preferably of the same metal, in order to promote thermocompression bonding during the treatment. step b).
- the donor substrate 3 has a monocrystalline structure.
- the parameters will be adapted according to the desired thickness for the useful layer 1.
- the donor substrate 3 is made of monocrystalline silicon
- an energy of 160 keV and a dose of 6 ⁇ 10 16 at.cm -2 lead to a thickness of 1.5 ⁇ m for the useful layer 1.
- the useful layer 1 of the donor substrate 3 provided during step a) has a density density, noted ⁇ 1 .
- Step a2) is advantageously performed so that the amorphous region 4 has a volumetric density, denoted ⁇ 2, ⁇ satisfying 2 ⁇ ⁇ 1/10.
- the useful layer 1 of the donor substrate 3 provided in step a) has a thickness, denoted t, defining a theoretical maximum width of the cavity, denoted W lim , which is proportional to t 2 , as described in D1.
- step a 2 ) is executed so that the amorphous zone 4 forms a periodic grating with a pitch, noted p, satisfying p ⁇ W lim , the periodic grating extending parallel to the first surface 30 of the donor substrate 3.
- W lim is of the order of 40 ⁇ m.
- step b) takes place between the first surface 30 of the donor substrate 3 and the first surface 20 of the support substrate 2.
- support substrate 2 is provided with a single cavity 200, step b) is performed so that the amorphous zone 4 is at least partially opposite the cavity 200.
- step b) is carried out so that the amorphous zone 4 is at least partially opposite each cavity 200.
- the side of the first surface 30 of the donor substrate 3 is defined by the orientation of the normal to the first surface 30 of the donor substrate 3.
- the side of the first surface 20 of the support substrate 2 is defined by the orienting the normal to the first surface 20 of the support substrate 2.
- the bonding performed during step b) is advantageously a bonding by direct adhesion between the first surface 30 of the donor substrate 3 and the first surface 20 of the support substrate 2.
- direct adhesion is meant a spontaneous bonding resulting from the contacting two surfaces, that is to say in the absence of an additional element such as glue, wax or solder.
- the adhesion comes mainly from the van der Waals forces resulting from the electronic interaction between atoms or molecules of two surfaces, hydrogen bonds due to surface preparations or covalent bonds established between two surfaces.
- molecular bonding or direct bonding Bonding by direct adhesion can not be likened to thermocompression bonding, eutectic bonding, or anodic bonding.
- the bonding performed during step b) may be a thermocompression bonding or eutectic bonding depending on the nature of the first surface 30 of the donor substrate 3 and the first surface 20 of the support substrate 2.
- Step b) is advantageously preceded by a preparation of the first surface 30 of the donor substrate 3 and a preparation of the first surface 20 of the support substrate 2.
- a preparation of the first surface 30 of the donor substrate 3 and a preparation of the first surface 20 of the support substrate 2 is advantageously preceded by a preparation of the first surface 30 of the donor substrate 3 and a preparation of the first surface 20 of the support substrate 2.
- direct bonding it is possible to chemically activate the first surfaces 20, 30, for example with the aid of a Caro acid (produced by a mixture of H 2 SO 4 and H 2 O 2 ), and then to clean the first surfaces 20, 30 by a standard RCA type process.
- CMP chemical mechanical polishing
- scrubber a cleaning brush
- Step b) is advantageously carried out in a controlled atmosphere medium.
- step b) can be performed under high vacuum such that a secondary vacuum of less than 10 -2 mbar.
- Step c) is illustrated in figure 1f .
- Step c) of splitting (" splitting " in English) is advantageously performed by applying thermal annealing to the assembly obtained at the end of step b).
- Thermal annealing is applied according to a thermal budget adapted to fracture the donor substrate 3 according to the zone of weakening ZS.
- the thermal annealing temperature is preferably between 350 ° C and 550 ° C.
- the duration of the thermal annealing is preferably between 5 minutes and 3 hours.
- Step c) is advantageously preceded by a step of applying thermal annealing to the assembly obtained during step b) according to a heat budget adapted to reinforce the bonding without initiating the fracture of the donor substrate 3 according to the zone ZS embrittlement.
- the method advantageously comprises a step d) of recrystallizing the amorphous zone 4, step d) being carried out after step c).
- Step d) is illustrated in figure 1g .
- Step d) is advantageously carried out by solid phase epitaxial resumption.
- an advantage provided is to be able to easily reconstruct a crystalline structure for the useful layer 1.
- Step d) is essential when it is desired to form an electronic device from the useful layer 1.
- the step a 2 ) is advantageously performed so that the amorphous zone 4 has a mass crystallinity of less than or equal to 20%, which improves the quality of the recrystallization.
- Step d) is performed by applying thermal annealing.
- the amorphous zone 4 is amorphous silicon, the recrystallization starts at 450 ° C.
- the method may also comprise dry or wet etching steps, as well as cleaning steps of the useful layer 1.
- step d) is optional.
- step a 2 can be performed so that the amorphous area 4 has a mass crystallinity of less than or equal to 80%.
- a polycrystalline structure of the amorphous zone 4 is perfectly suitable when an electronic device does not have to be formed from the useful layer 1.
- the pillars 6 are advantageously made of a metallic material, preferably copper.
- the pillars 6 are formed at the first surface 20 of the support substrate 2 by electrodeposition (ECD for " Electro-Chemical Deposition ").
- ECD Electro-Chemical Deposition
- the bonding performed during step b) is advantageously a thermocompression bonding.
- Such a useful layer 1 transferred locally forms a protective cover, preferably hermetic, on the support substrate 2, so as to form an encapsulation means.
- a transferred useful layer 1 forms a means of encapsulation that is more effective than an ad hoc layer deposited, pierced and then recapped.
- step d) is optional.
- step a 2 can be performed so that the amorphous zone 4 has a mass crystallinity of less than or equal to 80%.
- a polycrystalline structure of the amorphous zone 4 is perfectly suitable when an electronic device does not have to be formed from the useful layer 1.
- the pillars 6 'are advantageously made of a metallic material, preferably copper.
- ECD Electro-Chemical Deposition
- the bonding performed during step b) is advantageously a thermocompression bonding.
- Such a useful layer 1 transferred locally forms a protective cover, preferably hermetic, on the support substrate 2, so as to form an encapsulation means.
- a transferred useful layer 1 forms a means of encapsulation that is more effective than an ad hoc layer deposited, pierced and then recapped.
- step d) is optional.
- step a 2 can be performed so that the amorphous area 4 has a mass crystallinity of less than or equal to 80%.
- a polycrystalline structure the amorphous zone 4 is perfectly suitable when an electronic device does not have to be formed from the useful layer 1.
- the pillars 6 of the support substrate 2 and the pillars 6 'of the donor substrate 3 are advantageously made of a metallic material, preferably copper.
- the pillars 6 of the support substrate 2 and the pillars 6 'of the donor substrate 3 are respectively formed at the first surface 20 of the support substrate 2 and at the first surface 30 of the donor substrate 3 by electrodeposition (ECD for " ElectroChemical Deposition ").
- ECD ElectroChemical Deposition
- the bonding performed in step b) is advantageously thermocompression bonding.
- Such a useful layer 1 transferred locally forms a protective cover, preferably hermetic, on the support substrate 2, so as to form an encapsulation means.
- a transferred useful layer 1 forms a means of encapsulation that is more effective than an ad hoc layer deposited, pierced and then recapped.
- the invention is not limited to the exposed embodiments. Those skilled in the art are able to consider their technically operating combinations, and to substitute equivalents for them.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1763342A FR3076292B1 (fr) | 2017-12-28 | 2017-12-28 | Procede de transfert d'une couche utile sur un substrat support |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3506341A1 true EP3506341A1 (de) | 2019-07-03 |
EP3506341B1 EP3506341B1 (de) | 2020-07-29 |
Family
ID=62455579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP18213125.0A Active EP3506341B1 (de) | 2017-12-28 | 2018-12-17 | Übertragungsverfahren einer nutzschicht auf ein trägersubstrat |
Country Status (3)
Country | Link |
---|---|
US (1) | US11401162B2 (de) |
EP (1) | EP3506341B1 (de) |
FR (1) | FR3076292B1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3076292B1 (fr) * | 2017-12-28 | 2020-01-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile sur un substrat support |
FR3091032B1 (fr) * | 2018-12-20 | 2020-12-11 | Soitec Silicon On Insulator | Procédé de transfert d’une couche superficielle sur des cavités |
FR3091620B1 (fr) * | 2019-01-07 | 2021-01-29 | Commissariat Energie Atomique | Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture |
FR3108204B1 (fr) * | 2020-03-10 | 2023-10-27 | Commissariat Energie Atomique | Procédé de suspension d’une couche mince sur une cavité avec effet raidisseur obtenu par pressurisation de la cavité par des espèces implantées |
FR3108787B1 (fr) * | 2020-03-31 | 2022-04-01 | Commissariat Energie Atomique | Procédé basse température de transfert et de guérison d’une couche semi-conductrice |
CN112259675B (zh) * | 2020-10-19 | 2022-10-28 | 济南晶正电子科技有限公司 | 一种具有图案的薄膜键合体、制备方法及电子器件 |
US11955374B2 (en) * | 2021-08-29 | 2024-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming SOI substrate |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060118817A1 (en) * | 2002-12-19 | 2006-06-08 | Koninklijke Philips Electronics N.V. | Stress-free composite substrate and method of manufacturing such a composite substrate |
EP2224476A1 (de) * | 2009-02-27 | 2010-09-01 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Herstellungsverfahren eines Hybridsubstrats durch teilweise Rekristallisierung einer Mischschicht |
Family Cites Families (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4177084A (en) * | 1978-06-09 | 1979-12-04 | Hewlett-Packard Company | Method for producing a low defect layer of silicon-on-sapphire wafer |
US4509990A (en) * | 1982-11-15 | 1985-04-09 | Hughes Aircraft Company | Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates |
DE4439238A1 (de) * | 1994-11-03 | 1996-05-09 | Telefunken Microelectron | Kapazitiver Beschleunigungssensor |
US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US6451668B1 (en) * | 1998-12-15 | 2002-09-17 | Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of producing calibration structures in semiconductor substrates |
US6245618B1 (en) * | 1999-02-03 | 2001-06-12 | Advanced Micro Devices, Inc. | Mosfet with localized amorphous region with retrograde implantation |
US6806147B1 (en) * | 1999-11-22 | 2004-10-19 | Advanced Micro Devices, Inc. | Method and apparatus for suppressing the channeling effect in high energy deep well implantation |
US6459141B2 (en) * | 1999-11-22 | 2002-10-01 | Advanced Micro Devices, Inc. | Method and apparatus for suppressing the channeling effect in high energy deep well implantation |
US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
FR2810448B1 (fr) * | 2000-06-16 | 2003-09-19 | Soitec Silicon On Insulator | Procede de fabrication de substrats et substrats obtenus par ce procede |
FR2817974B1 (fr) * | 2000-12-12 | 2003-09-12 | Commissariat Energie Atomique | Micro-actionneur optique, composant optique utilisant le micro-actionneur, et procede de realisation d'un micro-actionneur optique |
EP1244142A1 (de) * | 2001-03-23 | 2002-09-25 | Universite Catholique De Louvain | Herstellungsverfahren für SOI-Halbleiterbauelemente |
US8415208B2 (en) * | 2001-07-16 | 2013-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and peeling off method and method of manufacturing semiconductor device |
FR2834123B1 (fr) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report |
US6958255B2 (en) * | 2002-08-08 | 2005-10-25 | The Board Of Trustees Of The Leland Stanford Junior University | Micromachined ultrasonic transducers and method of fabrication |
FR2850487B1 (fr) * | 2002-12-24 | 2005-12-09 | Commissariat Energie Atomique | Procede de realisation de substrats mixtes et structure ainsi obtenue |
US6902962B2 (en) * | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
FR2855908B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince |
WO2005031842A2 (en) * | 2003-09-26 | 2005-04-07 | Universite Catholique De Louvain | Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses |
US7247246B2 (en) * | 2003-10-20 | 2007-07-24 | Atmel Corporation | Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity |
US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
US7104129B2 (en) * | 2004-02-02 | 2006-09-12 | Invensense Inc. | Vertically integrated MEMS structure with electronics in a hermetically sealed cavity |
CN1922732B (zh) * | 2004-02-25 | 2010-06-09 | S.O.I.Tec绝缘体上硅技术公司 | 光电检测装置 |
DE602004010117D1 (de) * | 2004-09-16 | 2007-12-27 | St Microelectronics Srl | Verfahren zur Hestellung von zusammengestzten Halbleiterplättchen mittels Schichtübertragung |
WO2006037783A1 (fr) * | 2004-10-04 | 2006-04-13 | S.O.I.Tec Silicon On Insulator Technologies | Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline |
US7250353B2 (en) * | 2005-03-29 | 2007-07-31 | Invensense, Inc. | Method and system of releasing a MEMS structure |
US7318349B2 (en) * | 2005-06-04 | 2008-01-15 | Vladimir Vaganov | Three-axis integrated MEMS accelerometer |
US7880565B2 (en) * | 2005-08-03 | 2011-02-01 | Kolo Technologies, Inc. | Micro-electro-mechanical transducer having a surface plate |
DE102005054218B4 (de) * | 2005-11-14 | 2011-06-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterelements und Halbleiterelement |
FR2895391B1 (fr) * | 2005-12-27 | 2008-01-25 | Commissariat Energie Atomique | Procede d'elaboration de nanostructures ordonnees |
FR2897982B1 (fr) * | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat |
US7764003B2 (en) * | 2006-04-04 | 2010-07-27 | Kolo Technologies, Inc. | Signal control in micromachined ultrasonic transducer |
US7625776B2 (en) * | 2006-06-02 | 2009-12-01 | Micron Technology, Inc. | Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon |
US20080296708A1 (en) * | 2007-05-31 | 2008-12-04 | General Electric Company | Integrated sensor arrays and method for making and using such arrays |
JP2009016692A (ja) * | 2007-07-06 | 2009-01-22 | Toshiba Corp | 半導体記憶装置の製造方法と半導体記憶装置 |
FR2918792B1 (fr) * | 2007-07-10 | 2010-04-23 | Soitec Silicon On Insulator | Procede de traitement de defauts d'interface dans un substrat. |
FR2925888A1 (fr) * | 2007-12-27 | 2009-07-03 | Commissariat Energie Atomique | Dispositif a structure pre-liberee |
FR2938117B1 (fr) * | 2008-10-31 | 2011-04-15 | Commissariat Energie Atomique | Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree |
FR2941561B1 (fr) * | 2009-01-28 | 2011-05-13 | Commissariat Energie Atomique | Procede de fermeture de cavite pour au moins un dispositif microelectronique |
WO2011025939A1 (en) * | 2009-08-28 | 2011-03-03 | Analog Devices, Inc. | Dual single-crystal backplate microphone system and method of fabricating same |
US8563345B2 (en) * | 2009-10-02 | 2013-10-22 | National Semiconductor Corporated | Integration of structurally-stable isolated capacitive micromachined ultrasonic transducer (CMUT) array cells and array elements |
US9099526B2 (en) * | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
CN102822970B (zh) * | 2010-03-31 | 2015-06-17 | Soitec公司 | 键合半导体结构及其形成方法 |
US10497713B2 (en) * | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US8847337B2 (en) * | 2011-02-25 | 2014-09-30 | Evigia Systems, Inc. | Processes and mounting fixtures for fabricating electromechanical devices and devices formed therewith |
FR2973158B1 (fr) * | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences |
FI124354B (fi) * | 2011-04-04 | 2014-07-15 | Okmetic Oyj | Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille |
FR2983342B1 (fr) * | 2011-11-30 | 2016-05-20 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue |
FR2986106B1 (fr) * | 2012-01-20 | 2014-08-22 | Soitec Silicon On Insulator | Procede de fabrication de substrats semi-conducteur, et substrats semi-conducteur |
US20130278359A1 (en) * | 2012-04-19 | 2013-10-24 | Qualcomm Mems Technologies, Inc. | Two- and three-substrate level processes for producing evanescent mode electromagnetic wave cavity resonators |
US8884725B2 (en) * | 2012-04-19 | 2014-11-11 | Qualcomm Mems Technologies, Inc. | In-plane resonator structures for evanescent-mode electromagnetic-wave cavity resonators |
JP2013229356A (ja) * | 2012-04-24 | 2013-11-07 | Mitsubishi Electric Corp | Soiウェハおよびその製造方法、並びにmemsデバイス |
US8735199B2 (en) * | 2012-08-22 | 2014-05-27 | Honeywell International Inc. | Methods for fabricating MEMS structures by etching sacrificial features embedded in glass |
US9499392B2 (en) * | 2013-02-05 | 2016-11-22 | Butterfly Network, Inc. | CMOS ultrasonic transducers and related apparatus and methods |
EP2969914B1 (de) * | 2013-03-15 | 2020-01-01 | Butterfly Network Inc. | Ultraschallwandler mit komplementärem metalloxid-halbleiter (cmos) und verfahren zur herstellung davon |
US10446700B2 (en) * | 2013-05-22 | 2019-10-15 | W&Wsens Devices, Inc. | Microstructure enhanced absorption photosensitive devices |
FR3008543B1 (fr) * | 2013-07-15 | 2015-07-17 | Soitec Silicon On Insulator | Procede de localisation de dispositifs |
US9187316B2 (en) * | 2013-07-19 | 2015-11-17 | University Of Windsor | Ultrasonic sensor microarray and method of manufacturing same |
TWI682817B (zh) * | 2013-07-23 | 2020-01-21 | 美商蝴蝶網路公司 | 可互連的超音波換能器探頭以及相關的方法和設備 |
US9111996B2 (en) * | 2013-10-16 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor-on-insulator structure and method of fabricating the same |
WO2015191088A1 (en) * | 2014-06-13 | 2015-12-17 | Intel Corporation | High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer |
EP3158588A4 (de) * | 2014-06-23 | 2018-01-17 | Intel Corporation | Verfahren zur formung vertikaler transistorarchitekturen |
FR3023411B1 (fr) * | 2014-07-07 | 2017-12-22 | Commissariat Energie Atomique | Generation localisee de contrainte dans un substrat soi |
US9067779B1 (en) * | 2014-07-14 | 2015-06-30 | Butterfly Network, Inc. | Microfabricated ultrasonic transducers and related apparatus and methods |
US9165945B1 (en) * | 2014-09-18 | 2015-10-20 | Soitec | Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures |
US9394161B2 (en) * | 2014-11-14 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | MEMS and CMOS integration with low-temperature bonding |
US20160009544A1 (en) * | 2015-03-02 | 2016-01-14 | Butterfly Network, Inc. | Microfabricated ultrasonic transducers and related apparatus and methods |
FR3045934B1 (fr) * | 2015-12-22 | 2018-02-16 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d’un empilement de dispositifs electroniques |
US10629468B2 (en) * | 2016-02-11 | 2020-04-21 | Skyworks Solutions, Inc. | Device packaging using a recyclable carrier substrate |
FR3052765B1 (fr) * | 2016-06-17 | 2021-06-04 | Commissariat Energie Atomique | Dispositif microelectromecanique et/ou nanoelectromecanique a deplacement hors-plan comportant des moyens capacitifs a variation de surface |
US10991675B2 (en) * | 2016-10-10 | 2021-04-27 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10512936B2 (en) * | 2017-06-21 | 2019-12-24 | Butterfly Network, Inc. | Microfabricated ultrasonic transducer having individual cells with electrically isolated electrode sections |
FR3076292B1 (fr) * | 2017-12-28 | 2020-01-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile sur un substrat support |
US11121121B2 (en) * | 2018-09-04 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
-
2017
- 2017-12-28 FR FR1763342A patent/FR3076292B1/fr not_active Expired - Fee Related
-
2018
- 2018-12-17 EP EP18213125.0A patent/EP3506341B1/de active Active
- 2018-12-18 US US16/223,857 patent/US11401162B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060118817A1 (en) * | 2002-12-19 | 2006-06-08 | Koninklijke Philips Electronics N.V. | Stress-free composite substrate and method of manufacturing such a composite substrate |
EP2224476A1 (de) * | 2009-02-27 | 2010-09-01 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Herstellungsverfahren eines Hybridsubstrats durch teilweise Rekristallisierung einer Mischschicht |
Also Published As
Publication number | Publication date |
---|---|
FR3076292B1 (fr) | 2020-01-03 |
US20190202688A1 (en) | 2019-07-04 |
US11401162B2 (en) | 2022-08-02 |
EP3506341B1 (de) | 2020-07-29 |
FR3076292A1 (fr) | 2019-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP3506341B1 (de) | Übertragungsverfahren einer nutzschicht auf ein trägersubstrat | |
EP0851465B1 (de) | Verfahren zum Trennen von mindestens zwei Elementen einer Struktur, die durch Ionenimplantation verbunden sind | |
EP1155442B1 (de) | Verfahren zur herstellung einer mehrschichtigen struktur mit kontrollierten eigenspannungen | |
EP1114446B1 (de) | Herstellung einer dünnen membran | |
EP1923912B1 (de) | Verfahren zur Herstellung einer gemischten mikrotechnologischen Struktur | |
FR2797347A1 (fr) | Procede de transfert d'une couche mince comportant une etape de surfragililisation | |
EP1210730B1 (de) | Herstellung einer leitenden verbindung zwischen zwei halbleiterelementen | |
WO2007020351A1 (fr) | Procédé de report d'une couche mince sur un support | |
FR2952224A1 (fr) | Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante. | |
EP2965346A1 (de) | Verfahren zur herstellung einer leitfähigen direktmetallverbindung | |
EP1631982A1 (de) | Verfahren zur herstellung einer sehr dünnen schicht durch provozierte selbstragung | |
EP3900064B1 (de) | Verfahren zum übertragen einer oberflächenschicht auf hohlräume | |
EP4088309B1 (de) | Verfahren zum verbinden zweier halbleitersubstrate | |
EP4000090B1 (de) | Verfahren zum hydrophilen zusammenfügen von substraten | |
EP3817037A1 (de) | Verfahren zum transfer einer dünnschicht mithilfe eines präkeramischen geladenen polymers | |
EP3800658B1 (de) | Verfahren zur herstellung einer elektronischen vorrichtung | |
EP1861873A1 (de) | Verfahren zur herstellung einer heterostruktur mit mindestens einer dicken schicht aus halbleitermaterial | |
FR3063834A1 (fr) | Procede de fabrication d'un dispositif semi-conducteur tridimensionnel | |
FR3120737A1 (fr) | Procede de fabrication d’une structure semi-conductrice a base de carbure de silicium et structure composite intermediaire | |
EP4091197A1 (de) | Verfahren zur herstellung eines bildsensors | |
FR3108439A1 (fr) | Procede de fabrication d’une structure empilee | |
FR3120736A1 (fr) | Procede de fabrication d’une structure semi-conductrice a base de carbure de silicium et structure composite intermediaire | |
FR3076393A1 (fr) | Procede de transfert d'une couche utile | |
FR2822817A1 (fr) | Procede de fabrication d'une structure a membrane micro-usinee | |
FR3059149A1 (fr) | Procede de fabrication d'un film mince a base d'inp ou de gaas |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20181217 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20200310 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1296796 Country of ref document: AT Kind code of ref document: T Effective date: 20200815 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: FRENCH |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602018006473 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG4D |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20200729 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1296796 Country of ref document: AT Kind code of ref document: T Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20201029 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20201030 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20201029 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20201130 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20201129 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602018006473 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
26N | No opposition filed |
Effective date: 20210430 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20201231 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20201217 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20201217 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20200729 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20201231 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211231 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211231 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20231221 Year of fee payment: 6 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20231218 Year of fee payment: 6 Ref country code: DE Payment date: 20231219 Year of fee payment: 6 |