EP3384434B1 - Procédé pour incorporation circuit intégré flip chip - Google Patents

Procédé pour incorporation circuit intégré flip chip Download PDF

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Publication number
EP3384434B1
EP3384434B1 EP16809206.2A EP16809206A EP3384434B1 EP 3384434 B1 EP3384434 B1 EP 3384434B1 EP 16809206 A EP16809206 A EP 16809206A EP 3384434 B1 EP3384434 B1 EP 3384434B1
Authority
EP
European Patent Office
Prior art keywords
substrate
carrier core
contact pad
flip chip
flexible film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP16809206.2A
Other languages
German (de)
English (en)
Other versions
EP3384434A1 (fr
Inventor
Eng Seng NG
Sze Yong PANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NG, ENG SENG
SMARTFLEX TECHNOLOGY Pte Ltd
Original Assignee
Smartflex Technology Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Smartflex Technology Pte Ltd filed Critical Smartflex Technology Pte Ltd
Priority to PL16809206T priority Critical patent/PL3384434T3/pl
Priority to MA43370A priority patent/MA43370B1/fr
Publication of EP3384434A1 publication Critical patent/EP3384434A1/fr
Application granted granted Critical
Publication of EP3384434B1 publication Critical patent/EP3384434B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps

Definitions

  • the invention relates to manufacture of smart card devices with improved lifespan, reliability and aesthetics, and methods of manufacturing that reduce production steps and costs.
  • An integrated circuit (IC) module of smart-type, that can be either a secure microcontroller or equivalent intelligence with internal memory or a memory chip alone, is normally packaged or embedded in a carrier (e.g. card).
  • the resulting smart card device can be capable of connecting to a reader by direct physical contact, i.e. using contact-type interface defined by ISO (International Organization for Standardization) 7816, or by a remote contactless radio frequency interface, i.e. using contactless-type defined by ISO 14443, or both, i.e. using dual interface.
  • smart card devices are capable of storing large amounts of data, performing on-card functions (e.g. encryption, mutual authentication) and interacting intelligently with a smart card reader for various applications (e.g.
  • the smart card devices may be packaged into various form factors (e.g. plastic cards, key fobs, watches, subscriber identification modules used in GSM mobile phones, USB-based tokens, the Secure Digital (SD), mini/micro SD, MMC, VQFN8, SSOP20, TSSOP20, MemorySticks cards, etc).
  • form factors e.g. plastic cards, key fobs, watches, subscriber identification modules used in GSM mobile phones, USB-based tokens, the Secure Digital (SD), mini/micro SD, MMC, VQFN8, SSOP20, TSSOP20, MemorySticks cards, etc).
  • a method for fabricating a dual interface smart card device includes:
  • the antenna coil may be joined to the antenna contacts on the underside of the IC module by using traditional wire soldering, flexible bumps or insertion of conductive materials to solder onto the antenna contacts to form an electrical connection from the IC module to the antenna coil to allow performance of contact-type and contactless-type transactions.
  • a method for fabricating a single interface, i.e. contact-type, smart card device includes:
  • Figure 1B shows a cross-sectional view of a smart card device 100 having a wire-bonded encapsulated IC module 110 embedded in a laminated arrangement.
  • the IC module 110 the IC chip 150 is provided with encapsulation 152 and located directly underside of the contact pad 160.
  • EP 2750082 A1 discloses a card and card manufacturing method that enable clear visual recognition of a display in a display portion even if the card surface has been provided with a matte finish.
  • a method for fabricating a smart card device comprises: providing a carrier core in which a flexible film having a plurality of conductor patterns is interposed between a first substrate and a second substrate, wherein each of the conductor patterns includes:
  • the step of providing a carrier core in which a flexible film having a plurality of conductor patterns is interposed between a first substrate and a second substrate further includes:
  • the step of providing a carrier core in which a flexible film having a plurality of conductor patterns is interposed between a first substrate and a second substrate further includes: abutting the at least one flip chip to the first substrate, and the step of laminating the carrier core to produce a laminated carrier core further includes: embedding the at least one flip chip into the first substrate.
  • the first substrate is devoid of cavity.
  • the first substrate is provided with at least one cavity having at least one dimensional measurement no greater than at least one dimensional measurement of the at least one flip chip, and wherein the at least one cavity of the first substrate is dimensioned to at least partially receive the at least one flip chip therein.
  • the at least one dimensional measurement is selected from the group consisting of height, length and width.
  • the step of providing a carrier core in which a flexible film having a plurality of conductor patterns is interposed between a first substrate and a second substrate further includes: abutting the at least one flip chip to the second substrate, and the step of laminating the carrier core to produce a laminated core further includes: embedding the at least one flip chip into the second substrate.
  • the step of laminating the carrier core to produce a laminated core further includes:
  • the method further comprises: cutting the laminated carrier core into a plurality of individual sections.
  • the step of cutting the laminated carrier core into a plurality of individual sections further includes: cutting each of the individual sections as ID-1 size according to ISO 7810, wherein each of the individual sections includes at most one of the at least one conductor pattern.
  • the at least one contact pad is dimensioned according to ISO 7816.
  • the first and the second vertical plane are non-overlapping with a third vertical plane, wherein an embossing area, which is designated on each of the individual section according to ISO 7811, is arranged at a position in the third vertical plane.
  • a thickness of the first substrate is greater than a thickness of the second substrate.
  • each of the conductor patterns further includes at least one antenna coil arranged on the flexible film and at a position in a fourth vertical plane, and wherein the fourth vertical plane is non-overlapping with the first and the second vertical plane, and wherein the at least one antenna coil is electrically coupled to the at least one flip chip.
  • a smart card device comprises: a laminated carrier core comprising:
  • the laminated carrier core is dimensioned as ID-1 size according to ISO 7810.
  • the contact pad is dimensioned according to ISO 7816.
  • an embossing area which is designated on the laminated carrier core according to ISO 7811, is arranged in a position in a third vertical plane, wherein the third vertical plane is non-overlapping with the first and the second vertical plane.
  • the embossing area is configured to be embossed with information being at least one selected from the group consisting of identification number, name and address.
  • the at least one flip chip and the contact pad are arranged on opposite sides of the flexible film.
  • the at least one flip chip and the contact pad are arranged on same side of the flexible film.
  • the conductor pattern further includes at least one antenna coil electrically coupled to the at least one flip chip, wherein the at least one antenna coil is provided at a position in a fourth vertical plane, and wherein the fourth vertical plane is non-overlapping with the first and the second vertical plane.
  • a method for fabricating a smart card device 200 of contact type interface includes the following steps: In block 401 , a flexible film 230 or sheet inlay, having at least one conductor or circuit pattern 210, is provided.
  • Figure 2B is a schematic representation of a flexible film 230 or sheet inlay having multiple conductor patterns 210.
  • the flexible film 230 is non-metallic and may be made of plastic, e.g. polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • the flexible film 230 may be transparent.
  • Each conductor or circuit pattern 210 includes at least one flip chip 250 arranged on (e.g. bonded to) a bottom surface of the flexible film 230 and disposed at a position in a first vertical plane.
  • Each conductor pattern 210 further includes a metallic contact pad 260 arranged on a top surface of the flexible film 230 and disposed at a position in a second vertical plane.
  • the second vertical plane is non-overlapping with the first vertical plane. Accordingly, the flip chip is not disposed directly under the contact pad 260.
  • Each contact pad 260 provides electrical conductivity when the smart card device is inserted into a smart card reader, e.g. computer, point of sale terminal. Physical and electrical characteristics of the contact pad 260 may be defined according to ISO 7816, in particular ISO 7816-2.
  • Each conductor pattern 210 further includes conductor paths 270 provided on the top and/or the bottom surface of the film 230 to provide electrical connection to and from the flip chip 250, contact pad 260, and/or any other components.
  • the conductor paths 270 include at least one conductor path traversing a thickness of the flexible film 230 to electrically couple the contact pad 260 to the flip chip 250.
  • Such conductor path may be embedded in the flexible film 230 by techniques such as but not limited to piercing through hole or mechanical riveting techniques to provide electrical coupling between the contact pad 260 and the flip chip 250.
  • Figure 2H is a partial close-up view of the flexible film of Figure 2B wherein the contact pad 260 and certain conductor paths 270 are arranged on a top surface of the film 230 while a flip chip 250 is arranged on a bottom surface of the film 230.
  • Figure 2I shows one example of a conductor pattern 210 provided on a flexible film 230 wherein the contact pad 260 and certain conductor paths 270 are arranged on a top surface of the film 230 while a flip chip 250 is arranged on a bottom surface of the film 230.
  • contact pads and conductor paths are formed or built on the flexible film 230 by known methods, e.g. dry etching.
  • the flexible film 230 is overlaid or stacked on a first substrate 220 to produce a temporary core 225a.
  • This step includes applying an adhesive to one or both of the first substrate 220 and flexible film 230, and abutting the bottom surface of the flexible film 230 and the at least one flip chip 250 to the first substrate 220 (see Figure 2D ).
  • the first substrate 220 (see Figure 2A ) is provided with at least one cavity 222 which is arranged to align with and at least partially receive the at least one flip chip when the flexible film 230 is laid or stacked upon the first substrate 220.
  • the cavity 222 has at least one dimensional measurement which is no greater than at least one dimensional measurement of the at least one flip chip 250 such that the at least one cavity 222 of the first substrate 220 is dimensioned to at least partially receive the at least one flip chip 250 therein.
  • the at least one dimensional measurement is selected from the group consisting of height, length and width of the respective cavity 222 or flip chip 250.
  • the first substrate 220 (not shown) is devoid of cavity.
  • the temporary core 225a is subject to a first lamination cycle to produce a laminated temporary core 225b in which the at least one flip chip 250 is embedded into and encapsulated by the first substrate 220.
  • the temporary core 225a is placed or interposed between laminator plates.
  • This arrangement comprising of laminator plates together with the interposed temporary core 225a is fed into a lamination machine where the temporary core 225a is subject to a first hot cycle for a period of time, e.g. about 30 minutes.
  • the first hot cycle includes subjecting the temporary core 225a to high temperature, e.g. at least 80°C, and applying pressure, e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the temporary core 225a.
  • the temporary core 225a is subject to a first cold cycle for a period of time, e.g. about 20 minutes.
  • the first cold cycle includes subjecting the temporary core 225a to low temperature, e.g. no more than 30°Cand applying pressure, e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the temporary core 225a.
  • pressure e.g. at least 20 bars or 20 x 10 5 pascal (Pa)
  • time duration, temperature conditions, and pressure conditions may be modified, as known to persons skilled in the art, according to materials and equipment being used.
  • the first substrate 220 is softened and the flip chip(s) 250 are pressed or embedded into the softened first substrate 220.
  • the temporary core 225a is cooled and hardened.
  • a laminated temporary core 225b is produced in which the at least one flip chip 250 is embedded in the first substrate 220 such that the first substrate 220 provides an encapsulation to the at least one flip chip 250.
  • a second substrate 240 is overlaid or stacked on the laminated temporary core 225b to produce a carrier core 225c.
  • This step includes applying an adhesive to one or both of the second substrate 240 and flexible film 230, abutting the top surface of the film 230 to the second substrate 240 and exposing the at least one contact pad 260 through at least one cavity 242 in the second substrate 240.
  • the second substrate 240 (see Figure 2C ) is provided with at least one cavity 242 which is dimensioned to at least accommodate the contact pad 260 therein.
  • a thickness of the first substrate 220 is greater than a thickness of the second substrate 240.
  • a thickness of the first substrate 220 is substantially the same as a thickness of the second substrate 240.
  • the carrier core 225c is subject to a second lamination cycle to produce a laminated carrier core 225d (see Figure 2F ) in which the at least one contact pad 260 is projected through the at least one cavity 242 in the second substrate 240 to form a continuous even plane from an outer surface of the laminated carrier core 225d to the at least one contact pad 260.
  • the carrier core 225c is placed or interposed between laminator plates.
  • This arrangement comprising of laminator plates together with the interposed carrier core 225c is fed into a lamination machine where the carrier core 225c is subject to a second hot cycle for a period of time, e.g. about 30 minutes.
  • the second hot cycle includes subjecting the carrier core 225c to high temperature, e.g. at least 80°C, and applying pressure, e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the carrier core 225c.
  • the carrier core 225c is subject to a second cold cycle for a period of time, e.g. about 20 minutes.
  • the second cold cycle includes subjecting the carrier core 225c to low temperature, e.g. no more than 30°C, and applying pressure e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the carrier core 225c.
  • low temperature e.g. no more than 30°C
  • pressure e.g. at least 20 bars or 20 x 10 5 pascal (Pa)
  • the carrier core 225c is cooled and hardened.
  • a laminated carrier core 225d is produced. It is to be appreciated that the time duration, temperature conditions, and pressure conditions may be modified, as known to persons skilled in the art, according to materials and equipment being used.
  • each contact pad 260 and, in some embodiments, a portion of the flexible film 230 surrounding the contact pad 260 are urged into and through the space of the cavity 242. Further projection of the contact pad 260 and any surrounding portion of the film 230 through the cavity 242 are constrained by the laminator plates and, accordingly, in the laminated carrier core 225d, a continuous even plane from an outer surface of the laminated carrier core 225d to the at least one contact pad 260 is achieved. In other words, no groove or gap will be observed in the area around contact pad 260. The result is an aesthetically pleasing and continuously even surface on the side of the laminated carrier core 225d where the contact pad 260 is visible and located.
  • the laminated carrier core 225d is cut or diced into individual sections.
  • a schematic representation of the dimensions of an individual section 200 is illustrated in Figure 2F .
  • each individual section 200 is dimensioned for credit card or bank card applications, e.g. ID-1 size according to ISO 7810, and at least includes the least one flip chip 250, contact pad 260 and conductor paths. Accordingly, each section is capable of being provided as a smart card device. It is to be appreciated that each section may take on other dimensions for other applications, e.g. USB token.
  • the first and the second vertical plane are non-overlapping with a third vertical plane wherein an embossing area, which is designated on the ID-1 size laminated carrier core according to ISO 7811, particularly ISO 7811-3, is arranged at a position in the third vertical plane.
  • a method for fabricating a smart card device 200 of dual interface type i.e. contact and contactless interfaces
  • at least one antenna coil 280 is provided or formed, e.g. by dry etching, on the top surface or the bottom surface of the film 230 and at a position in a fourth vertical plane, and wherein the fourth vertical plane is non-overlapping with the first and the second vertical plane, and wherein the at least one antenna coil 280 is electrically coupled to the at least one flip chip 250 by one or more conductor paths 270.
  • each conductor pattern may include two flip chips for respectively operating the contact and contactless interfaces of the smart card device.
  • the antenna coil may take the dimensions of slightly smaller than ID-1 size, half ID-1 size, quarter ID-1 size or other suitable dimensions.
  • FIG. 5 illustrating a method for fabricating a smart card device 200 of contact type interface or dual interface (e.g. contact and contactless interfaces) according to one embodiment of the invention.
  • contact type interface or dual interface e.g. contact and contactless interfaces
  • a carrier core in which a flexible film having a plurality of conductor patterns is interposed between a first substrate and a second substrate.
  • This step includes applying an adhesive to one or both of the first substrate and flexible film, abutting the bottom surface of the flexible film and the at least one flip chip to the first substrate, applying an adhesive to one or both of the second substrate and flexible film, abutting the top surface of the flexible film to the second substrate, and exposing the at least one contact pad through at least one cavity in the second substrate. It is to be appreciated that some of the above steps within block 501 may be interchanged.
  • the at least one flip chip would not be abutted to the first substrate.
  • the carrier core is laminated to produce a laminated carrier core.
  • the carrier core is placed or interposed between laminator plates.
  • This arrangement comprising of laminator plates together with the interposed carrier core is fed into a lamination machine where the carrier core is subject to a hot cycle for a time period, e.g. about 30 minutes.
  • the hot cycle includes subjecting the carrier core to high temperature, e.g. at least 80°C, and applying pressure, e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the carrier core.
  • the core is subject to a cold cycle for a period of time, e.g. about 20 minutes.
  • the cold cycle includes subjecting the carrier core to low temperature, e.g. no more than 30°C, and applying pressure, e.g. at least 20 bars or 20 x 10 5 pascal (Pa), to the carrier core.
  • the time duration, temperature conditions, and pressure conditions may be modified, as known to persons skilled in the art, according to materials and equipment being used.
  • the first substrate is softened and the flip chip(s) are pressed or embedded into the softened first substrate.
  • each contact pad and, in some embodiments, a portion of the flexible film surrounding the contact pad would be urged into and through the space of the cavity. Further projection of the contact pad and any surrounding portion of the film through the cavity are constrained by the laminator plates and, accordingly, in the laminated carrier core, a continuous even plane from an outer surface of the laminated carrier core to the at least one contact pad is achieved. In other words, no groove or gap will be observed in the area around contact pad. The result is an aesthetically pleasing and continuously even surface on the side of the laminated carrier core where the contact pad is visible and located; and an encapsulation provided by the first or the second substrate to the flip chip.
  • the laminated carrier core is cut or diced into individual sections of ID-1 or other sizes.
  • Reference is made to Figure 2G is a cross-sectional view of an IC-embedded device or smart card device 200 cut out from the laminated carrier core 225d and corresponds to the individual section 200 referred to in block 411.
  • Figure 2G shows a flip chip 250 embedded in a laminated carrier core which includes a flexible film 230 having a conductor pattern and interposed between a first substrate 220 and a second substrate 240.
  • the flexible film 230 includes a conductor pattern 210 provided on a top and/or a bottom surface of the film 230.
  • the conductor pattern 210 includes at least one flip chip 250 embedded in the first substrate 220, and arranged on a bottom surface of the film 230 and at a position in a first vertical plane.
  • the conductor pattern 210 further includes a metallic contact pad 260 arranged on a top surface of the film 230 abutting the second substrate 240 and at a position in a second vertical plane.
  • the conductor pattern 210 further includes conductor paths 270 electrically coupling the contact pad 260 to the flip chip 250.
  • At least one conductor path traverses a thickness of the film 230 to electrically couple the contact pad 260 to the at least one flip chip 250.
  • the first vertical plane is non-overlapping with the second vertical plane.
  • the at least one flip chip module 250 is embedded into the first substrate 220 such that the second substrate 240 encapsulates the at least one flip chip module.
  • the at least one contact pad 260 is projected through the at least one cavity in the second substrate 240 to form a continuous even plane from an outer surface of the laminated carrier core to the at least one contact pad 260.
  • the first substrate 220 includes a top or inner surface laminated to a bottom surface of the film 230 including the at least one flip chip 250.
  • the at least one flip chip module is embedded in the first substrate 220 such that the entire body of the second substrate 240 provides an encapsulation to the flip chip module. This encapsulation provides an area and volume which are greater than flip-chip embedded device and protect the flip chip from breakage.
  • the second substrate 240 has a cavity through which the contact pad 260 and, in certain embodiments, a portion of the flexible film 230 surrounding the contact pad 260, are projected for implementing contact-type transactions.
  • the second substrate 240 includes a bottom or inner surface laminated to a top surface of the film 230 and a top or outer surface which forms a continuous even plane from an outer surface of the laminated carrier core to the at least one contact pad 260.
  • a region between the contact pad 260 and the surrounding outer surface of the laminated core or second substrate 240 is devoid of groove or gap which is otherwise present in existing smart cards fabricated by aforementioned existing methods.
  • a thickness of the first substrate 220 is greater than a thickness of the second substrate 240. In another embodiment, a thickness of the first substrate 220 is substantially the same as a thickness of the second substrate 240.
  • the laminated carrier core is dimensioned according to ID-1 size according to ISO 7810.
  • the contact pad 260 is dimensioned according to ISO 7816.
  • an embossing area which is designated on the laminated carrier core according to ISO 7811, particularly ISO 7811-3, is arranged at a position in a third vertical plane, wherein the third vertical plane is non-overlapping with the first and the second vertical plane.
  • the embossing area is configured to be embossed with information, e.g. identification number, name and address. Other types of information may also be embossed.
  • Figure 3G is a cross-sectional view of an IC-embedded device or smart card device 300 having dual interface i.e. contact and contactless interfaces.
  • the smart card device 300 of Figure 3G is similar to Figure 2G except that the film 230 further includes at least one antenna coil 280 provided on the top or bottom surface of the film 230 and is electrically coupled to the at least one flip chip 250.
  • the at least one antenna coil 280 is provided at a position in a fourth vertical plane, wherein the fourth vertical plane is non-overlapping with the first and the second vertical plane.
  • Figure 6 is a cross-sectional view of an IC-embedded device or smart card device 600 in which the flip chip 250 and contact pad 260 are arranged on the same side, e.g. top surface, of the flexible film 230. Accordingly, in this embodiment, the at least one flip chip 250 is embedded into and encapsulated by the second substrate 240.
  • Other details of the smart card device 600 are similar to Figure 2G and therefore will not be reproduced here.
  • a single layer e.g. a film or substrate which is preferably flexible and non-metallic
  • a conductor pattern comprising at least one flip chip, conductor paths and at least one antenna coil.
  • the use of this single sheet inlay with conductor patterns eliminates the steps for milling the laminated substrate to expose portions of the antenna coil and connecting the exposed portions of the antenna coil to the flip chip.
  • the use of this single sheet inlay with conductor patterns also improves the reliability of the connection to the antenna coil, as the contact pad and conductor paths including conductor path connecting the flip chip to antenna coil are laminated onto the film within a same process.
  • the offset arrangement or vertical dis-alignment of the flip chip relative to contact pad reduces the risk of damage to the chip even with repeated use from interfacing the contact pad with a contact-type reader.
  • the IC module may be positioned on anywhere within the ID-1 dimensions other than in the vertical planes for positioning the contact pad, embossing information, and positioning the antenna coil (for dual interface cards). Accordingly, the lifespan and reliability of the IC-embedded device or smart card device of the invention would be improved.
  • the flip chip 250 is embedded in the first substrate 220 or second substrate 240 and thus is provided with an encapsulation (i.e. first substrate) having an area and volume significantly greater than the contact pad 260 and flip chip 250. Consequently, if a force of same magnitude is separately applied to an existing smart card device 100 of Figure 1B and a smart card device 200, 300, 600 of Figures 2G , 3G and 6 according to the invention, the existing smart card device ( Figure 1B ) would be subject to greater pressure per unit area due to smaller encapsulation area and is therefore more likely to break, whereas the smart card device of the invention ( Figures 2G , 3G and 6 ) would be subject to lesser pressure per unit area due to larger encapsulation area and is therefore less likely to break. Accordingly, the larger encapsulation area and volume of the smart card device of the invention ( Figures 2G , 3G and 6 ) provide greater protection to the flip chip and therefore improves the lifespan and reliability of the smart device 200, 300, 600.
  • an encapsulation
  • the contact pad 260 and, in certain embodiments, a portion of the surrounding film is projected through a cavity during lamination and to provide a continuous even plane from an outer surface of the carrier core to the at least one contact pad with no groove or gap between the contact pad and carrier core.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Claims (23)

  1. Procédé de fabrication d'un dispositif de carte à puce (200, 300, 600), le procédé comprenant :
    fourniture d'un noyau porteur (225c) dans lequel un film souple (230) comportant une pluralité de motifs conducteurs (210) est interposé entre un premier substrat (220) et un deuxième substrat (240), caractérisé en ce que chacun des motifs conducteurs (210) comprend :
    au moins une puce retournée (250),
    au moins une pastille de contact (260) disposée avec un décalage par rapport à l'au moins une puce retournée (250),
    au moins un trajet conducteur (270) qui relie électriquement l'au moins une pastille de contact (260) à l'au moins une puce retournée (250), l'au moins un trajet conducteur (270) et l'au moins une pastille de contact (260) étant formés sur le film souple (230),
    l'étape de fourniture d'un noyau porteur (225c) dans lequel un film souple (230) comportant une pluralité de motifs conducteurs (210) est interposé entre un premier substrat (220) et un deuxième substrat (240) comprenant en outre : exposition de l'au moins une pastille de contact (260) à travers au moins une cavité (242) dans le deuxième substrat (240) ; et
    stratification du noyau porteur (225c) afin de produire un noyau porteur stratifié (225d) dans lequel l'au moins une pastille de contact (260) est projetée à travers l'au moins une cavité (242) dans le deuxième substrat (240) pour former un plan régulier continu depuis une surface extérieure du noyau porteur stratifié (225d) à l'au moins une pastille de contact (260) de telle sorte qu'une région entre la pastille de contact (260) et la surface extérieure du noyau porteur stratifié est dépourvue d'interstices.
  2. Procédé selon la revendication 1, la fourniture d'un noyau porteur (225c) dans lequel un film souple (230) comportant une pluralité de motifs conducteurs (210) est interposé entre un premier substrat (220) et un deuxième substrat (240) comprenant en outre :
    recouvrement du premier substrat (220) avec le film souple (230) afin de produire un noyau temporaire (225a) ;
    stratification du noyau temporaire (225a) afin de produire un noyau temporaire stratifié (225b) ; et
    recouvrement d'un deuxième substrat (240) sur le noyau temporaire stratifié (225b) afin de produire le noyau porteur (225c).
  3. Procédé selon l'une quelconque des revendications 1 à 2, la fourniture d'un noyau porteur (225c) dans lequel un film souple (230) comportant une pluralité de motifs conducteurs (210) est interposé entre un premier substrat (220) et un deuxième substrat (240) comprenant en outre :
    aboutement de l'au moins une puce retournée (250) contre le premier substrat (220), l'au moins une puce retournée (250) et l'au moins une pastille de contact (260) étant disposées sur des côtés opposés du film souple (230),
    la stratification du noyau porteur (225c) afin de produire un noyau porteur stratifié (225d) comprenant en outre :
    incorporation de l'au moins une puce retournée (250) dans le premier substrat (220).
  4. Procédé selon la revendication 3, le premier substrat (220) étant dépourvu de cavités.
  5. Procédé selon la revendication 3, le premier substrat (220) étant pourvu d'au moins une cavité (222) qui possède au moins une mesure dimensionnelle inférieure ou égale à au moins une mesure dimensionnelle de l'au moins une puce retournée (250) et l'au moins une cavité (222) du premier substrat (220) étant dimensionnée de manière à recevoir au moins partiellement dans celle-ci l'au moins une puce retournée (250).
  6. Procédé selon la revendication 5, l'au moins une mesure dimensionnelle étant choisie dans le groupe composé de la hauteur, la longueur et la largeur.
  7. Procédé selon l'une quelconque des revendications 1 à 2, la fourniture d'un noyau porteur (225c) dans lequel un film souple (230) comportant une pluralité de motifs conducteurs (210) est interposé entre un premier substrat (220) et un deuxième substrat (240) comprenant en outre :
    aboutement de l'au moins une puce retournée (250) contre le deuxième substrat (240), l'au moins une puce retournée (250) et l'au moins une pastille de contact (260) étant disposées sur le même côté du film souple (230),
    la stratification du noyau porteur (225c) afin de produire un noyau porteur stratifié (225d) comprenant en outre :
    incorporation de l'au moins une puce retournée (250) dans le deuxième substrat (240).
  8. Procédé selon l'une quelconque des revendications 1 à 7, la stratification du noyau porteur (225c) afin de produire un noyau porteur stratifié (225d) comprenant en outre :
    exposition du noyau porteur (225c) à un cycle chaud, l'exposition du noyau porteur (225c) à un cycle chaud comprenant l'exposition du noyau porteur (225c) à une température élevée d'au moins 80 °C et l'application d'une pression d'au moins 20 x 105 pascals (Pa) au noyau porteur (225c) ; et
    exposition du noyau porteur (225c) à un cycle froid, l'exposition du noyau porteur (225c) à un cycle froid comprenant l'exposition du noyau porteur (225c) à une basse température ne dépassant pas 30 °C et l'application d'une pression d'au moins 20 x 105 pascals (Pa) au noyau porteur (225c).
  9. Procédé selon l'une quelconque des revendications 1 à 8, comprenant en outre :
    découpe du noyau porteur stratifié (225d) en une pluralité de sections individuelles.
  10. Procédé selon la revendication 9, la découpe du noyau porteur stratifié (225d) en une pluralité de sections individuelles comprenant en outre :
    découpe de chacune des sections individuelles en tant que taille ID-1 conforme à l'ISO 7810, chacune des sections individuelles comprenant au plus l'un de l'au moins un motif conducteur (210).
  11. Procédé selon la revendication 10, l'au moins une pastille de contact (260) étant dimensionnée conformément à l'ISO 7816.
  12. Procédé selon la revendication 11, une zone de gaufrage étant dessinée sur chacune des sections individuelles conformément à l'ISO 7811.
  13. Procédé selon l'une quelconque des revendications 1 à 12, une épaisseur du premier substrat (220) étant supérieure à une épaisseur du deuxième substrat (240).
  14. Procédé selon l'une quelconque des revendications 1 à 13, chacun des motifs conducteurs (210) comprenant en outre au moins une bobine d'antenne (280) formée sur le film souple (230) et l'au moins une bobine d'antenne (280) étant reliée électriquement à l'au moins une puce retournée (250).
  15. Dispositif de carte à puce (200, 300, 600), comprenant :
    un noyau porteur stratifié comprenant :
    un premier substrat (220) ;
    un deuxième substrat (240) ; et
    un film souple (230) comportant un motif conducteur (210) et interposé entre le premier substrat (220) et le deuxième substrat (240), caractérisé en ce que le motif conducteur (210) comprend :
    au moins une puce retournée (250) incorporée dans le premier (220) ou le deuxième substrat (240),
    une pastille de contact (260) disposée avec un décalage par rapport à l'au moins une puce retournée (250),
    au moins un trajet conducteur (270) qui relie électriquement la pastille de contact (260) à l'au moins une puce retournée (250), l'au moins un trajet conducteur (270) et la pastille de contact (260) étant formés sur le film souple (230), et la pastille de contact (260) étant projetée à travers une cavité (242) dans le deuxième substrat (240) pour former un plan régulier continu depuis une surface extérieure du noyau porteur stratifié à la pastille de contact (260) de telle sorte qu'une région entre la pastille de contact (260) et la surface extérieure du noyau porteur stratifié est dépourvue d'interstices.
  16. Dispositif de carte à puce (200, 300, 600) selon la revendication 15, le noyau porteur stratifié étant dimensionné en tant que taille ID-1 conforme à l'ISO 7810.
  17. Dispositif de carte à puce (200, 300, 600) selon la revendication 16, la pastille de contact (260) étant dimensionnée conformément à l'ISO 7816.
  18. Dispositif de carte à puce (200, 300, 600) selon la revendication 17, la surface extérieure du noyau stratifié comprenant une zone de gaufrage qui est dessinée sur le noyau porteur stratifié conformément à l'ISO 7811.
  19. Dispositif de carte à puce (200, 300, 600) selon la revendication 18, la zone de gaufrage étant configurée pour être gaufrée avec une information qui est au moins l'une choisie parmi le groupe comprenant un numéro d'identification, un nom et une adresse.
  20. Dispositif de carte à puce (200, 300, 600) selon l'une quelconque des revendications 15 à 19, l'au moins une puce retournée (250) et la pastille de contact (260) étant disposées sur des côtés opposés du film souple (230) .
  21. Dispositif de carte à puce (200, 300, 600) selon l'une quelconque des revendications 15 à 19, l'au moins une puce retournée (250) et la pastille de contact (260) étant disposées sur le même côté du film souple (230).
  22. Dispositif de carte à puce (200, 300, 600) selon l'une quelconque des revendications 15 à 21, le motif conducteur (210) comprenant en outre au moins une bobine d'antenne (280) reliée électriquement à l'au moins une puce retournée (250), l'au moins une bobine d'antenne (280) étant formée sur le film souple (230).
  23. Dispositif de carte à puce (200, 300, 600) selon l'une quelconque des revendications 15 à 22, le premier (220) ou le deuxième substrat (240) réalisant une encapsulation de l'au moins une puce retournée (250), l'encapsulation ayant une surface et un volume qui sont supérieurs à la pastille de contact (260).
EP16809206.2A 2015-12-04 2016-11-22 Procédé pour incorporation circuit intégré flip chip Active EP3384434B1 (fr)

Priority Applications (2)

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PL16809206T PL3384434T3 (pl) 2015-12-04 2016-11-22 Sposób osadzania układu scalonego flip chip
MA43370A MA43370B1 (fr) 2015-12-04 2016-11-22 Procédé pour incorporation circuit intégré flip chip

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US201562263105P 2015-12-04 2015-12-04
PCT/SG2016/050574 WO2017095329A1 (fr) 2015-12-04 2016-11-22 Procédé d'incorporation de puce retournée de circuit intégré

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EP (1) EP3384434B1 (fr)
JP (1) JP6544759B2 (fr)
KR (1) KR101897944B1 (fr)
CN (1) CN108292373B (fr)
AU (1) AU2016361882B2 (fr)
BR (2) BR112018011000B1 (fr)
CA (1) CA3002778C (fr)
ES (1) ES2747913T3 (fr)
HU (1) HUE045755T2 (fr)
MA (1) MA43370B1 (fr)
MX (1) MX2018005155A (fr)
PH (1) PH12018500683B1 (fr)
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RU (1) RU2667741C1 (fr)
UA (1) UA118640C2 (fr)
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3063555B1 (fr) * 2017-03-03 2021-07-09 Linxens Holding Carte a puce et procede de fabrication d’une carte a puce
KR102107795B1 (ko) * 2018-11-22 2020-05-28 주식회사 엔에이블 플렉시블 기판을 이용한 스마트 카드 제조방법
DE102019202718B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
DE102019202716B4 (de) * 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit coplanarer topologie für hochfrequenzsignale und verfahren zum herstellen eines derartigen flex-folien-packages
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
CN114981817B (zh) 2020-08-05 2023-06-02 智能科技私人有限公司 具有led的智能卡及其制造方法
DE102021001579A1 (de) 2021-03-25 2022-09-29 Giesecke+Devrient Mobile Security Gmbh Chipkarte und Verfahren zur Herstellung einer Chipkarte
MX2024000745A (es) * 2021-07-16 2024-04-01 Act Identity Tech Limited Modulo de chip y metodo de formacion del mismo.
US11960951B1 (en) * 2022-09-23 2024-04-16 Capital One Services, Llc Transaction card with multiple orientations

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5837153A (en) * 1997-01-15 1998-11-17 Kawan; Joseph C. Method and system for creating and using a logotype contact module with a smart card
US6832730B2 (en) * 2001-07-27 2004-12-21 Storcard, Inc. Smart card with rotating storage
DE10303740B4 (de) * 2003-01-30 2006-09-14 Infineon Technologies Flash Gmbh & Co. Kg Sicherheitsspeicherkarte und Herstellungsverfahren
US9430732B2 (en) * 2014-05-08 2016-08-30 Tego, Inc. Three-dimension RFID tag with opening through structure
US20070290048A1 (en) * 2006-06-20 2007-12-20 Innovatier, Inc. Embedded electronic device and method for manufacturing an embedded electronic device
CN102231193B (zh) * 2011-07-06 2013-05-08 黄艳 一种双界面智能卡
US9390364B2 (en) * 2011-08-08 2016-07-12 Féinics Amatech Teoranta Transponder chip module with coupling frame on a common substrate for secure and non-secure smartcards and tags
JP5482746B2 (ja) * 2011-08-25 2014-05-07 大日本印刷株式会社 カード、カードの製造方法
FR2980015B1 (fr) 2011-09-08 2013-11-22 Sansystems Dispositif electronique a puce et procede de fabrication par bobines
US20140042230A1 (en) * 2012-08-09 2014-02-13 Infineon Technologies Ag Chip card module with separate antenna and chip card inlay using same
WO2014082401A1 (fr) * 2012-11-30 2014-06-05 Xue Yuan Carte à puce bi-interface et procédé de fabrication de celle-ci
FR2999753B1 (fr) * 2012-12-13 2015-02-13 Oberthur Technologies Procede de fabrication par lamination en continu de cartes a microcircuit du type a contact
EP2784724A3 (fr) * 2013-03-27 2015-04-22 Féinics AmaTech Teoranta Dépôt sélectif de particules magnétiques et utilisation de matériau magnétique comme support pour déposer d'autres particules

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

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CN108292373B (zh) 2019-07-23
HUE045755T2 (hu) 2020-01-28
JP6544759B2 (ja) 2019-07-17
AU2016361882A1 (en) 2018-04-19
KR101897944B1 (ko) 2018-09-12
PT3384434T (pt) 2019-10-28
BR112018011000A2 (pt) 2018-12-04
BR112018011000B1 (pt) 2020-10-20
MX2018005155A (es) 2018-08-15
US10558906B2 (en) 2020-02-11
EP3384434A1 (fr) 2018-10-10
PH12018500683A1 (en) 2018-10-15
CA3002778A1 (fr) 2017-06-08
UA118640C2 (uk) 2019-02-11
ES2747913T3 (es) 2020-03-12
US20200134413A1 (en) 2020-04-30
CA3002778C (fr) 2018-09-18
KR20180069000A (ko) 2018-06-22
CN108292373A (zh) 2018-07-17
US20180300597A1 (en) 2018-10-18
BR122019027776B1 (pt) 2020-10-20
JP2019500749A (ja) 2019-01-10
WO2017095329A1 (fr) 2017-06-08
PL3384434T3 (pl) 2020-01-31
AU2016361882B2 (en) 2018-11-01
ZA201802189B (en) 2019-08-28
RU2667741C1 (ru) 2018-09-24
US10685275B2 (en) 2020-06-16
MA43370B1 (fr) 2019-10-31
PH12018500683B1 (en) 2018-10-15

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