EP3179515A1 - Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements - Google Patents

Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements Download PDF

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Publication number
EP3179515A1
EP3179515A1 EP15199187.4A EP15199187A EP3179515A1 EP 3179515 A1 EP3179515 A1 EP 3179515A1 EP 15199187 A EP15199187 A EP 15199187A EP 3179515 A1 EP3179515 A1 EP 3179515A1
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Prior art keywords
passivation
layer
major surface
substrate
semiconductor device
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EP15199187.4A
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English (en)
French (fr)
Inventor
Johannes Josephus Theodorus Marinus Donkers
Godefridus Adrianus Maria Hurkx
Jeroen Antoon Croon
Mark Andrzej Gajda
Jan Sonsky
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Nexperia BV
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Nexperia BV
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Priority to EP15199187.4A priority Critical patent/EP3179515A1/de
Priority to US15/356,519 priority patent/US10157809B2/en
Priority to US15/356,527 priority patent/US10546816B2/en
Priority to CN202210166947.4A priority patent/CN114530500A/zh
Priority to CN201611122318.2A priority patent/CN107039517A/zh
Publication of EP3179515A1 publication Critical patent/EP3179515A1/de
Withdrawn legal-status Critical Current

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • the present specification relates to a semiconductor device and to a method of making a semiconductor device.
  • GaN/AlGaN high electron mobility transistors and GaN/AlGaN Schottky diodes have drawn a lot of attention regarding their potential to replace Si or SiC for use as High Voltage (HV) devices.
  • HV High Voltage
  • Devices of this kind often include a passivation layer that may be used to supress the formation of interface states at a major surface of the substrate.
  • these surface states may be charged, leading to changes in the charge balance. For applications that involve switching, this may translate into differences between the static condition and the switching condition.
  • charge trapping can reduce the current or increase the on-state resistance of the device. This degradation of the electric performance may be referred to as current-collapse in high voltage devices or dispersion in high frequency devices.
  • a semiconductor device comprising:
  • a method of making a semiconductor device comprising:
  • Part of the trapping that may give rise to current collapse or dispersion in a semiconductor device e.g. a HEMT or Schottky diode having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas (hereinafter also referred to as "2DEG") at an interface between the AlGaN layer and the GaN layer
  • 2DEG two dimensional electron gas
  • the amount of trapping in this region may depend on the resistance of leakage paths in the semiconductor, particularly across a depletion region that forms below the 2DEG. This resistance may be altered by using a different passivation material on top of the semiconductor.
  • the first passivation layer may be asymmetrically arranged with respect to the first of the electrical contacts.
  • the first passivation layer that is asymmetrically arranged in this way may include an extension located on one side of the first electrical contact. The extension may extend toward another electrical contact of the device.
  • the first area may include one or more islands located between two of the electrical contacts of the device.
  • the passivation layers may comprise silicon nitride.
  • the different passivation materials may comprise compositions of silicon nitride that include different proportions of silicon.
  • one of the passivation materials may be stoichiometric silicon nitride and another of the passivation materials (e.g. the first passivation material) may be a composition of silicon nitride that is more silicon rich than stoichiometric silicon nitride.
  • a device may operate at high voltages (e.g. voltages in the range 200-1000V) and/or at high frequencies (e.g. frequencies in the range 1kHz-100MHz).
  • high voltages e.g. voltages in the range 200-1000V
  • high frequencies e.g. frequencies in the range 1kHz-100MHz
  • power conversion applications of grid voltage to appliance voltage using power factor correction (PFC) boost converters and/or resonant DC/DC convertors may require power transistors operating in the range 200V to 800V.
  • the operating frequencies may be in the range 10kHz to 100MHz.
  • a substrate 102 In a first step shown in Figure 5A , there is provided a substrate 102.
  • the substrate 102 includes an AlGaN layer 112 and a GaN layer 106.
  • the underlying part of the substrate 102 may, for instance, comprise silicon, silicon carbide, a glass or a ceramic.
  • One or more buffer layers 104 may be located between the GaN layer 106 and the underlying part of the substrate 102, for matching the lattice of the GaN layer 106 to the underlying part of the substrate 102.
  • the buffer layer(s) 106 may, for instance, comprise GaN and may be doped (e.g. with carbon and/or iron).
  • a GaN cap layer may be provided on the AlGaN layer 112, although this is no shown in the example of Figure 5 .
  • a further opening may also be formed intermediate the opening 113 and the opening 114, for receiving a Schottky gate contact of the HEMT, although this is not shown in the present example. It is also envisaged that the device may be a MISHEMT, in which case the gate contact may simply be located above one or both of the passivation layers, in between the source contact and the drain contact.
  • the source contact and the drain contact of the device 200 may be formed.
  • the source contact and the drain contact may be configured similarly to the source and drain contacts described above in relation to Figure 5 .
  • the source contact in this example may include a Ti/Al (or, e.g. Ta/Al as noted above) electrode portion 230 and a layer 232 of TiW(N) (or, e.g. TiN, TiW, Pt as noted above) located on the electrode portion 230, which may act as a diffusion barrier
  • the drain contact may include a Ti/Al (or, e.g. Ta/Al as noted above) electrode portion 240 and a layer 242 of TiW(N) (or, e.g. TiN, TiW, Pt as noted above) located on the electrode portion 240, which may again act as a diffusion barrier.
  • the AlGaN layer 312 is located on the GaN layer 306. As discussed previously, a two dimensional electron gas may form at an interface between the AlGaN layer 312 and the GaN layer 306. A current flowing within this 2DEG may form the basis for the operation of the device.
  • a second passivation layer 320 is initially provided on a major surface of the substrate 302.
  • the major surface in this example is the (upper) surface of the AlGaN layer 312, although in other examples, the major surface may be the (upper) surface of a GaN cap layer, if one is present on the AlGaN layer 312.
  • the opening for the drain contact extends through the first passivation layer 310 but not the second passivation layer 320
  • a consequence of the fact that the first passivation layer 310 overlaps with the second passivation layer 320 in the second area of the device 300 is that the opening for the source contact extends through both the first passivation layer 310 and the second passivation layer 320.
  • a further opening may also be formed intermediate the source contact and drain contact, for receiving a Schottky gate contact of the HEMT, although this is not shown in the present example.
  • the device may be a MISHEMT, in which case the gate contact may simply be located above one or both of the passivation layers, in between the source contact and the drain contact.
  • the resulting device 300 has two passivation layers 310, 320, which each contact the major surface of the substrate 300 in respective areas.
  • the area in which the first passivation layer 310 contacts the major surface of the substrate 302 is adjacent a first contact (the drain contact) of the device 300.
  • the area in which the second passivation layer 320 contacts the major surface of the substrate 302 may be adjacent a second contact (the source contact) of the device 300.
  • a gate contact may be located between the source contact and the drain contact.
  • the gate contact may be located in an opening in both first passivation layer 310 and the second passivation layer 320 (or on the first and second passivation layers 310, 320, in the case of a MISHEMT).
  • the first passivation layer which may substantially surround a first of the electrical contacts on the major surface (e.g. the drain contact of a HEMT or the cathode of a Schottky diode as described above) may be asymmetrically arranged with respect to that contact.
  • the first passivation layer may include an extension located on one side of the first electrical contact. This extension may extend toward another electrical contact of the device (e.g. the gate contact of a HEMT or the anode of a Schottky diode).
  • the use of different silicon nitride passivation layers can affect the conductivity of the vertical defects in the GaN layers of a semiconductor device. If the vertical defects are conductive enough, they may locally short the above mentioned pn junction so that no depletion layer can build up locally.
  • Stoichiometric LPCVD silicon nitride, Si3N4 has typically a refractive index of around 2.0 and a stress of around 1000MPa. Stoichiometric silicon nitride can result in lowly-conducting vertical defects, which may lead to a strong dynamic on-resistance, together with a very low reverse bias leakage from the drain of the device to gate of the device.
  • a more silicon rich LPCVD silicon nitride which may for example be deposited by changing the standard gas flows of dichloresilane (DCS) and ammonia (NH3) that may be used to deposit stoichiometric silicon nitride.
  • One such composition of silicon rich silicon nitride may have a refractive index of 2.2 and a stress of 100MPa.
  • the second passivation material may comprise stoichiometric silicon nitride).
  • the passivation material of the first passivation layers 110, 210, 310 may comprise silicon nitride that is more silicon rich than the passivation material of the first passivation layers 120, 220, 320.
  • a device having passivation layers of this kind may allow for optimisation of the trade-off between leakage current and current collapse/dispersion, as discussed previously.
  • passivation materials comprising SiN
  • other passivation materials may be used.
  • the passivation layers of the device may comprise passivation materials such as silicon oxide or Semi-Insulating Polycrystalline Silicon (SIPOS).
  • SIPOS Semi-Insulating Polycrystalline Silicon
  • Further examples include atomic layer depositions of materials such as AlN.
  • Passivation materials that produce more leaky vertical defects may be located near the drain contract (in the case of a HEMT) or cathode (in the case of a Schottky diode) of the device while passivation materials that produce less leaky vertical defects may be located near the gate (in the case of a HEMT) or anode (in the case of a Schottky diode) of the device in a manner similar to that described above.
  • the device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer.
  • the device also includes a plurality of electrical contacts located on a major surface of the substrate.
  • the device further includes a plurality of passivation layers located on the major surface of the substrate.
  • the plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface.
  • the first and second passivation materials are different passivation materials.
  • the different passivation materials may be compositions of silicon nitride that include different proportions of silicon.
EP15199187.4A 2015-12-10 2015-12-10 Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements Withdrawn EP3179515A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP15199187.4A EP3179515A1 (de) 2015-12-10 2015-12-10 Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements
US15/356,519 US10157809B2 (en) 2015-12-10 2016-11-18 Semiconductor device and method of making a semiconductor device with passivation layers providing tuned resistance
US15/356,527 US10546816B2 (en) 2015-12-10 2016-11-18 Semiconductor substrate with electrically isolating dielectric partition
CN202210166947.4A CN114530500A (zh) 2015-12-10 2016-12-08 半导体装置和制作半导体装置的方法
CN201611122318.2A CN107039517A (zh) 2015-12-10 2016-12-08 半导体装置和制作半导体装置的方法

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EP15199187.4A EP3179515A1 (de) 2015-12-10 2015-12-10 Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements

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EP3179515A1 true EP3179515A1 (de) 2017-06-14

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CN109950323B (zh) * 2017-12-20 2022-04-08 中国科学院苏州纳米技术与纳米仿生研究所 极化超结的ⅲ族氮化物二极管器件及其制作方法
CN109659366A (zh) * 2018-12-21 2019-04-19 英诺赛科（珠海）科技有限公司 高电子迁移率晶体管及其制造方法
US10937873B2 (en) 2019-01-03 2021-03-02 Cree, Inc. High electron mobility transistors having improved drain current drift and/or leakage current performance
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