EP3138119A1 - Procédé de production de semi-conducteurs à dopage différent - Google Patents

Procédé de production de semi-conducteurs à dopage différent

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Publication number
EP3138119A1
EP3138119A1 EP15715773.6A EP15715773A EP3138119A1 EP 3138119 A1 EP3138119 A1 EP 3138119A1 EP 15715773 A EP15715773 A EP 15715773A EP 3138119 A1 EP3138119 A1 EP 3138119A1
Authority
EP
European Patent Office
Prior art keywords
composition
semiconductor substrate
silicon
dopant
sime
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP15715773.6A
Other languages
German (de)
English (en)
Inventor
Christoph Mader
Christian GÜNTHER
Joachim Erz
Susanne Martens
Jasmin Lehmkuhl
Stephan Traut
Odo Wunnicke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Evonik Operations GmbH
Original Assignee
Evonik Degussa GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Evonik Degussa GmbH filed Critical Evonik Degussa GmbH
Publication of EP3138119A1 publication Critical patent/EP3138119A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2225—Diffusion sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for producing differently doped semiconductors, the semiconductor obtainable by the method and their use.
  • Photovoltaics is based on the generation of free charge carriers in one
  • Metal contacts to generate a high doping to reduce the contact resistance
  • a low doping is advantageous in order to reduce the recombination and the free-carrier-absorption.
  • US 2012/0052618 A1 discloses a method for selectively doping a wafer by using a liquid, dopant-containing silicon precursor compound, which is applied to the wafer, partially into elemental silicon
  • the object of the present invention to provide a method for doping a semiconductor, which makes it possible to produce differently doped regions with respect to the type and concentration of the doping atoms on the semiconductor.
  • the present object is achieved by the inventive Flussigphasen compiler for doping a semiconductor substrate, in particular a silicon wafer, in which
  • a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate to produce one or more regions (e) coated with the second composition of the surface of the semiconductor substrate, the one or more regions (e) coated with the first composition and the one or more regions coated with the second composition are different and do not overlap or substantially overlap and wherein the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa;
  • the portions of the surface of the semiconductor substrate coated with the first composition and the second composition are each partially or fully activated;
  • Composition coated non-activated areas of the surface of the semiconductor substrate are each oxidized.
  • the semiconductor substrate is heated to a temperature at which the dopants diffuse from the coating into the semiconductor substrate.
  • compositions used in this process are preferably
  • a precursor is understood to mean a chemical compound which is essentially soluble in the composition in the composition or a liquid chemical compound of one or more semiconductor atoms which can be converted into the semiconductor material thermally or with electromagnetic radiation. Also when the invention is described below with reference to such
  • a liquid-phase process is to be understood as meaning a process in which at least one liquid composition (comprising at least one liquid precursor of the semiconductor or dopant material in which other other liquid or solid dopant precursors, semiconductor precursors and optionally other additives are dissolved or dispersed) and / or at least one solvent-containing formulation containing the (even liquid or solid) dopants, optionally semiconductor precursors (and optionally further additives) are applied to the substrate to be doped.
  • at least one liquid composition comprising at least one liquid precursor of the semiconductor or dopant material in which other other liquid or solid dopant precursors, semiconductor precursors and optionally other additives are dissolved or dispersed
  • solvent-containing formulation containing the (even liquid or solid) dopants optionally semiconductor precursors (and optionally further additives) are applied to the substrate to be doped.
  • silicon-based semiconductor precursors these may then subsequently be thermally or with electromagnetic radiation, for example, into a substantially elementary, amorphous, monocrystalline and / or
  • Dopant precursors are essentially converted into the underlying dopants and incorporated into the resulting silicon-containing coating.
  • the resulting doped semiconductor substrate is thus a
  • Semiconductor substrate that has been coated with at least one doped semiconductor layer.
  • the substrate itself may (but does not have to) continue to be doped by diffusion of dopant.
  • an “activation” is to be understood as meaning a “conversion” of the coating from a precursor composition into said elemental, amorphous, monocrystalline and / or polycrystalline silicon-containing coating.
  • "Partial activation” here means that not the entire Coating is converted, but only selected sub-areas
  • Coating i. 100% of the area, activated.
  • the p-type or n-type dopants can be used in particular in the form of
  • the at least one n-type dopant may preferably consist of phosphorus-containing dopants, in particular PH 3 , P 4 , P (SiMe 3 ) 3 , PhP (SiMe 3 ) 2 , CI 2 P (SiMe 3 ), PPh 3 , PMePh 2 and P (t-Bu) 3 , arsenic-containing dopants, in particular As (SiMe 3 ) 3 , PhAs (SiMe 3 ) 2 , CI 2 As (SiMe 3 ), AsPh 3 , AsMePh 2 , As (t-Bu) 3 and AsH 3 , antimony-containing dopants, especially Sb (SiMe 3 ) 3 , PhSb (SiMe 3 ) 2 , CI 2 Sb (SiMe 3 ), SbPh 3 , SbMePh 2 and Sb (t-Bu) 3
  • the at least one p-type dopant may preferably be selected from boron-containing dopants, in particular B 2 H 6 , BH 3 * THF, BEt 3 , BMe 3 , B (SiMe 3 ) 3 , PhB (SiMe 3 ) 2 , CI 2 B (SiMe 3 ), BPh 3 , BMePh 2 , and B (t-Bu) 3 , and mixtures thereof.
  • boron-containing dopants in particular B 2 H 6 , BH 3 * THF, BEt 3 , BMe 3 , B (SiMe 3 ) 3 , PhB (SiMe 3 ) 2 , CI 2 B (SiMe 3 ), BPh 3 , BMePh 2 , and B (t-Bu) 3 , and mixtures thereof.
  • At least one as used herein means 1 or more, ie 1, 2, 3, 4, 5, 6, 7, 8, 9 or more. With respect to an ingredient, the indication refers to the kind of the ingredient and not to the absolute number of molecules. "At least one dopant” thus means, for example, at least one type of dopant, ie that one type of dopant or a mixture of several different dopants can be used. The term, together with amounts, refers to all compounds of the type indicated which are included in the composition / mixture, i. that the composition does not contain any further compounds of this type beyond the stated amount of the corresponding compounds.
  • compositions are, unless explicitly stated otherwise, by weight, in each case based on the corresponding composition.
  • the activated coatings which can be prepared by the process according to the invention can contain or consist of elemental silicon, for example in amorphous, monocrystalline and / or polycrystalline form, in combination with the respective dopant.
  • the activated coatings produced by the process according to the invention may be coatings which, in addition to elemental silicon and the respective dopant, also contain other elements.
  • the oxidized coatings which can be prepared by the process according to the invention can be silicon oxide contain or consist of in combination with the respective dopant. Also in these coatings optionally other elements may be included.
  • the coatings can be treated with the first
  • structured coating is to be understood as meaning a coating which does not completely or substantially completely cover the substrate but which partially covers the substrate to form a structuring
  • structured layers are printed conductors (eg for contacts), finger structures or point-like structures (eg for emitter and base regions in back-contact solar cells) and selective emitter structures in solar cells.
  • the first composition containing at least one first dopant and the second composition containing at least one second dopant are applied to different, non-or substantially non-overlapping regions of the invention
  • substantially overlapping means that the areas do not overlap with each other by more than 5% of their respective area, it is preferred that the areas do not overlap at all, but it may be process-related
  • the application can be structured in each case, so that the first composition and the second
  • composition for example, one-sided in an interlocking structure
  • a third composition containing no dopant may be applied to the first and / or second composition
  • coated activated and / or non-activated areas are applied. This means that the coating of the first or the second composition with a
  • Coating consisting of the third composition, be coated.
  • These Composition, except for the absence of the dopant, may be identical to the first and / or second composition in terms of ingredients.
  • This coating with the third composition prevents contamination of the diffusion furnace commonly used in this step in the outdiffusion step, i. an escape of the doping atoms in the furnace atmosphere.
  • compositions according to the present invention i. the first and second composition and the optional third composition, in particular SATP conditions (25 ° C, 1, 013 bar) to understand liquid compositions containing either at least one liquid in the case of SATP conditions-containing precursor or at least one solvent and contain or consist of at least one liquid or solid silicon-containing precursor in SATP conditions, in each case in combination with the respective dopant.
  • SATP conditions 25 ° C, 1, 013 bar
  • compositions comprising at least one solvent and at least one liquid or solid in SATP conditions containing silicon-containing precursor can be achieved in combination with the respective dopant, since they can be particularly good print.
  • the precursors generally include all suitable polysilanes, polysilazanes and polysiloxanes.
  • Precursors are silicon-containing nanoparticles.
  • the precursors can be used both individually and in mixture. Particular preference is given to using polysilanes. These can also be used individually or in mixture.
  • Corresponding formulations are particularly suitable for the production of high-quality, thin and fine layers from the liquid phase, wet well in the coating process common substrates and have sharp edges after the
  • the formulation is liquid, since it is so easy to handle.
  • the isomers of these compounds can be linear or branched.
  • Preferred non-cyclic hydridosilanes are trisilane, iso-tetrasilane, n-pentasilane, 2-silyl-tetrasilane and neopentasilane and octasilane (ie n-octasilane, 2-silyl-heptasilane, 3-silyl-heptasilane, 4-silyl-heptasilane, 2 , 2-disilyl-hexasilane, 2,3-disilyl-hexasilane, 2,4-disilyl-hexasilane, 2,5-disilyl-hexasilane, 3,4-disilyl-hexasilane, 2,2,3
  • the hydridosilane of said generic formula is a branched hydridosilane, which leads to more stable solutions and better layers than a linear hydridosilane.
  • hydridosilane isotetrasilane, 2-silyltetra-silane, neopentasilane or a mixture of nonasilane isomers which can be prepared by thermal treatment of neopentasilane or by a method described by Holthausen et al. described rule (Poster presentation: A. Nadj, 6th European Silicon Days, 2012).
  • the hydridosilane oligomer is the oligomer of a hydridosilane compound, and preferably the oligomer of a hydridosilane.
  • the formulation of the invention is particularly well suited for the production of thin layers, if the
  • Hydridosilane oligomer has a weight average molecular weight of 200 to 10,000 g / ml. Methods for their preparation are known in the art. Appropriate
  • Molecular weights can be determined by gel permeation chromatography using a linear polystyrene column with cyclooctane as eluent against polybutadiene as reference.
  • the hydridosilane oligomer is preferably obtained by oligomerization of non-cyclic hydridosilanes. Unlike hydridosilane oligomers of cyclic hydridosilanes, these oligomers exhibit dissociative dissociation due to the different nature of the reaction
  • Substrate surface well can be used particularly well for the production of thin layers and lead to homogeneous and smooth surfaces. Even better results are shown by oligomers of noncyclic, branched hydridosilanes.
  • a particularly preferred hydridosilane oligomer is an oligomer obtainable by thermal reaction of a composition comprising at least one non-cyclic hydridosilane having a maximum of 20 silicon atoms in the absence of a catalyst at temperatures of ⁇ 235 ° C.
  • Corresponding hydridosilane oligomers and their preparation are described in WO
  • This oligomer has even better properties than the other hydridosilane oligomers of non-cyclic, branched hydridosilanes.
  • the Hydridosilan- oligomer may have other radicals in addition to hydrogen and silicon. So can Advantages of the layers made with the formulations result when the oligomer is carbonaceous.
  • Corresponding carbon-containing hydridosilane oligomers can be prepared by co-oligomerizing hydridosilanes with hydrocarbons.
  • the hydridosilane oligomer is an exclusively hydrogen- and silicon-containing compound which therefore has no halogen or alkyl radicals.
  • hydridosilane oligomers that are already doped.
  • the hydridosilane oligomers are preferably boron- or phosphorus-doped.
  • Corresponding hydridosilane oligomers can be produced by adding the corresponding dopants already during their preparation.
  • non-doped hydridosilane oligomers already prepared may be p-doped with the above-mentioned p-type or n-type dopants or n-doped by an energetic process (e.g., UV irradiation or thermal treatment).
  • the proportion of the hydridosilane (s) is preferably from 0.1 to 99% by weight, more preferably from 1 to 50% by weight, very preferably from 1 to 30% by weight, based on the total weight of the particular composition.
  • the proportion of the or the hydridosilane oligomers is preferably 0.1 to 99 wt .-%, more preferably 1 to 50 wt .-%, most preferably 1 to 20 wt .-% based on the total mass of the respective composition.
  • the proportion of the hydridosilane oligomer in the particular composition is furthermore preferably 40 to 99.9% by weight, particularly preferably 60 to 99, very particularly preferably 70 to 90% by weight, based on the total mass, in order to achieve particularly good results present hydridosilane and hydridosilane oligomer.
  • compositions used in the process according to the invention need not contain a solvent. However, they preferably have at least one solvent. If they contain a solvent, the proportion thereof is preferably 0.1 to 99% by weight, more preferably 25 to 95% by weight, very preferably 60 to 95% by weight, based on the total weight of the particular formulation. Very particular preference is given to compositions comprising 1-30% by weight of hydridosilane, 1-20% by weight of hydridosilane oligomer and 60-95% by weight of solvent, based on
  • Solvents which may preferably be used for the compositions described herein are those selected from the group consisting of linear, branched or cyclic saturated, unsaturated or aromatic hydrocarbons having 1 to 12 carbon atoms (optionally partially or completely halogenated), alcohols, ethers, carboxylic acids, Esters, nitriles, amines, amides, sulfoxides and water.
  • n-pentane n-hexane, n-heptane, n-octane, n-decane, dodecane, cyclohexane, cyclooctane, cyclodecane, dicyclopentane, benzene, toluene,
  • Ethylene glycol methyl ethyl ether diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, tetrahydrofuran, p-dioxane, acetonitrile, dimethylformamide, dimethyl sulfoxide, dichloromethane and chloroform.
  • the at least one dopant In addition to the at least one dopant, the at least one hydridosilane and the at least one
  • Hydridosilane oligomer and the optionally present solvents or other substances, in particular nanoparticles or additives to adjust the rheological properties.
  • solvents or other substances in particular nanoparticles or additives to adjust the rheological properties.
  • the compositions used do not consist of nanoparticles.
  • the semiconductor substrate used is in particular silicon
  • Used wafers may, for example, be polycrystalline or monocrystalline and possibly already ground-doped.
  • This base doping may be a doping with an n- or p-type dopant, as already defined above.
  • the application of the compositions is preferably carried out by a liquid phase method selected from printing processes (in particular flexographic / gravure printing, nanoimaging or microimprinting, inkjet printing, offset printing, reverse offset printing, digital offset printing and screen printing) and spraying processes (pneumatic Spraying, ultrasonic spraying, electrospray method).
  • printing processes in particular flexographic / gravure printing, nanoimaging or microimprinting, inkjet printing, offset printing, reverse offset printing, digital offset printing and screen printing
  • spraying processes pneumatic Spraying, ultrasonic spraying, electrospray method.
  • all known application methods are suitable which enable a structured coating with two different compositions without substantial overlap.
  • compositions can, in principle, be carried out flat (that is to say unstructured) or structured.
  • An areal plot may be made, in particular, in cases where the first and second compositions are applied to different sides of the wafer.
  • Particularly fine structures can with the invention
  • a corresponding structured application can e.g. be realized by the use of printing processes. It is also possible structuring via surface pretreatment of the substrate, in particular via a modification of the
  • Coating composition by a local plasma or corona treatment and thus a local removal of chemical bonds to the substrate surface or a local activation of the surface (eg Si-H termination), by chemical etching or applying chemical compounds (in particular by self-assembled monolayers ).
  • structuring is achieved in particular by virtue of the fact that the precursor-containing coating composition is more favorable only at the predefined regions
  • the process according to the invention can preferably be carried out by printing processes.
  • the method according to the invention is particularly preferably carried out in such a way that the first and the second composition are applied simultaneously or successively without overlapping to different areas of the wafer, the resulting ones
  • Coating areas are oxidized on the wafer.
  • particularly fine structures with different properties can be produced.
  • With a corresponding method particularly good and simply structured layers can be produced.
  • the coated substrate can furthermore preferably be dried before the conversion in order to remove any solvent present.
  • the heating temperature should be less than 200 ° C.
  • a partial activation can be done for example by using a mask or by using contact stamps.
  • the activation of the method according to the invention can in principle be carried out differently.
  • the activation or conversion is carried out thermally and / or using electromagnetic radiation and / or by electron or ion bombardment.
  • Thermal activation is preferably carried out at temperatures of 200-1000 ° C., preferably 250-750 ° C., particularly preferably 300-700 ° C. thermal
  • Activation times are preferably between 0.01 ms and 360 min.
  • the activation time is more preferably between 0.1 ms and 10 minutes, more preferably between 1 s and 120 s.
  • Corresponding rapid energetic process guides can be, for example, by the use of an IR radiator, a hot plate, a Schuttvs, a furnace, a flash lamp, a plasma (in particular a hydrogen plasma) or a corona with a suitable gas composition, an RTP system, a microwave system or a
  • Electron beam treatment (if necessary, in the preheated or warmed up state) done.
  • activation can be effected by irradiation with electromagnetic radiation, in particular with UV light.
  • the activation time may be preferably between 1 s and 360 min.
  • the structuring or (partial) activation can be realized in this case, for example by using point or line-shaped radiation sources or by the use of masks.
  • the activation is particularly preferably carried out by irradiation with laser radiation.
  • the use of point or line-shaped radiation sources, in particular of lasers, is advantageous, since hereby particularly fine
  • ions can be generated in different ways. Often come impact ionization, in particular
  • MALDI Desorption / Ionization
  • ESI electrospray ionization
  • Structuring can also be achieved via masks in the case of ion bombardment.
  • Partial activation thus results in areas on the substrate where the coating composition thereon has been converted and areas where the coating composition thereon has not been converted.
  • an activation can be understood to mean a conversion of the deposited precursors of the resulting coating film into amorphous or crystalline semiconductor layers.
  • the activation is preferably carried out in such a way that, after the conversion, structured amorphous or crystalline, in particular polycrystalline or monocrystalline, silicon layers result. Means and ways for this are known in the art.
  • the activation is performed such that amorphous silicon (a-Si) is formed. If not dried before conversion, unconverted areas can be dried after conversion.
  • the drying is also carried out here at temperatures below 200 ° C, preferably in the range of 100 to 200 ° C.
  • defined states can also be set in the regions with unconverted coating, with which the optical and electrical properties of the coating can be controlled after the subsequent optional oxidation step.
  • unconverted coating on the substrate can be oxidized.
  • silicon precursor compounds silicon oxide-containing layer structures thus arise in the regions with unconverted coating.
  • the converted silicon-containing regions already obtained by the previous conversion are not oxidized, so that silicon-containing layer structures which directly adjoin silicon oxide-containing layer structures can be obtained by the process according to the invention. Due to the use of differently doped starting compositions, n-doped silicon-containing, n-doped silicon oxide-containing, p-doped silicon-containing and p-doped silicon oxide-containing layer structures are thus obtained.
  • the silicon-containing and silicon oxide-containing layer structures differ in their diffusion rates, so that in the diffusion step, the doping atoms diffuse from the silicon-containing layers with a higher diffusion rate into the underlying substrate than the doping atoms from the silicon oxide-containing layers. Therefore, highly doped regions are created under the activated regions, while low-doped regions are created under the non-activated, oxidized regions.
  • the oxidation takes place in an oxygen-containing atmosphere at a temperature ⁇ 300 ° C, more preferably at a temperature ⁇ 150 ° C, particularly preferably at a temperature ⁇ 100 ° C. Most preferably, the oxidation takes place in one
  • the oxygen-containing atmosphere preferably has an oxygen concentration of 1 to 100 mol% and may contain nitrogen or argon as further gaseous constituents, for example.
  • Particular preference is furthermore the oxidation with oxidizing agents selected from the group consisting of ozone, carbon dioxide, hydrogen peroxide (H 2 0 2 ), water vapor (H 2 0), a mono- or polyhydric alcohol, a ketone, a carboxylic acid (especially trichloroacetic acid), a carbonic acid ester and mixtures comprising trichloroacetic acid and oxygen, and HCl and oxygen.
  • oxidizing agents selected from the group consisting of ozone, carbon dioxide, hydrogen peroxide (H 2 0 2 ), water vapor (H 2 0), a mono- or polyhydric alcohol, a ketone, a carboxylic acid (especially trichloroacetic acid), a carbonic acid ester and mixtures comprising trichloroacetic acid and oxygen, and HCl and oxygen
  • Oxidizing agents are known to the person skilled in the art. Particularly preferred is the use of ozone, carbon dioxide, hydrogen peroxide (H 2 0 2 ), water vapor (H 2 0), a carboxylic acid (especially trichloroacetic acid), a carbonic acid ester and a mixture comprising trichloroacetic acid and oxygen.
  • the method described for doping silicon wafers can furthermore be carried out several times simultaneously or chronologically in succession with respect to a wafer, although corresponding areas of the wafer surface are coated either several times with the first composition or several times with the second composition but not with both compositions ,
  • the activation of different coatings can take place simultaneously or successively. That is, the invention encompasses both
  • the diffusion step i.
  • activation is performed to form crystalline silicon. It is particularly preferred to carry out the activation so that the Silicon epitaxially crystallized. That is, the deposited doped precursor conforms to the silicon wafer in the crystal structure. Especially when using
  • the epitaxially crystallized region thus has a very high electronic quality and does not have to be subsequently removed. This is advantageous, as this eliminates the additional process step of removing.
  • the epitaxial growth is preferably carried out at temperatures of 600 - 1200 ° C, which prevail for a period of 30 s - 3 hours.
  • epitaxial growth can also be produced by a rapid thermal annealing step of 20-40 s at temperatures of 800-1200 ° C.
  • Advantageous for the epitaxial growth is the high purity of the polysilanes used and the small thickness of the deposited layers of preferably 5-150 nm.
  • the diffusion step can be carried out under a protective gas atmosphere, in particular an argon or nitrogen atmosphere, or alternatively also in an oxygen-rich environment.
  • the diffusion step is carried out in the presence of oxygen. This results in an in situ oxidation of the elemental silicon on the
  • Substrate surface where an oxide grows up This can then be referred to as
  • Passivation layer can be used. This oxidation need not be limited to certain areas of the surface, but can generally occur in all areas in which elemental silicon comes into contact with the oxygen-containing atmosphere.
  • the oxide produced in this way typically has a layer thickness of approximately 10 nm. Alternatively, such an oxidation step may also take place separately after the diffusion step.
  • the step is usually carried out in a diffusion oven.
  • This furnace may be, for example, a continuous band furnace or a quartz tube furnace.
  • the methods described herein may further include a step of removing the oxidized areas of the coating of the surface of the silicon wafer. This can be done for example by means of a wet-chemical etching process. To remove silicon oxide, for example, a wet chemical etching method using
  • Hydrofluoric acid for example 2-10% HF in water.
  • Such an etching step may be carried out after the outdiffusion step, for example, over a period of 1 to 20 minutes. With such a step, both the oxides that are not in the oxidation of activated areas of the coatings are formed, as well as the possibly produced during the diffusion step oxides are removed.
  • composition in the form of a wet film in the according to 1. deposited form of complementary shape on the same side of the silicon wafer;
  • the method may additionally include the step of applying another composition to the
  • This composition may also be liquid, for example in the form of a
  • composition may contain either n- or p-type dopants, especially n-type dopants.
  • the composition is a precursor composition and defined as those above
  • first or second composition The application, activation, oxidation, etc. can also be done as described above for the first and second compositions.
  • the corresponding activation and optional oxidation steps can be carried out together with the activation / oxidation of the first and / or second oxidation steps
  • the method according to the invention is directed to the different doping of a silicon wafer for the production of bifacial solar cells, comprising the steps
  • the present invention also relates to the semiconductor substrates produced by the process according to the invention and to their use, in particular for the production of electronic or optoelectronic components, preferably solar cells.
  • the solar cells can be, for example, back-contact solar cells.
  • the semiconductor substrate produced according to the invention can be coated in a further step with a silicon nitride layer (flat, especially over the entire surface), after which a metal-containing composition for the production of metallic contacts, for example a silver paste, on certain areas of
  • Silicon nitride layer is applied and fired by heating to make contact with the underlying doped layer.
  • the metal-containing composition is applied in particular in the areas that are highly doped.
  • the present invention also covers solar cells and solar modules which contain the semiconductor substrates produced according to the invention.
  • the following examples illustrate the subject matter of the present invention without being self-limiting.
  • the emitter saturation current of the heavily doped region could be determined to be 800 fA / cm 2 . Furthermore, it has been shown that the amorphous silicon epitaxially crystallizes on the silicon wafer during outdiffusion. Furthermore, it could be shown that the amorphous silicon adapts to the crystal structure of the silicon wafer and epitaxially crystallizes on the silicon wafer during the outdiffusion, as can be seen in the diffraction image attached as Appendix 1.
  • Formulations consisting of 30% neopentasilane with 1.5% boron doping and 70% solvent toluene and cyclooctane on the front of an n-type silicon wafer of an impedance of 5 ohmcm deposited. Conversion at 500 ° C for 60 s into a 50 nm thick amorphous silicon layer. Subsequently, by spin-coating deposition of a phosphorus-doped formulations consisting of 30% neopentasilane with 1.5% phosphorus doping and 70% solvent toluene and cyclooctane on the back of the n- Type wafers.
  • Neopentasilane with 1 - 10% boron doping and 70% solvent toluene and cyclooctane The fingers typically have widths of 200 ⁇ - 1000 ⁇ .; The points have a diameter of 10 ⁇ - 400 ⁇ .
  • b Printing a liquid, n-type dopant containing, Si-based composition in the form of a wet film in to 1 according to. Deposited structure of complementary shape on the same side of the silicon wafer. Ink also normally contains 30% neopentasilane with 1 - 10% phosphorus doping and 70% solvent toluene and cyclooctane. The fingers typically have widths of 200 ⁇ - 1000 ⁇ .;
  • Conversion takes place at temperatures of 400 - 600 ° C. Duration 1 s - 2 minutes. Preferably 60 s at 500 ° C. Oxidation in an oxygen-containing atmosphere at a temperature between room temperature and 300 ° C. Duration: Depending on temperature 30 s - 30 min.
  • the layer thickness of the amorphous silicon is 10-100 nm.

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Abstract

L'invention concerne un procédé en phase liquide destiné au dopage d'un substrat à semi-conducteur. L'invention est caractérisée en ce qu'une première composition contenant au moins un premier dopant est appliquée sur une ou plusieurs zones de la surface du substrat à semi-conducteur, afin de produire une ou plusieurs zones de la surface du substrat à semi-conducteur revêtues de la première composition ; une deuxième composition contenant au moins un deuxième dopant est appliquée sur une ou plusieurs zones de la surface du substrat à semi-conducteur, afin de produire une ou plusieurs zones de la surface du substrat à semi-conducteur revêtues de la deuxième composition. L'une des zones ou les différentes zones qui sont revêtues de la première composition et l'une des zones ou les différentes zones qui sont revêtues de la deuxième composition sont différentes et ne se chevauchent sensiblement pas, et le premier dopant est un dopant du type n et le deuxième dopant est un dopant du type p ou inversement. Les zones de la surface du substrat à semi-conducteur revêtues de la première composition et de la deuxième composition sont activées respectivement entièrement ou partiellement. Eventuellement, les zones non activées de la surface du substrat à semi-conducteur et revêtues de la première composition et de la deuxième composition sont respectivement oxydées. Le substrat à semi-conducteur est chauffé à une température à laquelle les dopants se diffusent du revêtement dans le substrat à semi-conducteur. L'invention concerne en outre les semi-conducteurs pouvant être obtenus selon le procédé et leur utilisation, en particulier pour la production de cellules solaires.
EP15715773.6A 2014-04-29 2015-04-17 Procédé de production de semi-conducteurs à dopage différent Withdrawn EP3138119A1 (fr)

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DE102014208054.1A DE102014208054A1 (de) 2014-04-29 2014-04-29 Verfahren zur Erzeugung unterschiedlich dotierter Halbleiter
PCT/EP2015/058371 WO2015165755A1 (fr) 2014-04-29 2015-04-17 Procédé de production de semi-conducteurs à dopage différent

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JP6839939B2 (ja) * 2016-07-26 2021-03-10 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法
WO2020050829A1 (fr) * 2018-09-05 2020-03-12 Bae Systems Information And Electronic Systems Integration Inc. Carbone dérivé de carbure pour des milieux de micro-extraction en phase solide
US11404270B2 (en) 2018-11-30 2022-08-02 Texas Instruments Incorporated Microelectronic device substrate formed by additive process
US10861715B2 (en) 2018-12-28 2020-12-08 Texas Instruments Incorporated 3D printed semiconductor package
US10910465B2 (en) 2018-12-28 2021-02-02 Texas Instruments Incorporated 3D printed semiconductor package
US12105071B2 (en) 2019-12-18 2024-10-01 Bae Systems Information And Electronic Systems Integration Inc. Multi-element, ultra-low SWaP chemical pre-concentrator
TW202426689A (zh) * 2021-12-23 2024-07-01 法商液態空氣喬治斯克勞帝方法研究開發股份有限公司 V族元素的新型無機矽基和聚矽基衍生物及其合成方法和使用其沈積之方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008060874A1 (fr) * 2006-11-10 2008-05-22 Evergreen Solar, Inc. Substrat présentant un dopage sur les deux faces et procédé de production du substrat
KR20090029494A (ko) 2007-09-18 2009-03-23 엘지전자 주식회사 비정질 실리콘 및 나노 결정질 실리콘의 복합 박막을이용한 태양전지 및 그 제조방법
CN102077329A (zh) * 2008-06-17 2011-05-25 英诺瓦莱特公司 氢钝化的硅和锗表面的选择性活化
US7846762B2 (en) 2008-09-22 2010-12-07 Applied Materials, Inc. Integrated emitter formation and passivation
DE102010002405A1 (de) 2010-02-26 2011-09-01 Evonik Degussa Gmbh Verfahren zur Oligomerisierung von Hydridosilanen, die mit dem Verfahren herstellbaren Oligomerisate und ihre Verwendung
EP2556539A4 (fr) 2010-04-06 2014-08-06 Kovio Inc Structures épitaxiales, leurs procédés de formation et dispositifs les comprenant
US8669169B2 (en) 2010-09-01 2014-03-11 Piquant Research Llc Diffusion sources from liquid precursors
DE102010040231A1 (de) * 2010-09-03 2012-03-08 Evonik Degussa Gmbh p-Dotierte Siliciumschichten
DE102010041842A1 (de) * 2010-10-01 2012-04-05 Evonik Degussa Gmbh Verfahren zur Herstellung höherer Hydridosilanverbindungen
JP5666267B2 (ja) 2010-11-25 2015-02-12 東京応化工業株式会社 塗布型拡散剤組成物
WO2012077797A1 (fr) * 2010-12-10 2012-06-14 帝人株式会社 Stratifié à semi-conducteur, dispositif à semi-conducteur, procédé de production de stratifié à semi-conducteur, et procédé de fabrication de dispositif à semi-conducteur
DE102011075232B4 (de) * 2011-05-04 2015-02-19 Evonik Degussa Gmbh Verfahren zum Herstellen von n-dotierten Silizium-haltigen Schichten und entsprechend hergestellte Schichten
TWI569461B (zh) 2012-07-19 2017-02-01 日立化成股份有限公司 太陽電池元件及其製造方法及太陽電池模組
TWI501292B (zh) 2012-09-26 2015-09-21 Ind Tech Res Inst 形成圖案化摻雜區的方法
CN103811591B (zh) * 2014-02-27 2016-10-05 友达光电股份有限公司 背接触式太阳能电池的制作方法

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CN106463366A (zh) 2017-02-22
WO2015165755A1 (fr) 2015-11-05
JP2017519353A (ja) 2017-07-13
TW201606858A (zh) 2016-02-16
KR20160143866A (ko) 2016-12-14
US20170054050A1 (en) 2017-02-23
US9887313B2 (en) 2018-02-06

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