EP3129833B1 - Apparatus for cleaning an object - Google Patents

Apparatus for cleaning an object Download PDF

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Publication number
EP3129833B1
EP3129833B1 EP15709638.9A EP15709638A EP3129833B1 EP 3129833 B1 EP3129833 B1 EP 3129833B1 EP 15709638 A EP15709638 A EP 15709638A EP 3129833 B1 EP3129833 B1 EP 3129833B1
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EP
European Patent Office
Prior art keywords
substrate
electrode
voltage
support
lithographic tool
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Active
Application number
EP15709638.9A
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German (de)
English (en)
French (fr)
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EP3129833A1 (en
Inventor
Ronald Van Der Wilk
Ger-Wim Jan Goorhuis
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ASML Netherlands BV
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ASML Netherlands BV
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Publication of EP3129833A1 publication Critical patent/EP3129833A1/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/70908—Hygiene, e.g. preventing apparatus pollution, mitigating effect of pollution or removing pollutants from apparatus
    • G03F7/70925—Cleaning, i.e. actively freeing apparatus from pollutants, e.g. using plasma cleaning
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
    • G03F7/70708—Chucks, e.g. chucking or un-chucking operations or structural details being electrostatic; Electrostatically deformable vacuum chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks

Definitions

  • the present invention relates to a lithographic tool comprising an apparatus for cleaning an object, for example an object which is to be held by an electrostatic clamp, and to a method for cleaning such an object in a lithographic tool.
  • a lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate.
  • a lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs).
  • a lithographic apparatus may for example project a pattern from a patterning device (e.g. a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate.
  • a patterning device e.g. a mask
  • a layer of radiation-sensitive material resist
  • the wavelength of radiation used by a lithographic apparatus to project a pattern onto a substrate determines the minimum size of features which can be formed on that substrate.
  • a lithographic apparatus which uses EUV radiation being electromagnetic radiation having a wavelength within the range 4-20 nm, may be used to form smaller features on a substrate than a conventional lithographic apparatus (which may for example use electromagnetic radiation with a wavelength of 193 nm).
  • Electrostatic clamps may be used in lithographic apparatuses operating at certain wavelengths, e.g. EUV, since at these wavelengths, certain regions of the lithographic apparatus operate under vacuum conditions.
  • An electrostatic clamp may be provided to electrostatically clamp (i.e. hold) an object, such as a mask or a substrate (wafer) to an object support, such as a mask table or a wafer table, respectively.
  • the voltage which is applied to an electrostatic clamp may be considerable.
  • the voltage may be of the order of kilovolts.
  • An insulating barrier is conventionally located over an electrode of an electrostatic clamp, the insulating barrier acting to insulate an object such as a substrate from the voltage applied to the electrode.
  • US Patent 5,938,854 discloses an apparatus for cleaning a surface of a workpiece with a glow discharge plasma.
  • the apparatus comprises a pair of electrodes, one of which is the workpiece. Insulating supports are used to space the workpiece from the counter electrode. At least one of the electrodes may be insulated to prevent arcing.
  • the workpiece and the counter electrode are each respectively connected to the opposite phases of a radio frequency (RF) power source in order to allow a steady state, quasi-neutral uniform glow discharge plasma to form above the workpiece, between the electrodes.
  • RF radio frequency
  • EP 1 329 773 A2 discloses a cleaning device for cleaning a component of a lithographic apparatus, the cleaning device comprising a contaminant liberating means using electromagnetic fields to liberate contaminants from the surface of the component to be cleaned.
  • JP H11 57632 discloses details of a scrubber.
  • a lithographic tool comprising an apparatus for cleaning an object, the apparatus comprising: an object support for supporting the object; a low pressure chamber for exposing a first surface of the object to a low pressure when the object is arranged on the object support, an electrode arranged adjacent to and separated from the first surface of the object when the object is arranged on the object support, the electrode being in electrical communication with a surface of the object support which is adjacent the first surface of the object; and a power supply arranged to apply a voltage between the electrode and the object; thereby generating a discharge between the object and the electrode, wherein the electrode is provided with a resistive layer on the surface of the object support which is adjacent the first surface of the object.
  • a discharge e.g. an electric discharge
  • the generation of a discharge causes small particles or scratches on the surface of the object to be modified or removed such that they do not act as electron emitters when the object is subsequently clamped by an electrostatic clamp.
  • This cleaning of the surface of the object, and resulting reduction in electron emission slows down any charge accumulation on an electrostatic clamp.
  • This reduction in the rate of charge accumulation can increase the time between maintenance operations on the clamp and improve clamping performance (e.g. clamping force uniformity).
  • the electrode being in electrical communication with the surface of the object support allows any electrons emitted from the surface of the object and incident upon the surface of the object support to be carried away from the surface of the object support, rather than becoming trapped, as they would if the surface was an insulating surface (e.g. as is the case with a conventional electrostatic clamp).
  • the object support may be arranged to support the object within the chamber.
  • a resistive layer limits the instantaneous current which can flow between the object and the electrode to a level which is not damaging to the object, while still ensuring that electrons can be carried away from the surface of the object support.
  • the resistive layer may have a resistance of greater than around 10 5 ⁇ .
  • the resistive layer may have a resistance of less than around 10 12 ⁇ .
  • the resistive layer may have a resistivity of greater than around 10 6 ⁇ m.
  • the resistive layer may have a resistivity of less than around 10 14 ⁇ m.
  • the magnitude of the voltage may be greater than about 200 V.
  • the magnitude of the voltage may be less than about 1000 V.
  • the separation between the object support and the first surface of the object when the object is arranged on the object support may be greater than about 5 mm.
  • the separation between the object support and the first surface of the object when the object is arranged on the object support may be less than about 20 mm.
  • the apparatus may further comprise a second electrode, wherein a power supply is arranged to apply a first voltage between the first electrode and the object and a second voltage between the second electrode and the object.
  • the second voltage may be of opposite sign to the first voltage.
  • the second voltage may be of substantially equal magnitude to the first voltage.
  • the low pressure may be less than about 100 mbar.
  • the low pressure may be greater than about 1 mbar.
  • the low pressure chamber may be a load lock of the lithographic tool.
  • a method of cleaning an object in a lithographic tool comprising: providing the object to be cleaned; supporting the object on an object support; exposing a first surface of the object to be cleaned to a low pressure; providing an electrode adjacent to and separated from the first surface of the object; applying a voltage between the electrode and the object so as to generate a discharge between the object and the electrode; and providing a current path between the electrode and the first surface of the object.
  • FIG. 1 shows a lithographic system including an apparatus for cleaning an object according to one embodiment of the invention.
  • the lithographic system comprises a radiation source SO and a lithographic apparatus LA.
  • the radiation source SO is configured to generate an extreme ultraviolet (EUV) radiation beam B.
  • the lithographic apparatus LA comprises an illumination system IL, a support structure MT configured to support a patterning device MA (e.g. a mask), a projection system PS and a substrate table WT configured to support a substrate W.
  • the illumination system IL is configured to condition the radiation beam B before it is incident upon the patterning device MA.
  • the projection system is configured to project the radiation beam B (now patterned by the mask MA) onto the substrate W.
  • the substrate W may include previously formed patterns. Where this is the case, the lithographic apparatus aligns the patterned radiation beam B with a pattern previously formed on the substrate W.
  • the radiation source SO, illumination system IL, and projection system PS may all be constructed and arranged such that they can be isolated from the external environment.
  • a gas at a pressure below atmospheric pressure e.g. hydrogen
  • a vacuum may be provided in illumination system IL and/or the projection system PS.
  • a small amount of gas (e.g. hydrogen) at a pressure well below atmospheric pressure may be provided in the illumination system IL and/or the projection system PS.
  • the radiation source SO shown in Figure 1 is of a type which may be referred to as a laser produced plasma (LPP) source).
  • a laser 1 which may for example be a CO 2 laser, is arranged to deposit energy via a laser beam 2 into a fuel, such as tin (Sn) which is provided from a fuel emitter 3.
  • tin is referred to in the following description, any suitable fuel may be used.
  • the fuel may for example be in liquid form, and may for example be a metal or alloy.
  • the fuel emitter 3 may comprise a nozzle configured to direct tin, e.g. in the form of droplets, along a trajectory towards a plasma formation region 4.
  • the laser beam 2 is incident upon the tin at the plasma formation region 4.
  • the deposition of laser energy into the tin creates a plasma 7 at the plasma formation region 4.
  • Radiation including EUV radiation, is emitted from the plasma 7 during de-excitation and recombination of ions of the plasma.
  • the EUV radiation is collected and focused by a near normal incidence radiation collector 5 (sometimes referred to more generally as a normal incidence radiation collector).
  • the collector 5 may have a multilayer structure which is arranged to reflect EUV radiation (e.g. EUV radiation having a desired wavelength such as 13.5 nm).
  • EUV radiation e.g. EUV radiation having a desired wavelength such as 13.5 nm.
  • the collector 5 may have an elliptical configuration, having two ellipse focal points. A first focal point may be at the plasma formation region 4, and a second focal point may be at an intermediate focus 6, as discussed below.
  • the laser 1 may be separated from the radiation source SO. Where this is the case, the laser beam 2 may be passed from the laser 1 to the radiation source SO with the aid of a beam delivery system (not shown) comprising, for example, suitable directing mirrors and/or a beam expander, and/or other optics.
  • a beam delivery system (not shown) comprising, for example, suitable directing mirrors and/or a beam expander, and/or other optics.
  • the laser 1 and the radiation source SO may together be considered to be a radiation system.
  • Radiation that is reflected by the collector 5 forms a radiation beam B.
  • the radiation beam B is focused at point 6 to form an image of the plasma formation region 4, which acts as a virtual radiation source for the illumination system IL.
  • the point 6 at which the radiation beam B is focused may be referred to as the intermediate focus.
  • the radiation source SO is arranged such that the intermediate focus 6 is located at or near to an opening 8 in an enclosing structure 9 of the radiation source.
  • the radiation beam B passes from the radiation source SO into the illumination system IL, which is configured to condition the radiation beam.
  • the illumination system IL may include a facetted field mirror device 10 and a facetted pupil mirror device 11.
  • the faceted field mirror device 10 and faceted pupil mirror device 11 together provide the radiation beam B with a desired cross-sectional shape and a desired angular distribution.
  • the radiation beam B passes from the illumination system IL and is incident upon the patterning device MA held by the support structure MT.
  • the patterning device MA reflects and patterns the radiation beam B.
  • the illumination system IL may include other mirrors or devices in addition to or instead of the faceted field mirror device 10 and faceted pupil mirror device 11.
  • the projection system PS comprises a plurality of mirrors which are configured to project the radiation beam B onto a substrate W held by the substrate table WT.
  • the projection system PS may apply a reduction factor to the radiation beam, forming an image with features that are smaller than corresponding features on the patterning device MA. A reduction factor of 4 may for example be applied.
  • the projection system PS has two mirrors in Figure 1 , the projection system may include any number of mirrors (e.g. six mirrors).
  • the substrate W is loaded into the lithographic apparatus LA via a load lock 15.
  • the load lock 15 is an enclosure into which the substrate W is loaded from an environment at atmospheric pressure in order to pass to the lower pressure environment within the lithographic apparatus LA.
  • the substrate W is placed within the load lock 15 and the load lock 15 is sealed and pumped from atmospheric pressure to a vacuum pressure which is equal to the pressure within the lithographic apparatus LA.
  • the substrate W is then transferred to the substrate table WT.
  • the load lock 15 includes a substrate support 16 upon which the substrate is supported during pressure equalisation.
  • Figure 2 shows the part of the substrate table WT in more detail.
  • the substrate W is supported and held on the substrate table by an electrostatic clamp 17.
  • the clamp 17 comprises a dielectric portion 18 formed from a dielectric material, and an electrode 19.
  • a plurality of burls 20 are located on an upper surface of the dielectric portion 18.
  • the burls 20 may be formed from a dielectric material. Upper surfaces of the burls 20 determine a plane 21 at which a lower surface of the substrate W is held.
  • the electrode 19 is provided on an opposing surface of the dielectric portion 18 to the burls 20.
  • the electrode 19 is configured to be held at a voltage to generate an electrostatic clamping force between the clamp 17 and the substrate W.
  • the voltage may be considerable.
  • the voltage may be of the order of kilovolts.
  • the substrate W is held in plane 21 by the electrostatic clamping force when the voltage is applied to the electrode 19.
  • the applied voltage and more particularly the resulting electrostatic-field which is established between the clamp 17 and the substrate W, may cause a localised discharge across the gap between the substrate W and the clamp 17.
  • This discharge may take the form of electrons being emitted from the lower surface of the substrate W, or an upper surface of the clamp. Any such discharge may lead to an instantaneous reduction in the local clamping force.
  • any such emitted electrons are driven by the electrostatic-field towards the electrode 19 of the electrostatic clamp 17.
  • the electrons are prevented from reaching the electrode 19 by the dielectric portion 18 which is provided over the electrode 19.
  • the electrons instead become trapped at the surface of the dielectric portion 18.
  • the insulating nature of the dielectric portion 18 prevents the electrons from flowing away. Any such trapped electrons therefore remain on the surface of the dielectric portion 18.
  • Trapped electrons may remain on the surface of the dielectric portion 18 for a significant time period, and will not be removed by normal clamp operations. Each time a wafer is clamped the electrode voltage is removed and re-applied. However, this does not cause any trapped electrons to be removed. Therefore the trapped electrons may remain for many clamping cycles. For example, a trapped electron may remain on the surface of a clamp for 1000s of clamping cycles.
  • any such trapped electrons will be localised to the area of the dielectric surface in which the electrons are trapped. This effect may be a reduction in the clamping force experienced by the substrate in that area due to the trapped charge screening the effect of the voltage applied to the electrode 18 from the substrate W. Alternatively, any such trapped electrons may cause a local increase in the clamping force experienced by the substrate in that area. It will be appreciated that the polarity of the clamping voltage may be reversed between clamping cycles, leading to trapped charge either reinforcing or degrading the effect of the clamping voltage, depending on the polarity of the applied clamping voltage. The location of any trapped charge corresponds to the location from which any electron was emitted or accepted, which may be randomly distributed across the surface of the substrate. During a single clamping operation a clamp may thus gradually accumulate a significant charge in a small area, or a plurality of small areas, which correspond(s) to the location or locations of electron emitters on the surface of the substrate.
  • a clamp is used to clamp a large number of substrates one after another.
  • a clamp may thus gradually accumulate a large number of trapped electrons, in a large number of small areas, and a potentially significant negative charge at its surface, each clamping operation potentially resulting in electron emission from the clamped substrate.
  • the locations of the small areas of accumulated charge would be randomly distributed about the surface of the clamp, each substrate potentially emitting electrons from random locations on their surface.
  • the clamping of some substrates may not result in any electron emission, while the clamping of other substrates may result in a significant amount of electron emission.
  • any such trapped charge could cause difficulties in substrate handling.
  • trapped charge could cause a non-uniform clamping effect. Any non-uniform clamping could cause non-uniform stress within a substrate, and result in distortions to a substrate. Further, before a substrate is clamped, as it is moved into position above a clamp, any trapped charge could cause local sticking of the substrate to the clamp, preventing the substrate from moving freely to the intended position, and again causing local stress and deformation within the substrate. Similarly, when a clamping voltage is removed, trapped charge may cause a substrate to continue to stick to the clamp.
  • Local stress and deformation within a substrate can lead to distortion in any pattern applied to the substrate, and subsequent alignment errors. For example, when a substrate which already has a pattern is clamped, and a second pattern is subsequently applied to the substrate, any distortion of the substrate during clamping may cause the second pattern to not overlay accurately on the first pattern.
  • the likelihood of electron emission occurring from the substrate W is strongly dependent on the nature and condition of the surface of the substrate W.
  • small particles or defects (e.g. scratches) on the lower surface of the substrate W may act as electron emitters, leading to local discharges across the vacuum gap.
  • Electron emission can occur from particles of any material (e.g. metal, silicon, fibre), and is influenced more by surface geometry than it is by the material of the surface or particle.
  • the probability of field electron emission occurring is significantly reduced by a substrate having a smooth and flat surface.
  • a surface has sharp features, for example small particles, then the electric field is enhanced at those sharp features.
  • the electric field will also be enhanced by a factor of 10. Any such features are likely to be randomly distributed across the surface of a substrate, and are thus likely to appear in different locations on each substrate.
  • the conditions experienced during clamping may involve, for example, an electric field strength of around 100 V/ ⁇ m across a clamping separation of around 10 ⁇ m). Further, the field enhancement factor caused by sharp features could, for example, be 20. This combination of conditions and field enhancement would generate an electric field strength of around 2000 V/ ⁇ m. Such an electric field strength is known to lead to field electron emission.
  • Figure 3 shows an apparatus which can be used for discharge cleaning the surface of a substrate W.
  • the load lock 15 and substrate support 16 of Figure 1 are shown in more detail.
  • the substrate support 16 is provided with a plurality of equally sized pins 22 which project from a surface of the substrate support 16.
  • the pins 22 are arranged in array, each pin having a tip which is configured to support substrate W.
  • the tips of each of the plurality of pins 22 together define a plane in which the lower surface of the substrate W is supported.
  • the lower surface of the substrate W is the same surface which is supported on the burls 20 when the substrate W is held on the substrate table WT (i.e. the surface which faces the electrostatic clamp 17, and from which electrons may be emitted during clamping). While a large number of pins 22 are shown, a smaller number may be used. For example, three pins may provide adequate support for a substrate.
  • the substrate support 16 further comprises first and second electrodes 23a, 23b arranged below the pins 22 on the side of the substrate support 16 which is facing the substrate W.
  • Each of the electrodes 23a, 23b extends across approximately half of the substrate support 16.
  • the plurality of pins 22 may extend from the surface of the substrate support 16 as shown in Figure 3 . Alternatively, pins may extend through holes in the electrodes.
  • the electrodes 23a, 23b are arranged adjacent to and separated from the plane in which the substrate W is supported.
  • the electrodes 23a, 23b are also arranged parallel to the plane in which the substrate W is supported. The height of the pins 22 determines the separation between the substrate W and the electrodes 23a, 23b.
  • the separation between the substrate W and the electrodes 23a, 23b may, for example, be greater than about 5 mm.
  • the separation between the substrate W and the electrodes 23a, 23b may, for example, be less than about 20 mm.
  • the pins 22 may be formed from a conductive material.
  • the pins may be stainless steel.
  • the first electrode 23a is connected to a first power supply 24a
  • the second electrode 23b is connected to a second power supply 24b.
  • the first and second power supplies 24a, 24b are configured to provide voltages relative to a common ground 25 which are substantially equal in magnitude but opposite in polarity (or sign) from one another.
  • the first power supply 24a may provide a voltage of +500 V to the first electrode 23a
  • the second power supply 24b may provide a voltage of -500 V to the second electrode 23b.
  • the substrate W may also be connected to the common ground 25, such that the electrodes 23a, 23b are held at voltages relative to the substrate W.
  • the pins 22 may provide a connection between the common ground 25 and the substrate W.
  • the substrate may be capacitively coupled to ground. In such an arrangement, any current flowing to or from the electrodes 23a, 23b, will flow via the other of the electrodes 23a, 23b, rather than directly to ground.
  • the electrodes 23a, 23b are each provided with a respective resistive layer 26a, 26b, which covers the upper surface of each of the electrodes 23a, 23b.
  • the upper surfaces of the electrodes 23a, 23b, while each covered with a respective resistive layer 26a, 26b, are still in electrical communication with the upper surface of the substrate support (i.e. the surface of the substrate support which faces the lower surface of the substrate W). This ensures that there is a current path from the upper surface of the substrate support 16 to the electrodes 23a, 23b.
  • any electrons which are emitted from the lower surface of the substrate W are allowed to flow to the electrodes 23a, 23b, rather than becoming trapped on the surface of the substrate support.
  • FIG 4 shows the substrate support 16 from above.
  • the substrate support 16 is circular, and is of a similar size to the substrate with which it is intended to be used.
  • the substrate W may, for example, be a circular wafer with a diameter of 300 mm.
  • the resistive layers 26a, 26b each cover approximately half of the substrate support 16. It will be appreciated that the electrodes 23a, 23b are located below the resistive layers 26a, 26b, and are thus not visible in Figure 4 .
  • the plurality of pins 22 are distributed across the surface of the substrate support 16.
  • the substrate support 16 may alternatively be larger than the substrate it is intended to support.
  • the load lock 15 allows the substrate W to pass from an environment at atmospheric pressure to the lower pressure environment within the projection system PS.
  • the load lock 15 is sealed and pumped from atmospheric pressure to a vacuum pressure which is equal to the pressure within the projection system PS.
  • the pressure within the load lock 15 may thus be readily controlled so as to be below atmospheric pressure.
  • the substrate W to be cleaned is positioned on the pins 22 within the load lock 15 and the pressure within the load lock is reduced to a pressure P LL which is below atmospheric pressure P atm .
  • the pressure P LL may, for example, be below 100 around mbar.
  • the pressure P LL may, for example, be above around 1 mbar.
  • the discharge may cause the particles (which are described above as electron emitters) to evaporate, or for sharp tips of particles to become more rounded. Similarly, the discharge may cause sharp edges of any surface scratches to become more rounded.
  • Any flow or current between the electrodes and the substrate is focused upon any features with high aspect ratios (e.g. sharp edges), for the same reasons which those features may emit electrons when clamped. That is, the field enhancement effect of any high aspect ratio surface features causes the particles or scratches to emit electrons, igniting the discharge.
  • This flow of current through particles or scratches on the surface of the substrate W also causes significant local heating due to the high current density. This local heating may, for example, cause the particle to evaporate, and be removed from the surface of the substrate W entirely.
  • the local heating may cause the emission characteristics of any particles or scratches to be modified such that they are less likely to emit electrons.
  • sharp edges of features which are responsible for field enhancement which causes electron emission may be partially rounded by the high current density flowing through those edges. This rounding may result in a reduced field enhancement effect, and reduced emission in during clamping. Electron emitters which are modified in this way may be considered to be neutralised.
  • the formation of a discharge causes ions to be generated between the electrodes 23a, 23b, and the substrate W. These ions may bombard the surface of the substrate W, and may further contribute to the cleaning effect described above.
  • the conditions required to remove or modify the electron emitters may vary depending upon the nature and number of the emitters. A number of properties cooperate to provide suitable conditions for discharge cleaning. For example, the voltage applied, the duration for which the voltage is applied, the pressure and the separation between the electrode and the substrate all cooperate to provide suitable conditions.
  • the voltage applied may be an AC or a DC voltage.
  • the voltage applied may be around ⁇ 500 V (i.e. +500 V and -500 V as described above).
  • the voltage applied may be up to around ⁇ 1 kV.
  • the voltage applied may be greater than around ⁇ 200 V.
  • the voltages may be applied in turn to each of the two electrodes 23a, 23b. That is, a positive voltage may be applied to the first electrode 23a, and a negative voltage may be applied to the second electrode 23b. The voltages may then be reversed, changing the direction of current flow. This would allow all parts of the substrate to act as an electron emitter during one of the directions of current flow.
  • a DC voltage may be applied in each direction for around 2 seconds.
  • a voltage may be applied for longer or shorter times depending on the number of electron emitters on a surface. It will be appreciated that the longer the duration for which the voltage is applied, the more electron emitters will be modified or removed.
  • the voltage applied to each of the electrodes 23a, 23b may simply be the same voltage in opposite phases. The direction of current flow will thus reverse in each AC cycle. One or two cycles may provide sufficient duration to remove electron emitters from the surface of the substrate. For example, where a 50 Hz supply is used, the AC voltage may be applied for as little as around 2-4 milliseconds.
  • the current density may be large where discharge does occur.
  • the current density may be around 10 A/mm 2 at a discharge location.
  • the area over which this current may flow may, for example, be around 1 ⁇ m 2 .
  • the current flow will thus be small (e.g. around 10 ⁇ A per location).
  • a substrate may, for example, have around 10000 such discharge locations (i.e. electron emitters) in each half.
  • a voltage is applied between the electrodes 23a, 23b and the substrate a total current of around 100 mA may flow to the substrate for each polarity of voltage applied (i.e.
  • 100 mA may flow from the first electrode 23a to a first half of the substrate when a first polarity of voltage is applied, and 100 mA may flow from the second electrode 23b to a second half of the substrate when a second polarity of voltage is applied).
  • the pressure in the load lock P LL during the formation of a discharge may be, for example, less than around 100 mbar.
  • the pressure P LL may be, for example, greater than around 1 mbar.
  • the gas present during the formation of a discharge may be any gas, for example air.
  • the electrodes 23a, 23b are described as being two separate electrodes. However, in embodiments of the invention, different numbers of electrodes may be used. For example, a single electrode may be used. Alternatively, a greater number of electrodes may be used. For example, four or more electrodes may be used.
  • a current path should be provided from the substrate to the power supply.
  • the substrate should thus be grounded where only a single electrode is used.
  • the substrate W may also be grounded (as shown in Figure 3 ).
  • the ground connection to the substrate W may be omitted.
  • the provision of the resistive layers 26a, 26b on the electrodes 23a, 23b limits the flow of current when the voltage is applied to the electrodes 23a, 23b.
  • a large flow of current may cause damage to the substrate.
  • an applied voltage between the electrode and the substrate may cause a large instantaneous current to flow. This may lead to large currents flowing within the substrate (e.g. from the discharge location to a connection to ground, or to another discharge location). Such currents flowing within the substrate may cause damage to circuits or semiconductor components which may already be defined on the substrate by earlier processing steps.
  • the provision of the resistive layers 26a, 26b on the electrodes 23a, 23b locally limits the flow of current when the voltage is applied to the electrodes 23a, 23b.
  • the high resistance of the resistive layers 26a, 26b will cause a local voltage drop at the surface of the resistive layer 26a, 26b in the region of the discharge, preventing significant current from flowing, and thus reducing possible damage to the substrate W.
  • the remainder of the surface of the resistive layer 26a, 26b will be maintained at the applied voltage, allowing further discharges to occur at the locations of other electron emitters on the surface of the substrate W.
  • the resistive layers 26a, 26b may be arranged such that the total resistance of each resistive layer 26a, 26b is greater than around 10 5 ⁇ , in order to provide adequate protection from high current flow.
  • the substrate support 16 may have a total area of around 0.1 m 2 .
  • Each electrode 23a, 23b (and hence each resistive layer 26a, 26b) would thus have an area of around 0.05 m 2 .
  • the resistive layers 26a, 26b may, for example, be around 1 mm in thickness. Such a resistive layer should therefore have a volume resistivity of the order of at least 10 6 ⁇ m in order to achieve a total resistance of around 10 5 ⁇ .
  • the resistive layers 26a, 26b may be arranged such that the total resistance of each resistive layer 26a, 26b is less than around 10 12 ⁇ in order to provide a current path from the surface of the substrate support 16 to the electrodes 23a, 23b. Such a resistive layer should therefore have a volume resistivity of less than around 10 14 ⁇ m in order to achieve a total resistance of around 10 12 ⁇ .
  • the resistive layers 26a, 26b may, for example, be formed from aluminium nitride.
  • the resistive layers 26a, 26b may be omitted.
  • the power supplies may be arranged so as to produce only a limited current output.
  • the power supplies may be arranged to have a large output impedance, which effectively limits the maximum output current to a safe level. It will be appreciated that a power supply having a large output impedance will cause the voltage applied to an entire electrode to be reduced in the event that a significant discharge occurs at a point on the electrode, reducing the likelihood of damage occurring to the substrate. Such a reduction in voltage may also reduce the likelihood that discharges will occur at other regions of the electrode.
  • the power supplies may be modulated so as to limit the energy output (e.g. PWM controlled), reducing the likelihood of damage by controlling the energy output.
  • PWM controlled e.g. PWM controlled
  • each switching of the applied voltage may cause an established discharge to be extinguished at a first location, and reignited at a second location.
  • the low pressure conditions present in a load lock 15 may provide suitable discharge formation conditions.
  • the load lock is thus an example of a low pressure chamber in which the substrate W can be cleaned.
  • cleaning the substrate W immediately prior to it being clamped within a lithographic apparatus maximises the effect of the cleaning (i.e. by minimising the risk of exposure to further contaminants prior to clamping).
  • the substrate cleaning apparatus may be located within another part of a lithographic apparatus or lithographic system.
  • the substrate cleaning apparatus may be located within a dedicated substrate cleaning chamber.
  • the substrate cleaning apparatus may be arranged as a separate tool which is used prior to loading into a load lock.
  • the invention may be configured without a chamber which encloses the substrate for cleaning.
  • a substrate may be arranged to be adjacent to an opening in a low pressure chamber, with a seal provided around the opening, the seal sealing against the surface of the substrate.
  • the surface of the substrate may be exposed to the low pressure within the chamber, and a discharge generated adjacent to the surface, without the entire substrate being enclosed within the low pressure chamber.
  • a substrate may not be able to withstand high differential pressures. Such a substrate should not therefore be exposed to high differential pressures.
  • support may be provided for a substrate so as to prevent deformation which may cause damage to the substrate.
  • the invention may be configured to clean a surface of a reticle or mask.
  • the substrate W is thus an example of an object which may be cleaned within an object cleaning apparatus according to an embodiment of the invention.
  • the substrate support 16 described above is an example of an object support which supports an object within an object cleaning apparatus.
  • the object support may be configured to support a reticle or mask, and may therefore be non-circular (e.g. square or rectangular).
  • the invention may form part of a mask inspection apparatus.
  • the mask inspection apparatus may use EUV radiation to illuminate a mask and use an imaging sensor to monitor radiation reflected from the mask. Images received by the imaging sensor are used to determine whether or not defects are present in the mask.
  • the mask inspection apparatus may include optics (e.g. mirrors) configured to receive EUV radiation from an EUV radiation source and form it into a radiation beam to be directed at a mask.
  • the mask inspection apparatus may further include optics (e.g. mirrors) configured to collect EUV radiation reflected from the mask and form an image of the mask at the imaging sensor.
  • the mask inspection apparatus may include a processor configured to analyse the image of the mask at the imaging sensor, and to determine from that analysis whether any defects are present on the mask.
  • the processor may further be configured to determine whether a detected mask defect will cause an unacceptable defect in images projected onto a substrate when the mask is used by a lithographic apparatus.
  • the invention may form part of a metrology apparatus.
  • the metrology apparatus may be used to measure alignment of a projected pattern formed in resist on a substrate relative to a pattern already present on the substrate. This measurement of relative alignment may be referred to as overlay.
  • the metrology apparatus may for example be located immediately adjacent to a lithographic apparatus and may be used to measure the overlay before the substrate (and the resist) has been processed.
  • Embodiments of the invention may form part of a mask inspection apparatus, a metrology apparatus, or any apparatus that measures or processes an object such as a wafer (or other substrate) or mask (or other patterning device). These apparatus may be generally referred to as lithographic tools. Such a lithographic tool may use vacuum conditions or ambient (non-vacuum) conditions.
  • EUV radiation may be considered to encompass electromagnetic radiation having a wavelength within the range of 4-20 nm, for example within the range of 13-14 nm. EUV radiation may have a wavelength of less than 10 nm, for example within the range of 4-10 nm such as 6.7 nm or 6.8 nm.
  • lithographic apparatus in the manufacture of ICs, it should be understood that the lithographic apparatus described herein may have other applications. Possible other applications include the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, flat-panel displays, liquid-crystal displays (LCDs), thin-film magnetic heads, etc.
  • imprint lithography a topography in a patterning device defines the pattern created on a substrate.
  • the topography of the patterning device may be pressed into a layer of resist supplied to the substrate whereupon the resist is cured by applying electromagnetic radiation, heat, pressure or a combination thereof.
  • the patterning device is moved out of the resist leaving a pattern in it after the resist is cured.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Health & Medical Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Atmospheric Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Environmental & Geological Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Cleaning In General (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
EP15709638.9A 2014-04-09 2015-03-02 Apparatus for cleaning an object Active EP3129833B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP14164043 2014-04-09
PCT/EP2015/054277 WO2015154917A1 (en) 2014-04-09 2015-03-02 Apparatus for cleaning an object

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EP3129833B1 true EP3129833B1 (en) 2018-05-02

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EP (1) EP3129833B1 (zh)
JP (1) JP6475260B2 (zh)
KR (1) KR102408173B1 (zh)
CN (1) CN106164776B (zh)
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WO (1) WO2015154917A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
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KR102617773B1 (ko) * 2017-06-01 2023-12-22 에이에스엠엘 네델란즈 비.브이. 입자 제거 장치 및 관련 시스템
NL2021410A (en) * 2017-08-28 2019-03-07 Asml Holding Nv Apparatus for and method cleaning a support inside a lithography apparatus
WO2019166318A1 (en) * 2018-03-02 2019-09-06 Asml Netherlands B.V. Method and apparatus for forming a patterned layer of material
CN111954852A (zh) * 2018-04-12 2020-11-17 Asml荷兰有限公司 包括静电夹具的装置和用于操作该装置的方法
CN112969970B (zh) * 2018-11-09 2024-10-11 Asml控股股份有限公司 用于清洁光刻设备内的支撑件的设备和方法
US20220308465A1 (en) * 2021-03-26 2022-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for removing contamination

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1157632A (ja) * 1997-08-28 1999-03-02 Dainippon Screen Mfg Co Ltd 基板処理装置
US5938854A (en) * 1993-05-28 1999-08-17 The University Of Tennessee Research Corporation Method and apparatus for cleaning surfaces with a glow discharge plasma at one atmosphere of pressure

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2383469A (en) * 1943-12-15 1945-08-28 Libbey Owens Ford Glass Co Method of cleaning and coating glass, plastics, and other surfaces
US3868271A (en) * 1973-06-13 1975-02-25 Ibm Method of cleaning a glass substrate by ionic bombardment in a wet active gas
BE1001027A3 (nl) 1987-10-21 1989-06-13 Bekaert Sa Nv Werkwijze en inrichting voor het reinigen van een langwerpig metalen substraat, zoals een draad, een band, een koord, enz., alsmede volgens die werkwijze gereinigde substraten en met dergelijke substraten versterkte voorwerpen uit polymeermateriaal.
US4883437A (en) 1988-06-29 1989-11-28 Rca Licensing Corp. Method for spot-knocking an electron gun mount assembly of a crt utilizing a magnetic field
US5393575A (en) 1992-03-03 1995-02-28 Esterlis; Moisei Method for carrying out surface processes
JP3162272B2 (ja) * 1995-08-22 2001-04-25 東京エレクトロン株式会社 プラズマ処理方法
US5948294A (en) 1996-08-30 1999-09-07 Mcdermott Technology, Inc. Device for cathodic cleaning of wire
US5779807A (en) 1996-10-29 1998-07-14 Applied Materials, Inc. Method and apparatus for removing particulates from semiconductor substrates in plasma processing chambers
US5880924A (en) * 1997-12-01 1999-03-09 Applied Materials, Inc. Electrostatic chuck capable of rapidly dechucking a substrate
JP3644246B2 (ja) * 1998-04-10 2005-04-27 三菱電機株式会社 Ｘ線露光方法
DE19907911C2 (de) 1999-02-24 2003-02-27 Mag Maschinen Und Appbau Ag Gr Vorrichtung und Verfahren zur Behandlung von elektrisch leitfähigem Endlosmaterial
JP3398936B2 (ja) * 1999-04-09 2003-04-21 日本エー・エス・エム株式会社 半導体処理装置
EP1329773A3 (en) * 2002-01-18 2006-08-30 ASML Netherlands B.V. Lithographic apparatus, apparatus cleaning method, and device manufacturing method
JP2003257949A (ja) * 2002-03-06 2003-09-12 Matsushita Electric Ind Co Ltd 液晶表示素子の製造方法
US7092231B2 (en) 2002-08-23 2006-08-15 Asml Netherlands B.V. Chuck, lithographic apparatus and device manufacturing method
JP2007115839A (ja) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及びプラズマ処理装置
US7894037B2 (en) * 2007-07-30 2011-02-22 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
CN101919041B (zh) * 2008-01-16 2013-03-27 索绍股份有限公司 衬底固持器，衬底支撑设备，衬底处理设备以及使用所述衬底处理设备的衬底处理方法
NL1036769A1 (nl) * 2008-04-23 2009-10-26 Asml Netherlands Bv Lithographic apparatus, device manufacturing method, cleaning system and method for cleaning a patterning device.
EP2145701A1 (fr) * 2008-07-16 2010-01-20 AGC Flat Glass Europe SA Procédé et installation pour la préparation de surface par décharge à barrière diélectrique
JP2010174325A (ja) * 2009-01-29 2010-08-12 Kyocera Corp 放電用電極体、放電用電極アセンブリおよび放電処理装置
US20130087287A1 (en) * 2011-10-10 2013-04-11 Korea Institute Of Machinery & Materials Plasma reactor for removal of contaminants
CN104272190A (zh) * 2012-02-03 2015-01-07 Asml荷兰有限公司 衬底保持器和光刻装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5938854A (en) * 1993-05-28 1999-08-17 The University Of Tennessee Research Corporation Method and apparatus for cleaning surfaces with a glow discharge plasma at one atmosphere of pressure
JPH1157632A (ja) * 1997-08-28 1999-03-02 Dainippon Screen Mfg Co Ltd 基板処理装置

Also Published As

Publication number Publication date
US10133196B2 (en) 2018-11-20
TWI659270B (zh) 2019-05-11
CN106164776B (zh) 2019-04-23
JP6475260B2 (ja) 2019-02-27
EP3129833A1 (en) 2017-02-15
KR102408173B1 (ko) 2022-06-13
JP2017518523A (ja) 2017-07-06
TW201541197A (zh) 2015-11-01
WO2015154917A1 (en) 2015-10-15
CN106164776A (zh) 2016-11-23
KR20160144438A (ko) 2016-12-16
US20170205717A1 (en) 2017-07-20

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