Classifications

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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
  • H01L21/4828—Etching
  • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/27—Manufacturing methods
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  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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  • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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  • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
  • H01L2224/061—Disposition
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  • H01L2224/06181—On opposite sides of the body
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
  • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Definitions

• the present invention relates to a method for producing a chip module having a carrier substrate and at least one arranged on the carrier substrate chip and a contact conductor arrangement for connecting Chipanschlus s vom with arranged on a contact side of the chip module connection scontakten, wherein the chip s vom provided with its with the Chipanschlus Front on the
• Carrier substrate is fixed and subsequently carried out the formation of the contact conductor arrangement by structuring a contact material layer of the carrier substrate.
• Chip modules which are often also termed "chip package” in technical terms, basically have a carrier substrate provided with a contact conductor arrangement and a chip which is received protected in a chip housing and which is contacted with the contact conductor arrangement via its chip contact surfaces to form a suitable arrangement for the outer contact of the chip module arrangement of connection contacts, wherein the connection contacts have a greater distance from each other than the chip pads and larger Have contact surfaces to facilitate the external contact of the chip module.
• an adaptation of terminal contact arrangements of further chip modules or boards can be carried out by means of the contact conductor arrangement, so that the chip module can be contacted with the further chip module or the board without further rewiring.
• the contact conductor arrangement can therefore also be regarded as an integrated "rewiring" of the chip module, which makes an external rewiring between chip modules to be contacted redundant
• the special layout or the special, the chip module individualizing distribution of the external connection scontakte is also often referred to as so-called " footprint ".
• Known methods for producing a chip module provide, for example, that s as a chip carrier sub strate of a dielectric material is used, which is provided with a contact conductor arrangement for forming the "internal rewiring", wherein after production of the contact conductor arrangement, the contacting of the chip on the chip carrier and then the formation of a chip housing the chip housing on the chip carrier takes place in that the chip is wrapped by a so-called “mold”, which in liq sigem
• the inventive method has the features of claim 1.
• the chip is fixed with its front side provided with chip pads on a contact material layer of a Suub strats.
• the formation of the contact conductor arrangement is carried out by structuring the contact material of the carrier substrate. This eliminates the need to provide chip carriers which are already provided with a contact conductor arrangement. Rather, the formation of the contact conductor arrangement with a chip module individualizing footprint can be carried out together with the production of the chip module.
• the arrangement of the chip on the carrier substrate takes place prior to the formation of the contact conductor arrangement.
• the formation of the contact conductor arrangement takes place in that from the
• Contact material formed carrier substrate is structured.
• the fixation of the chip on the carrier substrate is effected by arranging the chip with its front side provided with chip connection surfaces on an adhesive coating of the contact material layer of the carrier substrate. Due to the adhesive coating of the carrier substrate, it is possible, for example, to dispense with providing the position of the chip on the carrier substrate defining recesses in the carrier substrate or the like.
• the carrier substrate can be particularly easily configured with flat surfaces. It when the Suub strat is formed from a contact material film, which allows a particularly thin configuration of the carrier substrate formed from the contact material is particularly advantageous.
• the contact material film can be provided to form the carrier substrate as a continuous material, whereby an automated inline production of the chip module is facilitated in large quantities, since the contact material film at the same time as an endless conveyor for a clocked Vormony in Stanfordsprozes s of the chip module can be used.
• a contact material foil is used for the carrier substrate, which is already provided with an adhesive coating, so that it is not necessary to apply an adhesive coating in a separate process step preceding the loading of the carrier substrate with the chip.
• connection contacts that make an electrically conductive connection between the contact conductor arrangement and the Chipanschlus s vom, done in a particularly simple manner.
• the connection contacts can be formed by using a solder material as the contact material which is applied in the contact recesses.
• solder material can be effected, for example, by means of a method in which molten solder material deposits are thrown onto the chip terminals accessible by means of the contact recesses.
• contact material Another possibility to introduce contact material into the contact recesses, is to introduce the contact material by a deposition process in the contact recesses, in principle, both a galvanic deposition and an electroless deposition process is eligible, in which the contact material preferably by autocatalytic deposition, so for example by deposition of Nickel and / or gold.
• autocatalytic deposition so for example by deposition of Nickel and / or gold.
• contact material can be made prior to formation of the contact conductor arrangement contacting the Chipanschlus s vom with the Kunststoffmateriallage independent of the structuring of the contact material layer.
• the provided with contact increases Chipanschlus s vom brought to rest against the contact material layer, and subsequently the connection of the Chipanschlus s vom with the contact material position by melting the contact increases.
• the fixation of the chip on the carrier substrate can also take place simultaneously with the formation of the connection contact to the contact material layer.
• a shell material is applied to the carrier substrate prior to formation of the contact conductor arrangement for forming an envelope material layer which houses the chip.
• the Hüllmateriallage forms a support substrate from stiff support means, so that even in the case of the formation of the carrier substrate as a film material processing of the carrier substrate for structuring the contact material layer can be done without the flexibility of the carrier substrate would make the processing difficult.
• the cladding material layer is provided from its upper side with at least one contact recess which exposes the contact material of the carrier substrate to form a contact surface on the contact material layer of the carrier substrate, through-contacting of the cladding material layer with direct contact with the contact conductor arrangement of the carrier substrate getting produced.
• the contact recess can be filled with contact material to form a through-contact formed as a contact column, or a contact material introduced into the contact recess by a deposition process can be used to form a contact column.
• a particularly thin design of the chip module is possible if the Hüllmateriallage is machined material from its upper side to expose a chip back material, such that the chip back and the contact column are arranged flush in a formed by the processing Hüllmaterialober Design.
• a bit metallization can preferably be carried out. be introduced, which is subsequently provided with a contact material layer to electrically connect the back of the chip with the arranged on the chip front side contact conductor arrangement, so that s the back of the chip can be used as Anschlußs squares for an electric field.
• the contact conductor material layer can be structured to form a chip backside contact conductor arrangement.
• the base metalization can also be applied to the surface of the Hüllmateriallage before forming the contact recesses in Hüllmateriallage, and subsequently applied a contact material on the base metallization and to form a Chip backside contact conductor arrangement are structured.
• the cladding material layer can be provided with at least one contact recess from its upper side which exposes the contact material to form a contact surface on the contact material layer of the carrier substrate, and subsequently the contact recess can Formation of the via with a contact column of contact material are filled.
• the chip back side is first exposed by exposure of the enveloping material with laser radiation and subsequently a deposition of a Contact material is applied to the back of the chip to make contact between the back of the chip and the back of the chip contact layer.
• FIGS. 14 to 21 show the production of a chip module according to a variant of the method in steps which follow one another in different steps;
• FIGS. 22 and 23 show the formation of a bonding contact between chips and a carrier substrate via contact increases
• FIG. 24 shows the laminate structure of a chip module before structuring the contact material layer
• FIG. 25 shows the structuring of the contact material layer for forming the chip module
• FIG. 26 shows the laminate structure of a chip module before structuring the contact material layer
• FIG. 27 shows the structuring of the contact material layer for forming the chip module.
• Fig. 1 shows as a starting point for carrying out the method the
• the carrier substrate 30 is provided with an adhesive coating 32, which may be formed, for example, as a thermally activatable epoxy resin.
• the coating is formed as an adhesive layer which is also independent of an activation and which can be provided with a peel-off paper or the like for handling or providing the carrier film so that the carrier film can also be provided, for example
• an arrangement of at least one, in the present case a plurality of chip s 33, the s vom 34 are arranged with their downwardly directed Chipanschlus on the carrier substrate 30, wherein by the adhesive coating 32 one of the chips 33 positioning on the carrier substrate 30 positioning takes place.
• the envelope material layer 35 is brought into abutment against the carrier substrate 30 under simultaneous action of pressure and temperature, whereby the material of the envelope material layer 35 is displaced by the chips 33, with the result that s, as in FIG. 3 shown, after completion of the lamination step, the chips 33 are embedded embedded in the Hüllmateriallage 35, so in particular the chip back sides 36 of the chips 33 through the Material of Hüllmateriallage 35 are covered.
• the material of Hüllmateriallage 35 is chosen in its composition so that the thermal expansion coefficient of the shell material is as close as possible to the thermal expansion coefficient of the contact material 3 1 of the support substrate 30.
• this can be achieved by sufficiently adding a silicon oxide to the epoxy material of the coating material as a filler, for example by means of which a thermal expansion coefficient in the range of 7 to 8 K -1 can be achieved, which corresponds to the thermal expansion coefficient of copper,
• an essential component of the contact material is 3 1 and has a thermal expansion coefficient of about 16 K "1 , is not so far apart that s after curing of Hüllmateriallage 35 delamination between the Hüllmateriallage 35 and the support substrate 30 would have to be counted ste , Rather, the remaining after curing flexibility of the
• Envelope material 35 sufficient to compensate for the difference in the expansion coefficient can.
• contact recesses 38 are formed in the envelope material layer 35 from an upper side 37 of the envelope material layer 35, exposing the contact material 3 1 of the carrier substrate 30 to form an inner contact surface 39.
• the formation of the contact recesses 38 can be effected by applying the upper side 37 of the Hüllmateriallage 35 with laser radiation.
• Contact recesses 38 with a contact material 40, which are deposited, for example, autocatalytically on the contact surfaces 39 can, preferably before deposition of the contact material 40 on the contact surfaces 39, a seeding of the contact surfaces 39 can be done with zincate or palladium example, to the adhesion between the deposited on the contact surface 39 contact material 40 and the contact surface 39 to verbes fibers.
• the contact material 40 is preferably a matching with the contact material 3 1, at least predominantly copper having material composition selected.
• a subsequent method step preferably after the preceding formation of a base metallization 44 shown in Fig. 7 on the Hüllmaterialober Structure 41, the formation of a shown in Fig. 8 contact material layer 43 on the Hüllmateriallage 35, preferably as the contact material of the contact material layer 43 copper or copper Alloy is selected.
• the formation of the intermediate metallization 44 can be effected, for example, by depositing the material of the base metallization 44 onto the shell material surface 41, for example by sputtering a titanium / copper alloy.
• the contact material layer 43 can subsequently be applied to the base metalization 44 by deposition, wherein the deposition can be effected either galvanically or also autocatalytically.
• a lithographic structuring is preferably carried out. tion of the applied on the Hüllmateriallage 35 contact material layer 43, such that s the chip backside contact conductor assembly 5 1 in the present case has two contact conductors 52, 53, which in each case connect a chip rear side 36 with a contact column 42.
• a contact conductor arrangement 45 produced by structuring the carrier substrate 30 and shown in FIG. 12, as shown in the sequence of FIGS. 10 and 11, processing of the carrier substrate 30 is first performed in a first lithographic method, so that on the one hand Contact conductor 46, 47, 48 and the other contact recesses 49 are formed in the carrier substrate 30.
• connection contacts 68 which connect the contact conductors 46, 47, 48 to the chip connection surfaces 34 is then preferably effected by autocatalytic deposition of a contact material 50, which preferably consists of copper or a copper alloy and which furthermore preferably has been previously treated with zincate or palladium germinated chip pads 34 is de-energized.
• the contact conductor arrangement 45 shown in FIG. 12 is completed and thus the formation of a carrier substrate 30 based on FIG produced chip module 72 in a second lithographic process step in which from the contact conductors 46 and 48 terminal contacts 69, 70 and 7 1 are formed.
• the connection contacts 69 allow via the contact posts 42 and the contact conductors 52 and 53, a contacting of the chip backs 36 and the connection scontakte 70, 7 1 a contacting the Chipanschlus s vom 34th
• both a terminal contact side 56 and a back side 57 of the chip module 72 with a preferably formed from an epoxy resin Pas siv réelle 58, 59 is provided, wherein in the Pas siv réelle 58 of the outer contact side 56th Contact recesses 60 are formed, the contact surfaces 61 exposed so that s on the contact surfaces 61 Lotbumps 62 can be applied, which allow contact points for any external contact of the chip module 72.
• FIGS. 14 to 21 a variant of the method is shown in which, starting from the method illustrated in FIG. 3, that is to say subsequently the positioning and fixing of the chips 33 with their contact sides provided with the chip contact surfaces 34 on the carrier substrate 30, the upper side 37 of the wrapping material layer 35 is provided with the contact material layer 43, without the s previously, as shown in FIG. 6, a material-removing machining of the wrapping material surface 41 has taken place.
• the formation of a contact structure 63 on the envelope material layer 35 and subsequently, as in FIG. 16, is then carried out in a first step to form a chip back contact contact arrangement 62 shown in FIG. 19, preferably by using a lithographic method illustrated, the formation of contact recesses 64 in the Hüllmateriallage 35, the contact material 3 1 of the Suub strats 30 exposed in the area of contact surfaces 39, so the s, as shown in Fig. 17, and as already with reference to FIG 5, contact posts 42 may be formed in the skin layer 35.
• contact recesses 64 and contact surfaces 65 of the contact columns 42 formed on the chip backs 36 in the envelope material layer 35 are preferably provided with a contact material 66 by electroless deposition of copper or a copper alloy, which in conjunction with the previously by structuring the contact material layer 43 formed contact structure 63 contact conductor 67 forms, which in each case connect a chip rear side 36 with a contact column 42, as shown in Fig. 19.
• the structuring of the carrier substrate 30, as already described with reference to FIGS. 10 to 12, takes place so that the chip module 73 shown in FIG. 20 is formed.
• both the connection scontaktseite 56 and a back side 57 of the chip module 73 with a preferably formed from an epoxy resin Pas siv réelle 58, 59 is provided, wherein in the Pas siv réelle 58 of the outer contact page 56 contact recesses 60 are formed, the contact surfaces 61 exposed so that s on the contact surfaces 61 Lotbumps 62 can be applied, the contact points for any external contact of the chip module 73 allow.
• 22 and 23 is an alternative to the contacting of the chip pads 34 with the carrier substrate 30 shown in FIGS. 10 and 11 by forming contact recesses 49 in the contact material layer 3 1 by structuring the contact material layer 3 1 and subsequent filling of the contact recesses 49 shown with contact material 50.
• a contacting of the chip connection surfaces 34 with a contact material layer 80 of a support sub strate 8 1 is provided with an electrically non-conductive adhesive application 82.
• Chipanschlus s vom 34 with the Kunststoffmateriallage 80
• Chipanschlus s vom 34 provided with contact increases 83, which brought to rest against the contact material layer 80 and subsequently connected by melting with the contact material layer 80 become.
• the chips 33 are fixed on the carrier substrate 8 1.
• the contact material layer 80 or the chips 33 are exposed to laser radiation from their rear side.
• the chip modules 89, 90 produced in this way can then, like the chip modules 72, 73 shown in FIGS. 13 and 21, have a passivation 58, 59, preferably formed of an epoxy resin, on both the terminal contact side 56 and its rear side 57 are provided, wherein in the Pas siv réelle 58 of the outer contact side 56 contact recesses 60 are formed, the contact surfaces 61 expose so that s on the contact surfaces 61 Lotbumps 62 can be applied, the contact points for any external Maisie- tion of the chip modules 89, 90 allow ,

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Manufacturing Of Printed Wiring (AREA)
• Led Device Packages (AREA)
• Wire Bonding (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Related Child Applications (1)

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Family

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• 2013
  • 2013-12-27 DE DE102013114907.3A patent/DE102013114907A1/de active Pending
• 2014
  • 2014-11-25 EP EP17151929.1A patent/EP3236489A3/de active Pending
  • 2014-11-25 US US15/106,605 patent/US10354971B2/en active Active
  • 2014-11-25 EP EP14815258.0A patent/EP3087592A2/de not_active Withdrawn
  • 2014-11-25 WO PCT/EP2014/075518 patent/WO2015096946A2/de active Application Filing
  • 2014-11-25 CN CN201480071312.XA patent/CN105849901B/zh active Active

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