EP2847796A1 - Procédé de réalisation de détecteurs infrarouges - Google Patents
Procédé de réalisation de détecteurs infrarougesInfo
- Publication number
- EP2847796A1 EP2847796A1 EP13721698.2A EP13721698A EP2847796A1 EP 2847796 A1 EP2847796 A1 EP 2847796A1 EP 13721698 A EP13721698 A EP 13721698A EP 2847796 A1 EP2847796 A1 EP 2847796A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- component
- base substrate
- substrate
- bonding
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 100
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 59
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 56
- 230000005855 radiation Effects 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims description 297
- 238000005538 encapsulation Methods 0.000 claims description 95
- 239000010949 copper Substances 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 59
- 229910052802 copper Inorganic materials 0.000 claims description 49
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 47
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 34
- 238000005240 physical vapour deposition Methods 0.000 claims description 18
- 238000005498 polishing Methods 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 13
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 238000001771 vacuum deposition Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005411 Van der Waals force Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 4
- YBNMDCCMCLUHBL-UHFFFAOYSA-N (2,5-dioxopyrrolidin-1-yl) 4-pyren-1-ylbutanoate Chemical compound C=1C=C(C2=C34)C=CC3=CC=CC4=CC=C2C=1CCCC(=O)ON1C(=O)CCC1=O YBNMDCCMCLUHBL-UHFFFAOYSA-N 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000009396 hybridization Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 154
- 238000001514 detection method Methods 0.000 description 35
- 229910004298 SiO 2 Inorganic materials 0.000 description 20
- 238000004140 cleaning Methods 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 20
- 238000000151 deposition Methods 0.000 description 18
- 229920005989 resin Polymers 0.000 description 18
- 239000011347 resin Substances 0.000 description 18
- 238000000227 grinding Methods 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 17
- 235000019592 roughness Nutrition 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 238000004377 microelectronic Methods 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 229910052738 indium Inorganic materials 0.000 description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 12
- 239000002131 composite material Substances 0.000 description 11
- 230000008901 benefit Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000007788 liquid Substances 0.000 description 8
- 238000011109 contamination Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 229910020175 SiOH Inorganic materials 0.000 description 4
- 239000011324 bead Substances 0.000 description 4
- 238000005219 brazing Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000010070 molecular adhesion Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000003776 cleavage reaction Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 230000007017 scission Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000011540 sensing material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000000930 thermomechanical effect Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000004566 IR spectroscopy Methods 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003556 assay Methods 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- DGJPPCSCQOIWCP-UHFFFAOYSA-N cadmium mercury Chemical compound [Cd].[Hg] DGJPPCSCQOIWCP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 229920006335 epoxy glue Polymers 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- GPYPVKIFOKLUGD-UHFFFAOYSA-N gold indium Chemical compound [In].[Au] GPYPVKIFOKLUGD-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000037452 priming Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- GGYFMLJDMAMTAB-UHFFFAOYSA-N selanylidenelead Chemical compound [Pb]=[Se] GGYFMLJDMAMTAB-UHFFFAOYSA-N 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14649—Infrared imagers
- H01L27/1465—Infrared imagers of the hybrid type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/03845—Chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
- H01L2224/221—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/802—Applying energy for connecting
- H01L2224/80201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80909—Post-treatment of the bonding area
- H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- the present invention relates to infrared detectors in general. It is particularly advantageous for photosensitive infrared detectors using sensing materials that must operate at cryogenic temperatures in order to reduce their thermal noise.
- infrared detectors in the form of photodiodes which operate by infrared photon absorption and which use quantum detection materials of the composite semiconductor type, for example materials known as II-V or III-VI, that is to say semiconductor materials whose constituent elements come respectively from columns III and V and columns II and VI of the periodic table of elements.
- This type of detector is also inherently sensitive to the background noise (phonons) of the crystal lattice of the material that composes it, it must then be cooled to cryogenic temperatures, typically at the temperature of liquid nitrogen (77 ° K). to increase its detection sensitivity of infrared radiation.
- the reading circuits are typically electronic circuits of the integrated circuit type essentially based on the use of silicon as a semiconductor material.
- infrared detectors therefore requires the ability to combine components from different technologies within the same device: composite semiconductors for the detection of infrared radiation on the one hand, and silicon for reading circuits on the other hand. somewhere else.
- composite semiconductors for the detection of infrared radiation on the one hand
- silicon for reading circuits on the other hand. somewhere else.
- a hybridization of chips that uses materials of a very different nature does not fail to cause problems.
- the obligation to have the infrared detectors operate at very low temperatures poses the problem of the different expansion of the chips between the ambient temperature and the temperature at which the device must operate.
- CTE coefficient of thermal expansion
- a current technique of hybridization of the infrared radiation detection chip and that of the reading circuits relies on the use of indium balls.
- the method is described for example in the French patent applications FR2938973 and FR2949903. It consists in depositing pure indium balls so that each photodiode of the infrared radiation detector circuit is connected to a single indium ball. Pure indium balls are also deposited on the contact zones of the reading circuit according to a matrix which is the mirror of that of the photodiodes.
- the two matrices are then assembled by soldering using the flip chip technique.
- the assembly is then heated to a temperature greater than or equal to the melting temperature of the indium to cause the beads to melt.
- the balls create a mechanical and electrical connection between the connection pads of the two chips. The temperature rise required for melting may not be without damage to the hybridized components.
- FIG. 8 A schematic diagram of the technique is illustrated in FIG. 8.
- the quality of the brazing is favored by the deposition of a deoxidation flow on the matrix of balls.
- the brazing flux makes it possible to eliminate the native oxide layer at the surface of the indium.
- the cleaning step following the brazing where it is necessary to force the passage of a cleaning liquid so as to evacuate all the flux residues in a very dense area connections .
- This cleaning step is all the more difficult to realize that the repeat pitch of the balls is low.
- One of the major flaws of this cleaning step is that a large amount of liquid must be used to ensure that it penetrates the entire connection area. It is a long and expensive step.
- the products contained in the cleaning liquid are aggressive and corrosive. By using a large amount of liquid, there is thus a significant risk of degradation of the interconnect balls.
- Encapsulation of the connection area also creates difficulties. It is generally made with an encapsulating material such as epoxy glue.
- the overflow of the encapsulation liquid by the lateral edges creates a residual bead which causes stresses on the hybridized component, which degrades its electrical functions and causes cleavages, that is to say breaks, which can cause the cracking of the hybridized components.
- the present invention therefore aims to provide a method of producing an infrared detector that meets at least some of the difficulties described above.
- the present invention relates to a method of producing at least one photosensitive infrared detector by assembling a first electronic component comprising a plurality of photodiodes sensitive to infrared radiation and a second electronic component comprising at least one electronic circuit for reading the plurality of photodiodes.
- the method comprises: obtaining, on each of the first and second components, a bonding face formed at least partially by a layer based on silicon oxide SiO x , with x being between 1 and 2,
- obtaining the bonding faces comprises, preferably for each of the first and second components:
- CMP chemical mechanical polishing
- the direct bonding of two components means that the bonding is obtained by the chemical bonds that are established between the two surfaces brought into contact. These two surfaces have sufficiently small roughnesses that the Van der Waals forces provide, preferably on the basis of only two components.
- Direct bonding does not require an intermediate bonding layer. It is further obtained without requiring the application of significant pressure.
- the invention makes it possible to use highly conductive materials such as copper without surface oxide.
- the invention also makes it possible to eliminate brazing constraints. It also allows for short connections.
- the term "component" for designating the first and second components can be replaced by the term "chip” or by the term “electronic circuit”.
- the first component can thus also be designated 'detector circuit' or 'detection chip'.
- the second component can thus also be designated 'reading circuit' or 'reading chip'.
- the layer based on silicon oxide forming each bonding face may thus be a layer of SiO, Si0 2, or any silicon oxide SiO x which x is between 1 and 2, for example 1.2, 1. 5, 1 .8.
- a layer formed of SiON, SiOH, SiOC, SiOCH, SiONH may also be suitable.
- This layer is so neatly electrically insulative and transparent to the wavelengths of the infrared. It is compatible with semiconductor technologies and has good mechanical and chemical resistance to the temperature conditions imposed by the photoconductive material.
- the method according to the invention further comprises at least one of the following features and steps:
- obtaining the bonding faces comprises a chemical mechanical polishing (CMP) carried out so as to reduce their root mean squared roughness (RMS) to a value less than or equal to 10 ⁇ or 1 nanometer (nm), and preferably less than or equal to 5 ⁇ is 0.5 nanometer (nm).
- CMP chemical mechanical polishing
- the bonding step comprises the application of a bonding wave.
- the bonding wave comprises the application of one or more localized pressure points.
- the application of the bonding wave comprises the application of one or more localized pressure points on an area less than a few square millimeters, typically on a surface smaller than 10 mm 2 , or even a surface smaller than 5 mm. 2 , or an area less than a few tens or hundreds of ⁇ 2 .
- the bonding step comprises contacting the bonding faces at room temperature.
- the bonding step comprises contacting the connecting faces in the absence of a pressure exerted on the entire surface of one or the other of the first and second components. More generally, no pressure greater than 500 kN is exerted on the entire surface of one or the other of the first and second components.
- the direct bonding of the two components is provided, preferably entirely, by the Van der Waals forces, on all facing surfaces.
- the vacuum deposition makes it possible to obtain layers of a high density, which makes it possible, after chemical mechanical polishing (CMP), to achieve a very low roughness, typically a mean square roughness (RMS) of a lower value. or equal to 1 nanometer.
- Vacuum deposition to obtain a bonding face for the first and / or second component is preferably accomplished by any of the following techniques: Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) preferably plasma enhanced chemical vapor deposition (PECVD).
- PVD Physical Vapor Deposition
- CVD Chemical Vapor Deposition
- PECVD plasma enhanced chemical vapor deposition
- vacuum deposition is carried out at a temperature below 300 ° C.
- obtaining a bonding face on the first component and a bonding face on the second component comprises forming, on these bonding faces, copper (Cu) encrustation zones embedded in these faces and, arranged so as to coincide when these connecting faces are positioned opposite.
- the copper inlay zones occupy an area of between 18% and 40% of the surface area of this bonding face.
- the copper incrustation zones occupy an area of between 18% and 40% of the area of each of the bonding faces. Even more preferably, this area is between 15% and 30%.
- obtaining the bonding face on the first component is performed so that the layer based on silicon oxide (SiO x ) covers the entirety of this bonding face with the exception of the zones copper and tracks and / or vias electrical interconnection.
- SiO x silicon oxide
- the copper zones are turned towards the outside of each of the connecting faces. They are arranged on the surface of each of the connecting faces so as to be superimposed when the connecting faces are facing each other. They are in contact when the connecting faces are in contact.
- These copper zones have no electrical function. They are not connected to interconnections or components such as photodiodes. In this sense they clearly differ from the electrical interconnections made in the bonding layers. Each occupies a significantly larger area than a line or an electrical interconnection via.
- These copper zones make it possible to significantly strengthen the fixation of the first and second components because the Cu-Cu covalent bonds are stronger than the oxide-oxide covalent bonds.
- Each of the two components comprises, at its face intended to be in contact with the face of the other component, the silicon oxide-based layer and interconnection tracks.
- a direct bonding annealing is carried out at a temperature below 300 ° C.
- this temperature makes it possible to avoid the diffusion of doping species present in the photodiodes.
- a thinning step of the first component is carried out so that its thickness is less than about 35 times or more of the thickness of the second component and preferably so that its thickness is between ⁇ and 20 ⁇ and the thickness of the second component between 725 ⁇ and ⁇ ⁇ .
- this thinning allows the first component to undergo without damage the dimensional variations of the second component.
- the risks of cleavage or breakage are thus significantly reduced even when the detector is operated at very low temperatures.
- the thinning step is performed after the direct bonding step.
- At least one of the components forms a layer assembly, this assembly comprising a bonding face formed at least in part of the silicon oxide layer.
- the method comprises, prior to obtaining a bonding face on the first component, a step of preparing the first component.
- the step of preparing the first component comprises: obtaining at least one base substrate integrating or intended to integrate the plurality of photodiodes; encapsulation of the base substrate in an encapsulation layer, so that the major dimension of the first component comprising the base substrate and the encapsulation layer is greater than the main dimension of the base substrate.
- the main dimensions are the maximum dimensions taken along directions contained in planes parallel to the connecting faces.
- the encapsulation is preferably carried out so that the encapsulation layer entirely covers the base substrate with the exception of one face of the base substrate intended to be placed facing the second component.
- the invention enables the manufacture of photosensitive detectors by using size components that can easily be adapted to standard equipment in the microelectronics industry.
- the first component comprising the base substrate and the encapsulation layer thus forms a plate having two opposite planar faces. It can be called “galette” or “slice” or “wafer” in English.
- the invention is not limited to a specific shape of periphery defined by the plate. In particular, this plate may be circular, hexagonal, rectangular, square or other.
- the main dimension of a component is the maximum dimension of the component taken along a direction contained in the plane of one of the faces of the component.
- the main dimension is the diameter of the disk.
- the main dimension is the diagonal of the rectangle.
- the first component comprising the base material encapsulated in the encapsulation layer has a standard dimension in the microelectronics industry. Typically it forms a disc with a diameter of 100, 200, 300 or 450 mm in diameter.
- the first and second components form plates and a diameter or diagonal of the first component is: greater than the diameter or diagonal of the base substrate and approximately equal to the diameter or a diagonal of the second component.
- the second component also has a plate shape.
- the peripheries of the first and second components are identical. They have the same shape and size, or not. Indeed, it is possible to integrate a square substrate in a round wafer.
- the encapsulation layer is a layer based on silicon oxide SiO x with x between 1 and 2.
- This layer can thus be a layer of SiO , SiO 2 , or any silicon oxide SiO x whose ratio x is between 1 and 2, for example 1 .2, 1 .5, 1 .8.
- a layer formed of SiON, SiOH, SiOC, SiOCH, SiONH may also be suitable.
- This layer is also electrically isolated and transparent at the wavelengths of the infra-red. It is compatible with semiconductor technologies and has good mechanical and chemical resistance to the temperatures imposed by the photoconductive material.
- the base substrate has a coefficient of thermal expansion (CTE) of between 4 and 8 ppm / ° C and preferably between 5 and 7 ppm / ° C.
- This substrate is for example InSb.
- the second component comprises a substrate carrying the electronic reading circuit and having a coefficient of thermal expansion (CTE) of between 1.5 and 4 ppm / ° C. and preferably between 2.5 and 3.5 ppm. C.
- CTE coefficient of thermal expansion
- a step of fixing the base substrate on a handling substrate is carried out by direct or organic bonding.
- a step is performed to obtain a fixing layer on at least a portion of a face of the base substrate and a layer of fixing on at least a part of a face of the handling substrate.
- This fixing layer may be a native oxide or an oxide deposited by a PECVD or PVD method.
- the step of fixing the base substrate on the handling substrate is carried out by direct bonding of their attachment layers.
- the fixing layers are layers based on silicon oxide SiO x with x between 1 and 2.
- This layer can thus be a layer of SiO , SiO 2 or any silicon oxide SiO x whose ratio x is between 1 and 2, for example 1 .2, 1 .5, 1 .8.
- a layer formed of SiON, SiOH, SiOC, SiOCH, SiONH may also be suitable.
- the fixing layer of the base substrate corresponds to the bonding face of the first component.
- the fixing layer of the base substrate is disposed on a face opposite to the bonding face of the first component.
- the handling substrate has a receiving housing and the at least one base substrate is fixed in the receiving housing during the fixing step.
- the plurality of photodiodes is integrated into the base substrate before encapsulation of the base substrate in the encapsulation layer.
- a free face of the encapsulation layer is attached to a handle substrate, and then the handling substrate is at least partially removed.
- the free face of the encapsulation layer is a face that does not have the base substrate.
- the first component after encapsulation, has a first face formed by the encapsulation layer and the base substrate. This first face is then attached to the handling substrate.
- the first component also includes a second face formed solely by the encapsulation layer. It is this second face which is fixed on the handle substrate.
- the fixing of the first component on the handling substrate is effected by the connecting face of the first substrate and the withdrawal of the handling substrate is carried out so that the first component retains a layer based on silicon deposited on the base substrate prior to its attachment to the handling substrate, and preferably retains a silicon oxide-based layer provided by the handling substrate for the fixing step.
- a step is performed to obtain a bonding layer on at least a portion of a face of the handle substrate, and the step of fixing the encapsulation layer on the handle substrate is performed by direct bonding of the bonding face of the handle substrate on a free face of the encapsulation layer.
- the first component comprises a plurality of base substrates and the step of preparing the first component comprises encapsulating the plurality of base substrates in a single encapsulation layer.
- each individual base substrate consists of a plurality of chips with a network of integrated photodiodes and previously tested to integrate only the detection strips with better yields.
- the plurality of photodiodes is integrated into the base substrate after encapsulation of the base substrate in the encapsulation layer.
- the encapsulation of the base substrate is performed so that the encapsulation layer covers at least one face of the base substrate. Then, at least one access to the face of the base substrate which is covered by the encapsulation layer is carried out through the encapsulation layer and the photodiodes are produced by ion implantation of dopants by said at least one access.
- the second component comprises a number of read circuits equal to the number of photodiodes. It is a matrix of reading pixels that reads a matrix of photodiode pixels.
- At least one space is created between the periphery of the base substrate and the encapsulation layer.
- this space allows the basic substrate to be deformed under the effect of temperature variations independently of the deformations of the second component, thus reducing the mechanical stresses and the risks of rupture or cleavage.
- this gap extends over the entire periphery of the base substrate.
- This space thus forms a trench between the encapsulation layer and the base substrate. It is obtained either by sampling the material forming the base substrate or, preferably, by taking the material forming the encapsulation layer.
- the step of bonding the first component and the second component forms a plurality of photosensitive infrared detectors, each of which comprises at least one photodiode and a read circuit, and, after the collaging step, a step of cutting to separate the photosensitive infrared detectors from each other.
- the invention describes a method for producing at least one photosensitive detector by assembling a first electronic component comprising a plurality of photodiodes and a second component.
- electronic device comprising at least one electronic circuit for reading the plurality of photodiodes, the method comprising, prior to assembly, a step of preparing the first component comprising:
- the encapsulation layer encapsulates the base substrate so as to completely cover the base substrate with the exception of one face of the base substrate intended to be placed facing the second component.
- the first component and the second component are assembled at a later stage.
- This method of preparing the first component can be combined with all the steps described above.
- the invention thus makes it possible to proceed with the manufacture of photosensitive detectors by using the standard equipment of the microelectronics industry.
- the diameter of the base substrate is smaller than the diameter of the second component and the diameter of the first component is approximately equal to the diameter of the second component.
- each component has a plate shape.
- the photodiodes are preferably sensitive to infrared radiation and the detector is an infrared photosensitive detector.
- the invention relates to a photosensitive detector, preferably an infrared detector, comprising a first electronic component comprising a plurality of photodiodes preferably sensitive to infrared radiation and a second electronic component comprising at least one electronic circuit. reading of the first component.
- the first and second components each have a connecting face and are bonded directly to one another by their connecting faces, each of the connecting faces being formed at least in part by a layer based on silicon oxide SiO x with x between 1 and 2.
- the first component comprises: at least one base substrate comprising the plurality of photodiodes and an encapsulation layer.
- Layer encapsulation encapsulates the base substrate so as to completely cover the base substrate with the exception of one face of the base substrate to be placed facing the second component.
- each of the connecting faces also carries copper (Cu) inlay zones arranged to coincide with the copper incrustation zones carried by the other bonding face, the zones of FIG. copper inlay of each bonding face occupying an area of between 18% and 40% of each bonding face.
- Cu copper
- the invention relates to an assembly for producing a photosensitive detector, preferably an infrared detector.
- the assembly is a set of components used in the photosensitive detector composition.
- the assembly comprising at least one first electronic component comprising a plurality of photodiodes preferably sensitive to infrared radiation and at least one second electronic component comprising at least one electronic reading circuit.
- the first and second components each have a bonding face formed at least in part by a layer based on silicon oxide SiO x , with x being between 1 and 2.
- the first component comprises: at least one base substrate comprising the plurality of photodiodes and an encapsulation layer.
- the encapsulation layer encapsulates the base substrate so as to completely cover the base substrate with the exception of one face of the base substrate to be placed facing the second component.
- each of the connecting faces comprises copper (Cu) inlay zones arranged to coincide with the copper inlay areas carried by the other bonding face, the incrustation zones.
- copper of each bonding face occupying an area between 18% and 40% of the surface of this face.
- FIGS. 1a to 1i describe the steps of an exemplary method according to the invention in which a first electronic component comprising photodiodes sensitive to infrared radiation is formed and this first component is assembled on a "handle" substrate to form a manipulable assembly in a standard microelectronic manufacturing line.
- FIGURES 2a to 2c describe the preparation of a second electronic component containing the reading circuits of the photodiodes.
- FIGURES 3a to 3c describe assembly steps by direct bonding of the two electronic components, the one containing the photodiodes and the one containing the reading circuits.
- FIGURES 4a and 4b illustrate examples of complementary steps of the method of the invention that can be performed after the two components have been assembled.
- FI GU RES 5a to 5c another example of manufacture of the first component, in which example the photodiodes are made after assembling a base substrate on a handling substrate.
- FIGS. 6a to 6f another example of manufacture of the detection component, for example in which a receiving housing for the base substrate is produced in the handling substrate.
- FIGS. 7a to 7c illustrate another exemplary embodiment of the invention, in which there are several basic substrates each comprising infrared radiation detectors that are assembled on the same manipulation substrate to form an electronic detection component. .
- Figure 8 illustrates an example according to the state of the art.
- the term “over”, “overcomes” or “underlying” or their equivalents do not necessarily mean “in contact with”.
- the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another but that means that the first layer at least partially covers the second layer by being either directly in contact with it or separated from it by another layer or another element.
- the expression “based on silicon oxide” means “comprises a silicon oxide optionally associated with at least one other element”.
- this at least one other element makes it possible, for example, to form a layer made of one of: SiON, SiOH, SiOC, SiOCH and SiONH.
- FIGS. 1 to 1 i describe the steps of the method in which a detection component comprising the infrared radiation (IR) detector circuits is produced and this first component 100, 230 is assembled on a "handle" substrate 300 in order to form a together manipulable in a standard manufacturing line like those set up by the microelectronics industry.
- IR infrared radiation
- These include lines used for the manufacture of integrated circuits, typically electronic circuits of the CMOS type, acronym for "complementary metal-oxide-semiconductor", that is to say, electronic circuits based on transistors. complementary metal-oxide-semiconductor type.
- the component comprising the detection circuit can also be designated first component 100, 230, detection chip or detection chip circuit. It comprises in particular a base substrate 100 incorporating the photodiodes 1, 10. As will be detailed hereinafter with reference to a nonlimiting but advantageous embodiment, the component comprising the detection circuit may also comprise a layer 230 encapsulating the substrate. base 100. It also includes electrical tracks and advantageously but not limited to dummy copper zones often referred to by the English word "dummies”. It further comprises at least one layer based on silicon oxide 140, 210, preferably silicon dioxide, on one of these faces, described as a bonding face and whose function relating to bonding will also be detailed by the following.
- a quantum-detecting material is used that can be made of one of the various composite semiconductors used by the microelectronics industry.
- This is for example of composite semiconductor materials said IV-VI whose constituent elements come from columns IV and VI of the periodic table of elements.
- This is for example a ternary alloy such as PbSnTe and a binary alloy such as PbSe; that is to say respectively: lead-tin telluride and lead selenide.
- the composite semiconductor used for the base substrate 100 may also be a III-V material such as, for example, following materials: InSb, InP, GaAs, InAs, InGaAs, InGaSb and InAsSb. That is to say respectively: indium antimonide, indium phosphide, gallium arsenide, indium arsenide, gallium indium arsenide, gallium indium antimonide, and arsenide-antimonide indium. It can also be made of composite materials known as II-VI such as HgCdTe, that is to say the telluride mercury-cadmium. In a preferred embodiment of the invention the material of the base substrate 100 uses indium antimonide (InSb) which is known for its efficient IR detection in the wavelength range from 3 to 5 ⁇ .
- InSb indium antimonide
- the base substrate 100 of the detector component may be made of one of the following materials: II-V, II-VI, IV-IV (such as SiGe), IV-VI (such as the PbSe).
- the principal dimension of a component is the maximum dimension of the component taken along a direction contained in the plane of one of the two parallel faces of the component.
- the main dimensions are thus contained in planes parallel to the connecting faces 192, 492.
- the main dimension is contained in a horizontal plane.
- the thickness of a layer or a substrate is taken in turn in a vertical direction and perpendicular to the main dimensions.
- the size of the base substrate 100 is the diagonal or the diameter of its face intended to be placed facing the second component 400; the dimension of the first component 100, 230 is the diagonal or the diameter of its face intended to be placed opposite the second component 400; the dimension of the second component 400 is the diagonal or the diameter of its face intended to be placed facing the first component 100, 230.
- FIG. 1a shows the photodiodes 1 1 0 constituting the infrared radiation detectors that are produced in the basic substrate 1 00.
- the photodiodes can be PN-doped junctions or include an intrinsic intermediate zone, that is to say not doped, so as to form a so-called PIN diode.
- Photodiodes are conventionally manufactured by ion implantation of dopants.
- the base substrate 100 for the detection is typically 120 ranging from 700 to 1,000 ⁇ .
- the base substrate 100 is first cleaned to remove the native oxide at the surface and improve the adhesion of the coating layer.
- silicon oxide (SiO2) which will be deposited therein for gluing on the handling substrate.
- a thin layer of silicon oxide 140 is then deposited at low temperature on the InSb which preferably constitutes the material of the base substrate 100.
- the deposit is typically made using a method known as PECVD ( "Plasma-enhanced chemical vapor deposition" means plasma-enhanced chemical vapor deposition) at a temperature below 300 ° C.
- the gaseous plasma preferably consists of silane (SiH 4) and nitrous oxide (N 2 O).
- the invention provides for limiting the temperature of the deposition operation to a value of less than 300 ° C., since the preliminary photodiode fabrication steps have been carried out at temperatures that were themselves lower than this value.
- the other known deposition techniques known as PVD and CVD, acronyms of the English “physical vapor deposition” and “chemical vapor deposition”, that is to say, respectively, physical or chemical vapor deposition are also suitable for little that the temperature stress mentioned above can be respected.
- the surface of the oxide is then treated by chemical mechanical polishing, operation generally designated by its acronym CMP of the English "chemical mechanical polishing".
- CMP chemical mechanical polishing
- the purpose of this operation is to make the surface of the oxide plane.
- the chemical-mechanical polishing technique used may be that described in Chapter 14.2 of Handbook of Cleaning for Semiconductor Manufacturing, 201 1, Ed. Wiley.
- polishing residue abrasive particles and polishing liquid generally referred to by their name.
- the roughness is quantified by a parameter called RMS, an acronym for roughness mean square, which measures the root mean square.
- the surface is free from particulate contamination to create the intermolecular bonds which produce the adhesion of the base substrate 100 to the handling substrate 200 as will be seen hereinafter.
- the CVD and PVD deposition techniques mentioned above, preferably PECVD, for forming the silicon oxide layer 140 make it possible to obtain a particularly dense silicon oxide layer 140.
- These deposition techniques thus contribute to obtaining, after CMP, a surface state whose roughness RMS is less than or equal to 1 nm.
- the handling substrate 200 is prepared separately. As the name suggests it serves mainly as mechanical support. It has a size greater than 220 which must be compatible with the manufacturing line of the electronic reading circuits which will eventually be assembled with the infrared radiation detectors of the base substrate 100.
- the handling substrate 200 will itself be covered with a thin layer 21 0 based on silicon oxide. It may be in this case an oxide obtained by thermal growth at high temperature, since the handling substrate contains no sensitive device. It can also be deposited, as above by P E CVD, CVD or PVD, at a sufficiently low temperature so as not to damage the photodiodes. As indicated above, these deposition techniques make it possible to obtain a layer 210 based on high density silicon oxide.
- the vacuum deposition allows the density of the deposited layer to be sufficient for a chemical mechanical polishing (CMP) of the deposited layer to obtain a root mean square (RMS) of a value less than or equal to 1 nanometer.
- CMP chemical mechanical polishing
- RMS root mean square
- the deposited thickness is typically 500 nm.
- the oxide surface of the handling substrate is polished. During this operation approximately 250 nm of SiO 2 is removed. After cleaning, a flat surface of low roughness is obtained. As above, a roughness that is not greater than 10 ⁇ or even 5 ⁇ and a surface free of particulate contamination will improve molecular adhesion.
- the handling substrate 200 may be of different size, of different geometry, of different thickness, and made of a material different from that of the base substrate 1 00.
- handling substrate 200 serves essentially as a mechanical support for the base substrate 100 containing photodiodes 1 10.
- the material of which it is made must be compatible with a subsequent mechanical grinding step described in FIG. This step, which is generally designated by the term “grinding", will make it possible to remove the handling substrate and allow the substrate 100 containing the infrared radiation detectors to be assembled with the one containing the reading circuit.
- the material of the handling substrate 200 may be chosen from among the following materials: glass, silicon (Si), germanium (Ge) or sapphire.
- a material having a coefficient of thermal expansion close to that of the base substrate 100 will be chosen above all in order to avoid, during the annealing operation described hereinafter, which will create thermomechanical stresses, a on the other hand, a delamination of the bonding interface which can create cracks in the quantum-sensing material, on the other hand, a misalignment of the pads and / or connection tracks which will be detrimental during the final bonding of the component containing the detectors infrared radiation with the component containing the reading circuits.
- the surfaces of the base substrate 100 and of the handling substrate 200 are brought into contact via the silicon oxide atoms of their respective oxide layers 140 and 210, implementing the so-called Van der Waals forces.
- One or more pressure points are made on the wafer 200 to initiate a sticking wave (molecular adhesion wave).
- an annealing in the range 200-300 ° C is then performed for two hours to create covalent bonds to enhance the strength of the bonding between the base substrate 100 and the handling substrate 200.
- the annealing can be done or not. under nitrogen (N2) or argon (Ar) gas atmosphere.
- FIGS. 1 a to 1 c The steps described in FIGS. 1 a to 1 c above allow the reconstitution of heterogeneous substrates 100, 200 by direct bonding. The two substrates 100, 200 are then integral.
- the base substrate 100 is then thinned by the grinding technique mentioned above to a thickness 150 less than or equal to 15 ⁇ " ⁇ .
- mechanical thinning done with a fine grinding wheel high-porosity polymer-bonded finishing wheel, diamond grain size in a range of 2 to 4 ⁇
- Chemical cleaning is performed to remove particles remaining on the surface after grinding.
- the base substrate 100 is then encapsulated in an encapsulation layer 230.
- the encapsulation is carried out so that the encapsulation layer 230 completely encapsulates the base substrate 100 at the same time.
- this face is intended to be covered by the layer 140, as shown in Figure 1 d.
- the base substrate 100 associated with the encapsulation layer 230 forms a set of the also designated infrared radiation detection circuit, detection substrate or first component.
- This first component comprises other elements that will be mentioned in the following description.
- the base substrate 100 mu of the encapsulation layer 230 may have a diameter of, for example, 2 inches, 3 inches, be round or square.
- the size of such a substrate 100, 230 square can be 37x38 mm or 47x48 mm.
- This encapsulation layer 230 is preferably a silicon oxide (SiO 2) layer. It is advantageously obtained as previously by PECVD from a gaseous plasma of N 2 O / SiH 4.
- the deposited thickness is less than 30 ⁇ . In a preferred embodiment a thickness of 25 ⁇ m of SiO 2 is deposited.
- the deposition is carried out at low temperature, that is to say at a temperature below 300 ° C.
- this is to minimize the stress on the base substrate 100.
- the low temperature deposition method of the oxide is chosen for its compliance with the temperature limits of the photodiodes present in the detector material and avoids the risk diffusion of the dopant species present therein.
- the oxide also has the following features: compatibility with the grinding and chemical mechanical polishing (CMP) stages, low mechanical stress, low surface roughness after grinding and especially after CMP, high deposition speed , Good overlay that is to say that there is continuity of the Si02 at the base of the periphery of the substrate 100.
- CMP chemical mechanical polishing
- the oxide layer 230 may be deposited by other techniques, in particular those referred to as PVD and CVD already mentioned, insofar as the deposition mode and the oxide obtained remain compatible with the above constraints. .
- the assembly comprising the base substrate 100, the encapsulation layer 230 and the handling substrate 200 advantageously form a plate having two opposite flat faces. It is therefore easily manipulated by the devices of the microelectronics industry.
- the next step is to plan the deposited oxide layer 230.
- the planarization can be carried out according to two different methods:
- a photolithography step is performed to open, in a pre-deposited resin layer, a central zone corresponding to the area of the base substrate 100 ( to discuss).
- About 15 ⁇ of SiO 2 are then etched if the thickness of SiO 2 deposited is 25 ⁇ by dry or wet etching.
- the resin is removed by plasma in a confined chamber and / or wet by conducting an operation called "stripping" or pickling of this resin.
- the planarization of the oxide surface by CMP is performed to leave a thickness 241 of 1 to 3 ⁇ on the central zone 100 after CMP.
- the polished SiO 2 surface is then cleaned.
- the 25 ⁇ oxide is mechanically thinned to a thickness of approximately 19 to 22 ⁇ using two grinding sequences.
- the planarization of the oxide surface by CMP makes it possible to remove a thickness of 2 to 3 ⁇ to leave as above a thickness 241 of 1 to 3 ⁇ m on the central zone 1 00.
- the surface of polished SiO 2 is then cleaned under the same conditions as above.
- an oxide layer of about 1 to 3 m above the material constituting the base substrate 100 is thus left, in order, as we shall see, to be able to make the metal interconnection tracks or postpone a handle substrate.
- the first component, formed by the encapsulated base substrate 100, has in top view (that is to say perpendicular to the view of Figure 1 d) the shape that is desired to give the detector to be prepared.
- the invention is not limiting of any specific form. It can typically be a disc shape of a desired diameter. It can also be a form of hexagon, rectangle, square or other.
- a so-called "handle” substrate 300 is bonded to the base substrate 100 containing the radiation detector circuits I R.
- the handle substrate 300 is adhered to a free face of the encapsulation layer 230, ie, the face opposite to the face which is fixed to the handling substrate 200.
- the handle substrate 300 may be chosen for example from the following materials: germanium (Ge), glass, silicon (Si) and sapphire. This bonding can be done by direct bonding or by means of an organic glue.
- the handle substrate 300 is prepared separately by depositing thereon a POCVD layer 31 0 of SiO 2 of the order of 500 nm. The surface of the oxide is then treated with CMP to remove a thickness of about 250 nm.
- the preparation of the handle substrate 300 is identical to that previously described for the handling substrate 200 in FIG. 1b. As in the previous case, it is sought to obtain after polishing and cleaning a flat hydrophilic oxide surface having a roughness preferably of less than 10 ⁇ or even 5 ⁇ , and free from particulate contamination in order to be able to improve the molecular adhesion via intermolecular links.
- the surfaces are brought into contact via the silicon oxide atoms and annealing is carried out under the same conditions in order to reinforce the strength of the bonding between the handle substrate 300 and the substrate comprising the silicon layer.
- encapsulation 230 encapsulating the base substrate 100.
- a thermally and mechanically compatible organic adhesive is chosen with the following technological steps for producing the interconnection tracks. Steps that include plasma etching, chemical cleaning, plasma deposition.
- a polyimide adhesive whose glass transition temperature (TG) is greater than or equal to 250 ° C. is preferably chosen.
- the assembly comprising the encapsulated base substrate 100 associated with the handling substrate 200 and the handle substrate 300 advantageously forms a plate.
- the multilayer assembly is thinned from the accessible face 202 of the handling substrate 200, integral with the base substrate 100 containing the detector circuits. IR radiation, until reaching the silicon oxide layer previously carried by the handling substrate 200. Stopping the removal of the material forming the handling substrate 200 is referenced 232.
- the withdrawal of the handling substrate 200 is made such that the first component comprising the encapsulated base substrate 100 keeps the oxide layer 140 deposited thereon and further retains the oxide layer 21 which has been previously deposited on the handling substrate 200. Thinning is advantageously obtained mechanically by grinding, wet etching and CMP.
- the metal interconnection tracks of the first component ie, the metal interconnection tracks of the infrared radiation detection circuit, are then made. They will be brought into contact during the final bonding with the metal interconnection tracks of the second component 400 ie, the interconnection tracks of the photodiode reading circuit.
- the realization of the metal interconnection tracks on the side of the infrared radiation detector circuit comprises the following steps, the result of which is shown in FIG. 1 g:
- dummies are dummy metallic zones made of copper (Cu) in this example, which are not used for the interconnections but which will make it possible to ensure a better bond Cu / Cu between the base substrate 100 containing the infrared radiation detector circuits and the reading component 400 which will come into contact therewith during a subsequent direct bonding phase.
- damascene also called damascene
- the lines and copper strips therefore not only serve to ensure the passage of the electric current but also participate in the Cu / Cu and Cu / SiO 2 bonding between the first component 100, 230 containing the photodiodes and the second reading component 400 during the phase direct bonding.
- the copper surface should occupy a fraction of not less than 18 percent and not more than 40 percent of the total bond area. It is particularly the role of the dummies to allow to adjust the copper surface participating in the collage so as to optimize this operation.
- the previous lithography step is followed by a dry etching step lines and dummies. Approximately 500 nm of SiO 2 are etched and then most of the protective resin is removed by plasma. Then, a fine cleaning of the SiO 2 surface wet is carried out in order to remove the resin residues.
- a bonding layer and a barrier layer are deposited by conventional deposition techniques, ie PVD and / or CVD already mentioned.
- the bonding layer acts as an adhesion layer.
- the main function of the barrier layer is to prevent diffusion of the copper towards the detector substrate 100.
- the deposited metals and the processes used must all respect the temperature limit imposed by the embodiment of the photodiodes, which limit is the same as has already seen lower than 300 ° C.
- a thin layer of copper of the order of 300 nm is then deposited. It is typically deposited by PVD.
- seed layer that is to say, priming layer
- a cleaning of the underlying metal level which serves as a barrier After which is deposited by electrolysis a larger copper layer of the order of 2 to 5 ⁇ . The copper is then annealed at 250 ° C under vacuum or not to improve its adhesion. All of these layers are represented by the layer 180 in FIG. 1h.
- the previous deposition operations are followed by a metal polishing step before direct bonding, the result of which is shown in FIG.
- the face of the base substrate 100 on which the copper has been deposited is polished by CMP.
- the polishing is stopped when the mixed SiO 2 / Cu surface is reached and the desired result of inlaying copper in all the zones 190 etched initially by photoengraving (interconnections, dummies and vias) in the layers oxide 140 and 210 according to the so-called damascene technique (also called damascene process).
- a wet cleaning under the action of brushes or "scrubber" of the polished surface is then performed. This gives a flat surface 192 with a low roughness of about 5 ⁇ , free of particulate contamination.
- the encapsulation layer 230 is directly in contact with the base substrate 100.
- the silicon oxide layer 140 forming part of the bonding layer is in direct contact with the base substrate 100.
- the photodiodes 1 10 are in contact with the base substrate 100. contact with the silicon oxide layer 140 forming part of the connecting face 192.
- the connecting face 192 of the first component 100, 230 is carried on the one hand by a face of the base substrate 100 preferably covered with the layer 140 and on the other hand by a face of the encapsulation layer 230 which extends in the plane of the layer 140.
- FIGS. 2a, 2b and 2c describe the preparation of the second component 400, that is to say the component containing the reading circuits of the photodiodes 1 10.
- This component 400 can also be designated read substrate, read circuit or chip Reading (ROIC) stands for ReadOut Integrated Circuit. It is typically formed by a substrate of the type produced by the microelectronics industry which essentially uses silicon to deliver all kinds of integrated electronic circuits. The invention does not make any other hypothesis on the nature of the electronic reading circuits which have been manufactured in the upper layers 402 of the second component 400. However, it will typically be, as already mentioned, generally CMOS-type circuits. from an elaborate substrate of SOI type, acronym for "silicon on insulator", that is to say silicon on insulator. CMOS technology makes it possible to produce all kinds of high-performance circuits, logical and analog, and thus read circuits suitable for photodiodes which have been manufactured separately as described above in FIGS. 1a to 1i.
- ROIC ReadOut Integrated Circuit
- FIGS. 2a, 2b and 2c show more particularly the final manufacturing operations of the component 400 containing the reading circuits and the preparation of the surface state for the purpose of bonding.
- at least two layers of metal connections are generally made which will allow the electrical interconnection between the photodiodes and the reading circuits present on this reading component 400.
- These are represented by the set of layers 402 comprising underground metal tracks 494 for resumption of contact.
- FIGS. 2a to 2c illustrate the operations that will allow bonding and interconnection of this component with the detection component 100 containing the photodiodes 1 10.
- FIG. 2b where a first level of metal 410 is shown
- FIG. 2c where a second level of metal 420 is shown
- the materials and techniques used are shown. are preferably similar or identical to those used for producing the first component containing the photodiodes 1 10 for detecting infrared radiation. Therefore, for the formation of successive silicon oxide layers can be used to the aforementioned techniques of PVD and CVD, preferably PECVD techniques that allow to obtain a deposited layer having a high density.
- damascene also called damascene process. A technique which consists, as has been seen in FIGS.
- a first oxide layer 405 is for example represented in FIG. 2a from which a first level of interconnections 410 will be made, followed by a second level of interconnections 420.
- FIGS. 2a to 2c are only representative examples of the implementation of the invention. In particular, more than two levels of interconnections can obviously be realized.
- the annealing step will preferably be carried out under vacuum with three steps in a temperature range from 150 ° C. to 400 ° C., the reading component 400 being able to withstand at this stage without disadvantage of higher temperatures than those of photodiodes which is limited to 300 ° C as already mentioned.
- the etching of the vertical interconnections, vias can be done by providing a stop layer of the etching (not shown) typically made of silicon nitride (SiN) which is deposited preferentially by PECVD to a typical thickness of 40. nm.
- a stop layer of the etching typically made of silicon nitride (SiN) which is deposited preferentially by PECVD to a typical thickness of 40. nm.
- CMP chemical mechanical polishing
- the front face of the reading substrate is polished by CMP. Polishing stops when the mixed SiO 2 / Cu surface is reached. The polished surface is then cleaned using a scrubber, that is to say a wet cleaning under the action of brushes.
- the metal zones 490 at the surface of the reading component 400 generally comprise alignment marks (not shown), so-called “dummies” pads, interconnecting metal lines and vias, all of which will have have been delimited by photolithography of the oxide layers to correspond and adapt to the corresponding areas 190 of the base substrate 100. All these areas will also participate in obtaining a better adhesion during the direct bonding of the two substrates formed by the detection 100, 230 and reading 400 components as described below.
- FIGS. 3a to 3c describe the assembly steps of the two components, that containing the photodiodes and that containing the reading circuits, by direct bonding.
- each of these two components advantageously forms a plate having two opposite flat faces, which makes their easy handling.
- the detection component thus has a face 192, described as connecting face.
- This bonding face 192 is formed by at least one silicon oxide-based layer 140, 210 in which interconnection tracks and preferably dummy copper zones are formed.
- the reading component 400 also has a connecting face 492.
- This connecting face 492 is also formed by a silicon oxide layer and carries interconnection tracks and preferably dummy areas of copper.
- the bonding faces 192 and 492 have been polished and cleaned to maintain surface quality in terms of chemical and particulate contamination. They are then put in contact.
- the surface quality of The components are such that molecular adhesion is established between them thanks to the so-called van der Waals attractive forces which occur at distances of less than a few nanometers. This bonding is performed using equipment that can ensure alignment between the two components before contacting with the aid of alignment patterns specific to direct bonding.
- the bonding operation can be described as the "direct bonding" detection and reading component.
- one or more pressure points are exerted on one or the other of the components in order to initiate a bonding wave.
- the application of the bonding wave comprises the application of one or more localized pressure points on an area of less than a few mm 2 .
- annealing at a temperature below 300 ° C is performed for two hours, with or without a controlled atmosphere, to create covalent bonds to enhance the strength of the bonding. It will be noted again that it is important that the annealing be done at a temperature below this value to avoid the risk of diffusion of the doping species of the photodiodes 1 10 in the detector material.
- the handle substrate 300 is then thinned by grinding to leave about 50 ⁇ of this substrate, then by wet etching to the silicon oxide (SiO 2) of the encapsulation layer 230.
- the encapsulation layer 230 (SiO 2) is etched chemically and / or mechanically by grinding.
- a step of CMP makes it possible to remove the work-hardened surface by grinding until the mixed surface 194 formed, peripherally, by the SiO 2 of the encapsulation layer 230 and, in the center, by the material used, appears.
- the base substrate 100 typically indium antimonide (I nSb) or other infrared material already mentioned.
- the polished mixed surface 194 is then cleaned to leave apparent the detection material, indium antimonide, in this example.
- FIGS. 4a and 4b illustrate complementary steps of the method of the invention which are executed after the two detection and reading components have been assembled as described in the preceding figures.
- the opening 440 makes it possible to make reliable the initial assembly at the wafer scale during the annealing or cooling down steps.
- the lateral displacement of the detector substrate is facilitated by the opening 440.
- openings 430 which reveal test pads, are made peripherally to test the electrical continuity of the photodiodes as a function of temperature.
- photolithography is conventionally carried out which defines the openings 430 and then a dry etching of the silicon oxide (SiO 2) in these openings and then the removal of the previously deposited and served resin. to define the openings 430.
- the periphery 440 of the base substrate 100 containing the infrared photodiodes is disengaged so that the base substrate 100 can expand or compress during operation and during electrical temperature tests, from room temperature to 77 ° K and vice versa.
- the type of device considered by the invention is designed to operate normally at a low temperature, for example 77 ° K, which is the temperature of liquid nitrogen, in order to to reduce the background noise of the detector and thus considerably increase the detection range of the infrared radiation that can be measured.
- This release of the base substrate 100 is performed using photolithography, etching and resin removal operations similar to those described above for Figure 4a.
- the invention solves the problem set forth in the chapter on the state of the art by refining 450 sufficiently the detection component (100, 230) and releasing its periphery 440 so that it can follow without difficulty the expansion of the reading component 400.
- the latter is made of silicon, a material of which we have seen that the CTE was much lower than that of the composite semiconductor materials used for the base substrate 100 containing the photodiodes.
- the latter is for example made of one of the materials III-V, I-VI or IV-VI already mentioned.
- FIGS. 5a to 5c describe a variant of the method of manufacturing the detection component containing the infrared radiation detectors, ie the photodiodes 1, 10.
- the photodiodes 1 10 are not initially produced in the base substrate 100 but only after the step corresponding to FIG. 1d as explained hereinafter, that is to say after bonding the substrate base 100 on the handling substrate 200 and after encapsulation 230.
- the initial steps are the same and are performed under the same conditions as described in Figures 1a to 1d.
- annealing may be carried out at a higher temperature and not exceeding the melting temperature of the detector material since the doping species constituting the photodiodes have not yet been implanted.
- the photodiodes can be PN or PIN junctions and are produced by ion implantation. Their realization after encapsulation includes the following steps:
- a photolithography step of apertures 170, called vias is first performed.
- the vias can be of different diameters, for example 5 ⁇ and 8 ⁇ .
- a positive photosensitive resin with a thickness of less than 10 ⁇ is spread.
- a positive resin of 1, 5 ⁇ thick is spread.
- the conventional photolithography technique is applied.
- the patterns of the vias insolated through a mask then developed.
- the resin is then fired at about 110 ° C.
- FIG. 5a illustrates the result of the etching of the encapsulation layer 230, typically made of SiO 2.
- photolithography of vias of variable diameter for example 5 ⁇ and ⁇
- a photosensitive resin is spread.
- a conventional photolithography technique is applied.
- the patterns of openings 170 (vias) are developed and then insolated through a mask.
- the resin is then fired.
- About 1 to 3 ⁇ of the encapsulation layer 230 are etched by plasma to lead to the material constituting the base substrate 100.
- the majority of the resin is removed by plasma and then a fine cleaning is carried out. wet encapsulation layer surface 230 to remove resin residues.
- FIG. 5b illustrates the step of ion implantation of the photosensitive diodes 1 10 where the openings 170 have been made.
- ion implantation of positive ions is performed if the material constituting the base substrate 100 is N-doped as shown. If the material is doped with P type, negative ions will be implanted. In both cases a PN junction is formed.
- doping elements of InSb it is possible to use for example cadmium (Cd), tin (Sn) and tellurium (Te).
- FIG. 5c illustrates the result of the photolithography and etching steps in the oxide of the layer 230 of the zones 160 called "dummies" described previously and after removal of the resin. Photolithography of the resin, etching and cleaning are identical to what has been described previously.
- FIGS. 6a to 6f describe another variant of the method in which a receiving housing 250 for the base substrate 1 00 is produced in the handling substrate 200.
- the assembly thus formed then makes it possible to reconstitute a wafer, typically a diameter of 200 mm, which then becomes compatible with the standard of current production lines of integrated circuits, in particular those of the CMOS technology.
- a base substrate 100 made of a semiconductor semiconductor material as described in FIG. 1a is used.
- This variant of the method is also identical to that described in Figures 5a to 5c, that is to say that the photodiodes are manufactured only after the base substrate 100 has been assembled on a handling substrate 200.
- the base substrate 100 is prepared under the same conditions as those already described. In particular, an oxide layer 140 is created at the surface for bonding.
- a reception housing 250 is prepared in the handling substrate 200 in order to receive the base substrate 1 00 in which the radiation detection photodiodes i n red.
- the accommodating housing 250 is typically comprised between 2 inches and 200 mm to a depth of about 15 micrometers. This housing is created either by mechanical machining, or by dry etching in a plasma, or The size of the docking housing is defined according to the size of the base substrate 100.
- the handling substrate 200 also has all the characteristics described in FIG. 1 b.
- the surface state obtained and the means for obtaining this surface state are those already described in order to allow direct bonding of the two substrates as shown in FIG. 6c.
- the following step consists, as already described in FIG. 1 d, in thinning the base substrate 100 to bring it down to a working thickness 150 less than or equal to 15 ⁇ .
- the base substrate 100 is then at the same level as the handling substrate 200.
- the base substrate 100 has a free face opposite a face by which it is fixed to the handling substrate 200.
- the handling substrate 200 comprises a receiving face intended to receive the base substrate 100. This receiving face defines a plane outside the receiving housing 250. After its thinning, the free face of the base substrate 100 is contained in this plan. The base substrate 100 therefore does not protrude beyond the receiving face of the handling substrate 200.
- the thinned base substrate 100 is then encapsulated, typically in a layer of silicon oxide 230, under the same conditions as previously described in FIG. 1 d. The result of this operation is illustrated in Figure 6e.
- the encapsulation layer 230 is then in turn thinned and flattened using all the techniques of grinding, chemical mechanical polishing and cleaning already described. As shown in FIG. 6f, a thickness 241 of the encapsulation layer 230, for example approximately 1 ⁇ , is left above the thinned base substrate 100.
- the assembly formed by the handling substrate 200 and the detection component 100, 230 forms a plate having two opposite planar faces. It is therefore easy to manipulate. At this point the result corresponds to what was obtained in Figure 1 d.
- the variant of the process previously described in FIGS. 5a to 5c is then applied to finally obtain an assembly between the base substrate 100 containing the infrared radiation detectors and that containing the reading circuits 400.
- FIGS. 7a to 7c show that the method also applies in the case where there are several basic substrates 100 smaller size infrared radiation detectors that will be assembled on the same handling substrate 200 to adapt it in the format of the production line in which they are to be processed.
- the individual substrates 100 may come from different technologies and be of different sizes.
- the materials that compose them can be different composite semiconductor materials.
- the assembly operations are the same as those described above. Any of the process variants described may apply.
- the photodiodes may have been manufactured before assembly or after as described in the variant of the method illustrated in FIGS. 5a to 5c.
- FIG. 7a shows the example of three individual basic substrates 100 whose semiconductor materials are different and which are assembled together on the same handling substrate 200.
- the photodiodes have already been manufactured in the base substrates 100.
- the method which applies is that described in FIGS. 1 a to 1 i.
- the base substrates 100 will be assembled by direct bonding on the handling substrate 200. Then, after thinning of the base substrates 100, their encapsulation is carried out 230 as shown in FIG. 7d.
- the base substrates 100 may each be a detection chip that has been cut from a plate on which it was manufactured before assembly on the handling substrate.
- connecting faces Preparation of the connecting faces by a CMP adapted to reduce the roughness.
- These connecting faces have either only SiOx or SiOx and copper inlay areas.
- this bringing into contact is carried out at ambient temperature.
- this contacting is performed without exerting an overall pressure force.
- a localized pressure is preferably applied at one or more points.
- the localized pressure is applied to a surface, typically less than a few mm 2 , for example a few tens or hundreds of ⁇ 2 , of one of the components, so as to generate a bonding wave in the Van der Waals sense.
- thermal annealing is preferably carried out. This annealing is performed at a temperature below 300 ° C to not degrade the photodiodes.
- the method of the invention makes it possible to assemble not only two components together but also several basic substrates comprising infrared photodiodes on the same handling substrate, or even individual chips cut from one or more detection substrates.
- the advantage being that in this case only assay chips which have been tested and which are deemed to be completely functional are assembled, which makes it possible to increase the manufacturing efficiency of the infrared radiation detectors manufactured according to the method of the invention. 'invention.
- the hybrid bonding technology by direct bonding of the invention eliminates the steps related to indium metallurgy currently used. This removes: indium deposits; the stages of recasting; soldering fluxes; the flatness defects that frequently appear on the components (lack of uniformity); the stages of cleaning the flux residues; the coating steps generating unreliability due to the inclusion of bubbles confined in the interconnection zone and excess glue to be removed (eg coating beads); hybridization problems due to differences in the expansion of the substrates; reliability defects due to gold-indium (Au-In) intermetallics.
- the coating material used can not play its full role because it can not be crosslinked to the temperature that gives it its thermomechanical consistency. Indeed, in order to save the photodiodes and to accommodate the significant differences between the coefficients of thermal expansion (CTE) of heterogeneous substrates, this crosslinking is at a temperature which is 40 ° C below the manufacturer's recommendation.
- the invention makes it possible to overcome this problem.
- the progress made today in the field of intra-connections can accommodate even smaller pixel steps that become less than or equal to 15 ⁇ .
- the method of the invention which can potentially benefit from all the technological advances of the silicon microelectronics sector unlike current hybridization techniques, can easily adapt to this decrease in the pitch of pixel repetition.
- Hybridization based on the use of indium beads on the contrary reaches its limits, in particular because of the flatness defects it entails.
- the cleaning and coating of components having steps less than 15 ⁇ becomes extremely difficult if not impossible as soon as the component size exceeds a few square centimeters.
- the matrices of large sizes are therefore extremely difficult to achieve with the industry based on the use of indium balls matrices.
- the volume of indium decreases with the decrease of the pitch, making the hybridization very difficult because the recovery of the lack of flatness of the components is no longer possible.
- a major contribution of the invention is the use of processes that fully benefit from the constant development of microelectronics with a gain in terms of shortened cycle times, improved performance and reliability of the assembly, which offers both technical advantages. and economic.
- the technique of the invention is independent of the nature of the radiation detector substrate provided that the maximum temperature allowed by the photodiodes is respected.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Materials Engineering (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1201324A FR2990565B1 (fr) | 2012-05-09 | 2012-05-09 | Procede de realisation de detecteurs infrarouges |
PCT/EP2013/059421 WO2013167553A1 (fr) | 2012-05-09 | 2013-05-06 | Procédé de réalisation de détecteurs infrarouges |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2847796A1 true EP2847796A1 (fr) | 2015-03-18 |
Family
ID=46940514
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP13721698.2A Withdrawn EP2847796A1 (fr) | 2012-05-09 | 2013-05-06 | Procédé de réalisation de détecteurs infrarouges |
Country Status (4)
Country | Link |
---|---|
US (1) | US9318527B2 (fr) |
EP (1) | EP2847796A1 (fr) |
FR (1) | FR2990565B1 (fr) |
WO (1) | WO2013167553A1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10571631B2 (en) | 2015-01-05 | 2020-02-25 | The Research Foundation For The State University Of New York | Integrated photonics including waveguiding material |
US10020343B2 (en) * | 2015-09-25 | 2018-07-10 | Flir Systems, Inc. | Wafer-level back-end fabrication systems and methods |
TWI597390B (zh) * | 2015-11-10 | 2017-09-01 | Jx Nippon Mining & Metals Corp | Electrolytic copper foil, manufacturing method of electrolytic copper foil, copper clad laminated board, printed wiring board, the manufacturing method of a printed wiring board, and the manufacturing method of an electronic device |
DE102015121066B4 (de) | 2015-12-03 | 2021-10-28 | Infineon Technologies Ag | Halbleitersubstrat-auf-halbleitersubstrat-package und verfahren zu seiner herstellung |
US10978508B2 (en) | 2018-10-16 | 2021-04-13 | L3 Cincinnati Electronics Corporation | Infrared detector having a directly bonded silicon substrate present on top thereof |
CN114220783A (zh) * | 2021-12-21 | 2022-03-22 | 中国科学院深圳先进技术研究院 | 一种混合键合结构及其制备方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5455202A (en) * | 1993-01-19 | 1995-10-03 | Hughes Aircraft Company | Method of making a microelectric device using an alternate substrate |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
FR2781925B1 (fr) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
US20030113947A1 (en) | 2001-12-19 | 2003-06-19 | Vandentop Gilroy J. | Electrical/optical integration scheme using direct copper bonding |
US6962835B2 (en) | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
JP4046067B2 (ja) | 2003-11-04 | 2008-02-13 | ソニー株式会社 | 固体撮像素子の製造方法 |
FR2876244B1 (fr) | 2004-10-04 | 2007-01-26 | Commissariat Energie Atomique | Composant muni d'un ensemble de micropointes conductrices dures et procede de connexion electrique entre ce composant et un composant muni de protuberances conductrices ductiles |
FR2938973B1 (fr) | 2008-11-27 | 2011-03-04 | Sagem Defense Securite | Cellules matricielles photosensibles dans l'infrarouge a base d'antimoniure sur substrat optiquement transparent et procede de fabrication associe |
JP4835710B2 (ja) * | 2009-03-17 | 2011-12-14 | ソニー株式会社 | 固体撮像装置、固体撮像装置の製造方法、固体撮像装置の駆動方法、及び電子機器 |
US7820525B2 (en) * | 2009-03-25 | 2010-10-26 | E-Phocus | Method for manufacturing hybrid image sensors |
FR2947481B1 (fr) * | 2009-07-03 | 2011-08-26 | Commissariat Energie Atomique | Procede de collage cuivre-cuivre simplifie |
US8772717B2 (en) | 2009-08-10 | 2014-07-08 | Drs Rsta, Inc. | Radiation detector having a bandgap engineered absorber |
FR2949903A1 (fr) | 2009-09-07 | 2011-03-11 | Soc Fr Detecteurs Infrarouges Sofradir | Procede d'hybridation de composants electroniques, notamment de detection |
FR2963158B1 (fr) * | 2010-07-21 | 2013-05-17 | Commissariat Energie Atomique | Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques |
-
2012
- 2012-05-09 FR FR1201324A patent/FR2990565B1/fr not_active Expired - Fee Related
-
2013
- 2013-05-06 EP EP13721698.2A patent/EP2847796A1/fr not_active Withdrawn
- 2013-05-06 US US14/399,824 patent/US9318527B2/en not_active Expired - Fee Related
- 2013-05-06 WO PCT/EP2013/059421 patent/WO2013167553A1/fr active Application Filing
Non-Patent Citations (2)
Title |
---|
None * |
See also references of WO2013167553A1 * |
Also Published As
Publication number | Publication date |
---|---|
US9318527B2 (en) | 2016-04-19 |
US20150102447A1 (en) | 2015-04-16 |
WO2013167553A1 (fr) | 2013-11-14 |
FR2990565A1 (fr) | 2013-11-15 |
FR2990565B1 (fr) | 2016-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2863420B1 (fr) | Procédé amélioré d'assemblage par collage direct entre deux éléments, chaque élément comprenant des portions de métal et de matériaux diélectriques | |
WO2013167553A1 (fr) | Procédé de réalisation de détecteurs infrarouges | |
EP1923912B1 (fr) | Procédé de fabrication d'une structure microtechnologique mixte | |
FR2986904A1 (fr) | Systeme d'assemblage de puces | |
FR2992473A1 (fr) | Procede de fabrication de structures de led ou de cellules solaires | |
FR2810448A1 (fr) | Procede de fabrication de substrats et substrats obtenus par ce procede | |
FR2910707A1 (fr) | Capteur d'image a haute densite d'integration | |
EP2162907A1 (fr) | Dispositif comportant des composants integres encastres dans des cavites d ' une plaquette semi-conductrice d ' accueil et procede correspondant | |
EP2840589B1 (fr) | Procédé améliore de séparation entre une zone activé d'un substrat et sa face arrière ou une portion de sa face arrière | |
WO2021099713A1 (fr) | Procede de fabrication d'une puce fonctionnelle adaptee pour etre assemblee a des elements filaires | |
EP1774588B1 (fr) | Assemblage par adhesion moleculaire de deux substrats | |
WO2007006914A1 (fr) | Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure | |
FR2983638A1 (fr) | Procede de formation d'un circuit integre | |
FR2938973A1 (fr) | Cellules matricielles photosensibles dans l'infrarouge a base d'antimoniure sur substrat optiquement transparent et procede de fabrication associe | |
FR2990297A1 (fr) | Empilement de structures semi-conductrices et procede de fabrication correspondant | |
WO2017051004A1 (fr) | Procédé de fabrication de structures pour cellule photovoltaïque | |
FR3064398B1 (fr) | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure | |
EP3568868A1 (fr) | Substrat pour capteur d'image de type face avant et procédé de fabrication d'un tel substrat | |
FR3120737A1 (fr) | Procede de fabrication d’une structure semi-conductrice a base de carbure de silicium et structure composite intermediaire | |
EP2962325B1 (fr) | Procédé d'obtention d'une surface de collage pour collage direct et structure correspondante | |
WO2024133682A1 (fr) | Substrat comprenant des tranchées et procédés de fabrication associés | |
WO2024115528A1 (fr) | Dispositif optoélectronique et son procédé de fabrication | |
EP4128330A1 (fr) | Procede de fabrication d'une structure empilee | |
EP4264659A1 (fr) | Procede de fabrication d'une structure semi-conductrice comprenant une zone d'interface incluant des agglomerats | |
FR3142038A1 (fr) | Procédé de fabrication d’un dispositif électronique |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20141204 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAX | Request for extension of the european patent (deleted) | ||
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 27/146 20060101AFI20190516BHEP Ipc: H01L 23/00 20060101ALI20190516BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 27/146 20060101AFI20190523BHEP Ipc: H01L 21/48 20060101ALI20190523BHEP Ipc: H01L 21/60 20060101ALI20190523BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20190717 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20191203 |