EP2717316B1 - Verfahren zur Herstellung verspannter Germanium-Lamellenstrukturen - Google Patents

Verfahren zur Herstellung verspannter Germanium-Lamellenstrukturen Download PDF

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EP2717316B1
EP2717316B1 EP12187332.7A EP12187332A EP2717316B1 EP 2717316 B1 EP2717316 B1 EP 2717316B1 EP 12187332 A EP12187332 A EP 12187332A EP 2717316 B1 EP2717316 B1 EP 2717316B1
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Prior art keywords
areas
trenches
structures
substrate
fin
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French (fr)
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EP2717316A1 (de
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Benjamin Vincent
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Priority to JP2013174538A priority patent/JP6204749B2/ja
Priority to US14/047,950 priority patent/US9263528B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention is related to the production of fin-shaped structures comprising strained Ge on a SiGe buffer, mainly for use as quantum well digital logic transistors.
  • a known technique for depositing a SiGe layer in a narrow trench is referred to as Aspect Ratio Trapping (ART). This technique allows filling of narrow trenches, e.g. obtained by STI (Shallow Trench Isolation) on a silicon substrate, with a SiGe layer that does not show defects in the top part of the trenches.
  • STI Shallow Trench Isolation
  • the document US20070221956 discloses a method for forming germanium-rich fins using oxidation of SiGe fins.
  • the SiGe fins are formed by patterning an SiGe layer and the underlying graded SiGe buffer.
  • the invention is related to a method as disclosed in the appended claims.
  • the method of the invention provides a way of producing fin-structures comprising strained Ge on a SiGe buffer of less than 20nm in width, without the above-described limitation on the size of the fins.
  • the present invention is related to a method for producing one or more semiconductor fin structures, in particular fins comprising a SiGe buffer portion and a strained Ge top portion.
  • the strained Ge portion is formed by a step of oxidizing SiGe structures extending outwards from an insulation surface, said insulation surface being preferably formed by the top surface of STI oxide regions produced in a Si substrate.
  • the SiGe structures may be grown in the Si substrate by Aspect Ratio Trapping, thereby obtaining a SiGe structure that is relaxed and essentially defect free in a top region.
  • the oxidation step results in the formation of a Ge region and a SiO 2 layer covering the fin.
  • the oxidation is continued until a pure strained Ge top portion is obtained on the SiGe base of the fins.
  • the process can involve the oxidation of separate SiGe structures formed by overgrowth of SiGe into separate mushroom-shaped overgrowth portions.
  • the SiGe structures are formed after a CMP step and the step of etching the oxide regions in between the structures.
  • the SiGe structures are obtained by patterning a SiGe layer that is sufficiently thick so as to obtain relaxed and defect free SiGe in a top sublayer of said SiGe layer.
  • the invention is thus in particular related to a method for producing one or more semiconductor fin structures comprising the steps of :
  • said oxidation and condensation continue until substantially none of the second material remains in the top portion of the fins, whilst the first material in said top portion remains in a strained condition.
  • the step of producing said one or more elongate structures comprises the steps of :
  • the step of producing said one or more elongate structures comprises the steps of :
  • the step of producing said one or more elongate structures comprises the steps of :
  • Said two different semiconductor materials are silicon and germanium, wherein said compound material is SiGe, said base portion is a SiGe portion and said top portion is a strained Ge portion.
  • SiGe is defined as Si x Ge 1-x , with x higher than 0.2.
  • Said substrate may be a silicon substrate.
  • the method of the invention may further comprise the step of depositing a cap layer formed of silicon on said one or more relaxed and defect free fin-shaped structures consisting of said alloy material, before subjecting said structures to said oxidation step.
  • Figures 1a to 1f illustrate a first embodiment of the method according to the invention.
  • standard STI Shallow Trench Isolation
  • SiGe silicon germanium
  • x any suitable value known in the art for this type of alloy.
  • the width and depth of the trenches 4 is such that aspect ratio trapping (ART) takes place, i.e. dislocations 6 become trapped by the sidewalls of the trenches 4.
  • the result is a set of elongate SiGe structures 7, consisting of a base area 8 and a mushroom-shaped overgrowth area 9.
  • the depth and aspect ratio of the trenches 4 is such that in said mushroom-shaped area 9 and in an upper portion 8' of the base area 8, relaxed and defect free SiGe is formed.
  • a further etching step removes a portion of the STI oxide, resulting in part of the elongate SiGe structures 7 extending outwards with respect to oxide surface 10 (see figure 1d ).
  • the mushroom-shaped portion 9 itself is the part that is extending outwards with respect to the oxide surface 14 (see figure 1c ). This structure is then subjected to a dry oxidation at high temperature, transforming the structures 7 into :
  • the Ge top portion 17 is obtained by condensation of the Ge from the SiGe simultaneously with the oxidation of the Si.
  • the oxidation step (hereafter also referred to as condensation/oxidation step) continues until the top portion 17 of the fins consists of substantially pure strained Ge, i.e. until no silicon is left in the top portion, whilst ensuring that the formed Ge is in a strained condition.
  • the condensed volume is kept below the critical volume of plastic relaxation. This critical volume depends on the lattice mismatch between Ge and the initial relaxed SiGe, so mainly on the initial Ge concentration.
  • the silicon oxide layer 18 is removed above the level 10 of the STI regions, by a suitable etching step, resulting in a set of fins 15 having a Ge top portion 17 of defect free strained Ge on a buffer of SiGe (the buffer being the base portion 16).
  • silicon oxide formed in the oxidation step remains, i.e. in the preferred case where the regions 3 are also silicon oxide, the fins are embedded in a continuous oxide layer.
  • a small over-etching may occur of the STI regions 3 during removal of the oxide 18, i.e. material removed from surface 10.
  • the flanks of the base portions 16 may comprise a zone (not shown) of pure Ge or SiGe with higher Ge content, as Ge condensation may take place also in these regions.
  • the fins 15 are suitable for producing quantum well FinFET transistors by applying further process steps as known in the art.
  • the width of the top portions 17 can be lower than 20nm.
  • the size of this top portion 17 can be designed by adequate choices in terms of the SiGe composition (value of x in Si x Ge 1-x ), the size of the overgrowth areas 9, the size of the trenches 4, taking into account the critical volume as stated above. Sufficient freedom is possible in the choice of these parameters to allow the production of very narrow fin structures starting from trenches 4 that are wide enough to ensure that no twin formation takes place during filling of the trench.
  • the invention thus provides a solution for the above described problem : size reduction of the fins is possible without requiring trenches 4 that are too narrow to avoid twin formation in the upper part of the trench.
  • the overgrowth of the SiGe is continued until a contiguous layer 20 of relaxed and defect free SiGe is obtained on top of the STI-substrate.
  • the depth and aspect ratio of the trenches 4 is such that relaxed and defect free SiGe is obtained in the overgrowth area 20 and in an upper area 8' of the SiGe deposited in the trenches 4.
  • CMP chemical-mechanical-polishing step
  • An etch step follows to recess the STI oxide regions and form SiGe structures 7, a part of which is extending outwards from the STI surface 10. This structure is then subjected to the oxidation step as described above, again leading to the formation of :
  • the strained Ge fins 15 are obtained, with remaining oxide areas 19 at the sides.
  • a thin silicon cap layer is deposited (not shown), preferably by epitaxial growth, on top of the elongate structures 7, before performing the oxidation step.
  • the purpose of this cap layer is to avoid oxidation of Germanium.
  • the Si-cap forms a silicon oxide layer which will obstruct formation of germanium oxide, and ensure that all of the Ge moves to the center portion 17 by condensation.
  • the oxidation of the cap may take place at a lower temperature than the oxidation of the SiGe.
  • diffusion anneal steps can be combined with condensation/oxidation steps in a cyclic process, in order to enhance the interdiffusion of the semiconductor elements in the alloy Si and Ge).
  • a condensation/oxidation and anneal cycles is to be regarded as an embodiment of the 'oxidation step' referred to in the claims.
  • the structures 7 that are partly extending outwards with respect to the insulation areas 3 are obtained in another way than in the embodiments of figures 1 and 2 .
  • a layer of SiGe is grown on a substrate, e.g. a Silicon substrate.
  • the layer is grown at a sufficiently high thickness for un upper sublayer of the SiGe to be in a relaxed condition, and defect free.
  • the thickness is sufficient so that dislocations caused by a mismatch between the SiGe and the underlying substrate do not propagate into said upper portion.
  • the SiGe layer is few microns thick, preferably with a Ge gradient in order to bend dislocations defects forming in this way a graded strain relaxed buffer.
  • a patterning and etching step is performed to produce trenches in the SiGe layer, whereafter said trenches are filled with an insulating material, for example silicon oxide. Possibly after a planarization step, this results in the same structure as the one shown in figure 2d , i.e. elongate areas of SiGe in between oxide areas 3, wherein a top portion 8' of the SiGe is relaxed and defect free.
  • an insulating material for example silicon oxide
  • the description of a layer being deposited or produced 'on' another layer or substrate includes the options of

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Claims (7)

  1. Verfahren zur Herstellung einer oder mehrerer Halbleiterlamellenstrukturen (15), umfassend die Schritte zum:
    • Herstellen einer oder mehrerer länglicher Strukturen (7) auf einem Substrat, wobei die Strukturen aus einer Legierung aus Silizium und Germanium bestehen, ein Teil der Strukturen sich in Bezug auf die Oberfläche (10, 14) einer Isolierungsschicht, die auf dem Substrat vorliegt, nach außen erstreckt, ein Deckabschnitt (8',9) der Strukturen aus entspanntem und defektfreiem Legierungsmaterial besteht,
    • Unterziehen der Struktur(en) (7) einem Oxidationsschritt, um die Struktur(en) umzuwandeln zu:
    • einer oder mehreren Lamellen (15), die einen Basisabschnitt (16) umfassen, der aus der Legierung gebildet ist, und einen Deckabschnitt (17), der aus Germanium in einem verspannten Zustand gebildet ist, wobei der Deckabschnitt durch Kondensation von Germanium gebildet wird,
    • eine Schicht aus Siliziumoxid (18), die die Lamelle(n) (15) abdeckt, wobei die Oxidschicht (18) durch Oxidation des Siliziums gebildet wird,
    • Entfernen des Teils der Schicht (18) von Siliziumoxid, die sich über der Oberfläche (10, 14) der Isolierungsschicht erstreckt, um dadurch die eine oder mehreren Lamellenstrukturen (15), die einen Deckabschnitt (17) von Germanium in verspanntem Zustand umfasst, auf einem Basisabschnitt (16) des Legierungsmaterials herzustellen.
  2. Verfahren nach Anspruch 1, wobei der Schritt zur Herstellung der einen oder mehreren länglichen Strukturen (7) die Schritte umfasst zum:
    • Bereitstellen oder Herstellen eines Substrats (1) mit einem oder mehreren lamellenförmigen Bereichen (2) auf der Oberfläche, mit Isolierungsbereichen (3), die die Räume zwischen den lamellenförmigen Bereichen füllen,
    • Entfernen von Substratmaterial von den lamellenförmigen Bereichen (2), wodurch Gräben (4) zwischen den Isolierungsbereichen (3) erzeugt werden,
    • Züchten der Silizium- und Germaniumlegierung in den Gräben (4) durch eine Technik, die "Aspect Ratio Trapping" von Verlagerungen in den Gräben erlaubt, wodurch entspanntes und defektfreies Legierungsmetall in einem oberen Abschnitt (8') der Gräben erhalten wird, wie auch in einem pilzförmigen Abschnitt (9), der die Oberkanten von jedem der Gräben (4) überspannt,
    • optional, Entfernen eines Deckabschnitts der Isolierungsbereiche (3), was dazu führt, dass sich der pilzförmige Abschnitt (9) und optional mindestens Teil des entspannten und defektfreien oberen Abschnitts (8') in Bezug auf die Oberfläche (14, 10) der Isolierungsbereiche (3) oder des Rests der Isolierungsbereiche (3) nach außen erstrecken.
  3. Verfahren nach Anspruch 1, wobei der Schritt zum Herstellen der einen oder mehreren länglichen Strukturen (7) die Schritte umfasst zum:
    • Bereitstellen oder Herstellen eines Substrats (1) mit einem oder mehreren lamellenförmigen Bereichen (2) auf der Oberfläche, mit Isolierungsbereichen (3), die die Räume zwischen den lamellenförmigen Bereichen füllen,
    • Entfernen von Substratmaterial von den lamellenförmigen Bereichen (2), wodurch Gräben (4) zwischen den Isolierungsbereichen (3) gebildet werden,
    • Züchten der Silizium- und Germaniumlegierung in den Gräben durch eine Technik, die "Aspect Ratio Trapping" von Verlagerungen in den Gräben erlaubt, wodurch entspanntes und im Wesentlichen defektfreies Legierungsmaterial in einem oberen Abschnitt (8') der Gräben erhalten wird, wie auch in einem angrenzenden Bereich (20), der die oberen Ränder der Gräben überlagert,
    • Ebnen des Substrats mindestens bis zur höchsten Ebene (14) der Isolierungsbereiche (3),
    • Entfernen eines Deckabschnitts der Isolierungsbereiche (3), was darin resultiert, dass mindestens Teil des oberen entspannten und defektfreien Abschnitts (8') sich in Bezug auf die Oberfläche (10) des Rests der Isolierungsbereiche (3) nach außen erstreckt.
  4. Verfahren nach Anspruch 1, wobei der Schritt zur Herstellung der einen oder mehreren länglichen Strukturen (7) die Schritte umfasst zum:
    • Herstellen einer Schicht der Legierung auf einem Substrat, wobei die Schicht ausreichend dick ist, sodass sie einen oberen Bereich umfasst, der in einem entspannten und defektfreien Zustand ist,
    • Ätzen einer Vielzahl an Gräben in die Schicht,
    • Füllen der Gräben mit einem Isolierungsmaterial, optional gefolgt von einem Ebnungsschritt, um dadurch ein Substrat mit einem oder mehreren länglichen Bereichen der Legierung auf der Oberfläche zu erhalten, mit Isolierungsbereichen (3), die die Räume zwischen den länglichen Bereichen füllen, wodurch entspanntes und im Wesentlichen defektfreies Legierungsmaterial in einem oberen Abschnitt (8') der länglichen Bereiche erhalten wird,
    • Entfernen eines Deckabschnitts der Isolierungsbereiche (3), was darin resultiert, dass mindestens Teil des oberen entspannten und defektfreien Abschnitts (8'), sich in Bezug auf die Oberfläche (10) des Rests der Isolierungsbereiche (3) nach außen erstreckt.
  5. Verfahren nach Anspruch 4, wobei die Silizium- und Germaniumlegierung als SixGe1-x definiert ist, mit x höher als 0,2.
  6. Verfahren nach einem der Ansprüche 1 bis 5, wobei das Substrat ein Siliziumsubstrat ist.
  7. Verfahren nach einem der Ansprüche 1 bis 6, weiter umfassend den Schritt zum Abscheiden einer Abdeckschicht, die aus dem zweiten Halbleitermaterial gebildet wird, auf der einen oder den mehreren entspannten und defektfreien lamellenförmigen Strukturen (7), die aus dem Legierungsmaterial bestehen, bevor die Strukturen dem Oxidationsschritt unterzogen werden.
EP12187332.7A 2012-10-05 2012-10-05 Verfahren zur Herstellung verspannter Germanium-Lamellenstrukturen Active EP2717316B1 (de)

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EP12187332.7A EP2717316B1 (de) 2012-10-05 2012-10-05 Verfahren zur Herstellung verspannter Germanium-Lamellenstrukturen
JP2013174538A JP6204749B2 (ja) 2012-10-05 2013-08-26 歪みＧｅフィン構造の製造方法
US14/047,950 US9263528B2 (en) 2012-10-05 2013-10-07 Method for producing strained Ge fin structures

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US9263528B2 (en) 2016-02-16
EP2717316A1 (de) 2014-04-09
JP6204749B2 (ja) 2017-09-27
JP2014096565A (ja) 2014-05-22
US20140099774A1 (en) 2014-04-10

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