EP2582050A1 - Mehrstufen-Sigma-Delta-Analog-zu-Digital-Wandler mit reduzierten Quantifizierungsstufen - Google Patents

Mehrstufen-Sigma-Delta-Analog-zu-Digital-Wandler mit reduzierten Quantifizierungsstufen Download PDF

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Publication number
EP2582050A1
EP2582050A1 EP11185107.7A EP11185107A EP2582050A1 EP 2582050 A1 EP2582050 A1 EP 2582050A1 EP 11185107 A EP11185107 A EP 11185107A EP 2582050 A1 EP2582050 A1 EP 2582050A1
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EP
European Patent Office
Prior art keywords
converter
analog
block
analog signal
direct path
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Application number
EP11185107.7A
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English (en)
French (fr)
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EP2582050B1 (de
Inventor
Carlo Pinna
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OCT Circuit Technologies International Ltd
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ST Ericsson SA
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Priority to EP11185107.7A priority Critical patent/EP2582050B1/de
Priority to PCT/EP2012/069818 priority patent/WO2013053659A1/en
Priority to US14/351,059 priority patent/US8890735B2/en
Priority to CN201280050525.5A priority patent/CN103875184B/zh
Publication of EP2582050A1 publication Critical patent/EP2582050A1/de
Application granted granted Critical
Publication of EP2582050B1 publication Critical patent/EP2582050B1/de
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Definitions

  • the present invention relates to Analog-to-Digital Converter circuits (ADCs) and particularly to a multi-level sigma-delta ADC with reduced quantization levels.
  • ADCs Analog-to-Digital Converter circuits
  • ADCs Analog-to-Digital Converter circuits
  • this topology of converters transforms an analog input signal to a digital stream of words with a low number of bits and a spectrally-shaped quantization noise.
  • the first Sigma-Delta converters had a single bit output (2 levels), then they evolved to multi-level outputs thanks to the usage of new design techniques.
  • the multi-level solution has the advantage of reducing the quantization noise at the cost of an increased complexity of the ADCs.
  • Figure 1 shows a multi-level second-order sigma-delta converter 100 of the prior art in which the shown quantizer 101 is L-levels.
  • the converter 100 of figure 1 is arranged to convert an input analog signal X into a stream of digital words Y.
  • the converter 100 includes a direct path d1 having a first analog integrator 102 and a second analog integrator 103 connected in series one another upstream the quantizer 101.
  • the converter 100 further comprises a feedback path f1 arranged to subtract an analog signal corresponding the digital output signal Y from the input of the first analog converter 102 and the second analog converter 103, respectively.
  • the quantizer must not introduce substantial delay in the direct path because the delay can cause instability, so the preferred solution to implement the quantizer is to do a flash-converter with a number of comparators equal to the output levels minus one (in this example L-1 comparators).
  • An object of the present invention is to provide a multi-level sigma-delta AD converter with reduced quantization levels which is alternative to the ones of the cited prior art overcoming at least some of their drawbacks and limitations and reducing the quantizer accuracy needed.
  • a multi-level sigma-delta AD converter comprises a direct path having an input terminal to receive an input analog signal and an output terminal to provide a output digital signal corresponding to said input analog signal.
  • the direct path comprises a computation block arranged to receive a first analog signal representative of the input analog signal and to provide a analog computed signal, an analog integrator having an input terminal operatively associated to the computation block to receive the analog computed signal and a output terminal to provide a third analog signal, a quantizer having a respective input terminal operatively connected to the output terminal of the analog integrator and a respective output terminal operatively connected to the output terminal of the direct path.
  • the converter comprises a first feedback path arranged to provide to the computation block a feedback analog signal representative of a digital signal present at the output terminal of the quantizer.
  • the computation block is arranged to subtract said feedback analog signal from the first analog signal.
  • the first feedback path comprises an amplification block having a respective gain factor.
  • the direct path comprises a first amplification block interposed between said computational block and the input terminal of the quantizer.
  • the first amplification block of the direct path has a respective gain factor which is the inverse of the gain factor of the amplification block of the first feedback path.
  • An embodiment of the invention is a digital audio device comprising a multi-level sigma-delta AD converter.
  • Block diagram of a preferred embodiment of a multi-level sigma-delta Analog-to-Digital (AD) converter of the invention can be described with reference to figure 2 .
  • a digital audio device (described in the following with reference to figure 4 ) comprises the multi-level sigma-delta AD converter according to the invention.
  • the digital audio device can be used in any portable equipments with audio signals, e.g. mobile or cellular phone, MP3 players, PDAs (Personal Digital Assistant), portable computers, tablets, and so on.
  • portable equipments e.g. mobile or cellular phone, MP3 players, PDAs (Personal Digital Assistant), portable computers, tablets, and so on.
  • the multi-level sigma-delta AD converter 200 in the following also simply converter 200, comprises a direct path d1 having an input terminal Id1 to receive an input analog signal X and an output terminal Od1 to provide an output digital signal Y corresponding to the input analog signal X.
  • the output digital signal Y is a digital stream of words with a number of bits depending on the number of levels of the converter 200.
  • the output digital signal Y is a digital stream of words with 5 bits.
  • the direct path d1 of the converter 200 comprises a computation block S2, e.g. an adder, arranged to receive a first analog signal X1 representative of the input analog signal X and to provide an analog computed signal X2.
  • a computation block S2 e.g. an adder, arranged to receive a first analog signal X1 representative of the input analog signal X and to provide an analog computed signal X2.
  • the direct path d1 of the converter 200 comprises an analog integrator 2, e.g. a first order analog integrator, having an input terminal 12 operatively associated to the computation block S2 to receive the analog computed signal X2 and an output terminal 02 to provide a third analog signal X3.
  • an analog integrator e.g. a first order analog integrator
  • the analog integrator 2 comprises a respective direct path comprising an adder block and delay block connected in series one another.
  • the adder block has an input terminal corresponding to the input terminal 12 of the analog integrator 2 and an output terminal connected to the input terminal of the delay block.
  • the delay block has an output terminal corresponding to the output terminal 02 of the analog integrator 2.
  • the analog integrator further comprises a respective feedback path to provide to a further input terminal of the adder block the third analog signal X3 present at the output terminal 02 of the analog integrator 2.
  • the direct path d1 of the converter 200 further comprises a quantizer 3 having a respective input terminal 13 operatively connected to the output terminal 02 of the analog integrator 2 and a respective output terminal 03 operatively connected to the output terminal Od1 of the direct path d1.
  • the portion of the direct path d1 of the converter 200 before the quantizer 3 is in the analog domain and the portion of the direct path d1 of the converter 200 after the quantizer 3 is in the digital domain.
  • the quantizer 3 has a reduced number of quantization levels, e.g. 8 quantization levels, depending on the architecture of the converter 100 according to the invention, as it will be explained in the following.
  • quantizer 3 is a flash converter having a number of comparators equal to r-1.
  • the converter 200 advantageously comprises a first feedback path f1 arranged to provide to the computation block S2 a feedback analog signal AN1 representative of a digital signal DS present at the output terminal 03 of the quantizer 3.
  • computation block S2 is arranged to subtract said feedback analog signal AN1 from the first analog signal X1.
  • the computation block S2 is preferably configured to change from positive to negative the sign of the feedback analog signal AN1 received from the first feedback path f1 of the converter 200.
  • the first feedback path f1 of the converter 200 comprises an amplification block A0 having a respective gain factor 1/K2.
  • the first feedback path f1 further comprises a Digital-to-Analog (DA) converter DA1, e.g. a flash DA converter, interposed between the output terminal 03 of the quantizer 3 and the amplification block A0.
  • DA Digital-to-Analog
  • the direct path d1 comprises a first amplification block A2 interposed between the computational block S2 and the input terminal 13 of the quantizer 3.
  • the first amplification block A2 of the direct path d1 has a respective gain factor K2 which is the inverse of the gain factor 1/K2 of the amplification block A0 of the first feedback path f1.
  • the first amplification block A2 of the direct path d1 is interposed between the computation block S2 and the analog integrator 2.
  • the first amplification block A2 of the direct path d1 is interposed between the analog integrator 2 and the quantizer 3.
  • the converter 200 of figure 2 further comprises a second feedback path f2 arranged to provide to the computation block S2 a further feedback analog signal AN2 representative of the output digital signal Y present at the output terminal Od1 of the direct path d1.
  • the computation block S2 is advantageously arranged to subtract said further feedback analog signal AN2 from the first analog signal X1.
  • the computation block S2 is preferably configured to change from positive to negative the sign of the further feedback analog signal AN2 received from the second feedback path f2 of the converter 200.
  • the second feedback path f2 further comprises a further Digital-to-Analog (DA) converter DA2, e.g. a flash DA converter, interposed between the output terminal Od1 of the direct path d1 of the converter 200 and the computational block S2.
  • DA Digital-to-Analog
  • the direct path d1 comprises a further analog integrator 1, e.g. a first order analog integrator, having an input terminal I1 operatively connected to the input terminal Id1 of the direct path d1 and a output terminal 01 operatively connected to the computation block S2 to provide it the first analog signal X representative of the input analog signal X of the direct path d1.
  • a further analog integrator e.g. a first order analog integrator
  • the internal structure of the further analog integrator 1 is analogous to the internal structure of the analog integrator 2, previously described.
  • the direct path d1 of the converter 200 further comprises a further computation block S1, e.g. an adder, arranged to receive the input analog signal X and to provide a further analog computed signal X4 to the further analog integrator 1.
  • a further computation block S1 e.g. an adder
  • the second feedback path f2 of the converter 200 is further arranged to provide the feedback analog signal AN2 to the further computation block S1.
  • the further computation block S1 is arranged to subtract the further feedback analog signal AN2 from the first analog signal X1.
  • the further computation block S1 is preferably configured to change from positive to negative the sign of the further feedback analog signal AN2 received from second feedback path f2 of the converter 200.
  • the direct path d1 further comprises a second amplification block A1 interposed between the further computation block S1 and the computation block S2.
  • the second amplification block A1 has a respective gain factor K1.
  • the second amplification block A1 of the direct path d1 is interposed between the further computation block S1 and the further analog integrator 1.
  • the second amplification block A1 of the direct path d1 is interposed between the further analog integrator 1 and the computation block S2.
  • the direct path d1 further comprises a digital integrator block 4, e.g. a first order digital integrator, interposed between the output terminal 03 of the quantizer 3 and the output terminal Od1 of the converter 200.
  • a digital integrator block 4 e.g. a first order digital integrator
  • the digital integrator block 4 is arranged to receive the digital signal DS present at the output terminal 03 of the quantizer 3 and to provide the corresponding output digital signal Y on the output terminal Od1 of the direct branch d1 and on the second feedback path f2 of the converter 200.
  • the digital integrator block 4 comprises a respective direct path comprising an adder block.
  • the adder block has an input terminal corresponding to the input terminal of the digital integrator block 4 and an output terminal corresponding to the output terminal of the digital integrator block 4.
  • the output terminal of the adder of the digital integrator block 4 is also connected to the second feedback path f2, particularly to the input terminal of the further digital-to-analog converter DA2.
  • the digital integrator block 4 further comprises a respective feedback path comprising a delay block arranged to provide to a further input terminal of the adder block the output digital signal Y present at the output terminal Od1 of the digital integrator 4.
  • Block diagram of a further embodiment of a multi-level sigma-delta Analog-to-Digital (AD) converter of the invention can be described now with reference to figure 3 .
  • the multi-level sigma-delta Analog-to Digital (AD) converter of figure 3 in the following also simply converter, is indicated by the reference number 300.
  • the converter 300 comprises a direct path d1 having an input terminal Id1 to receive an input analog signal X and an output terminal Od1 to provide an output digital signal Y corresponding to the input analog signal X.
  • the output digital signal Y is a digital stream of words with a number of bits depending on the number of levels of the converter 300 (in the case of a 32-level sigma-delta AD converter, the output digital signal Y is a digital stream of words with 5 bits).
  • the direct path d1 of the converter 300 comprises a computation block S2 and an analog integrator 2 analogous the ones described with reference to the converter 200 of figure 2 .
  • the direct path d1 of the converter 300 further comprises a quantizer 3' having a respective input terminal 13' operatively connected to the output terminal 02 of the analog integrator 2 and a respective output terminal 03' operatively connected to the output terminal Od1 of the direct path d1.
  • the portion of the direct path d1 of the converter 300 before the quantizer 3' is in the analog domain and the portion of the direct path d1 of the converter 300 after the quantizer 3 is in the digital domain.
  • the quantizer 3' has a reduced number of quantization levels, e.g. 8 quantization levels, depending on the architecture of the converter 100 according to the invention.
  • An example of quantizer 3' is a flash converter having a number of comparators equal to r-1.
  • the quantizer 3 of the converter 200 of figure 2 has an accuracy more relaxed than the accuracy of the quantizer 3.
  • the accuracy of the quantizer depends on the thresholds of the comparators, which can be generated in many ways related to the implementation of the converter.
  • the difference between the quantizer 3 of the embodiment of fig. 2 and the quantizer 3' of the embodiment of fig. 3 is the positioning of the thresholds of the comparators. It should be noted that this does not involve a change in the complexity in putting them at different values.
  • the converter 300 comprises a first feedback path f1 arranged to provide to the computation block S2 a feedback analog signal AN1 representative of a digital signal DS present at the output terminal 03' of the quantizer 3'.
  • the computation block S2 is arranged to subtract said feedback analog signal AN1 from the first analog signal X1.
  • the computation block S2 is preferably configured to change from positive to negative the sign of the feedback analog signal AN1 received from the first feedback path f1 of the converter 200.
  • the first feedback path f1 of the converter 300 comprises an amplification block A0' having a respective gain factor 1/4K2.
  • the first feedback path f1 further comprises a Digital-to-Analog (DA) converter DA1 analogous to the DA converter described with reference to the converter 200 of figure 2 , interposed between the output terminal 03' of the quantizer 3' and the amplification block A0'.
  • DA Digital-to-Analog
  • the direct path d1 comprises a first amplification block A2' interposed between the computational block S2 and the input terminal 13' of the quantizer 3'.
  • the first amplification block A2' of the direct path d1 has a respective gain factor 4K2 which is the inverse of the gain factor 1/4K2 of the amplification block A0' of the first feedback path f1.
  • the first amplification block A2' of the direct path d1 can be interposed between the computation block S2 and the analog integrator 2 or between the analog integrator 2 and the quantizer 3'.
  • the output terminal 02 of the analog integrator 2 is connected to the input terminal 13 of the quantizer 3 and its amplitude is reduced with respect to the solution of the prior art.
  • the gain factor of the first amplification block from K2 to 4K2 and advantageously reducing the accuracy needed for the quantizer 3, and then obtaining the further embodiment of the invention, i.e. the converter 300 of figure 3 .
  • the gain factor of the amplification block A2' of the first feedback path f1 is reduced from 1/k2 to 1/4k2.
  • the relaxed accuracy of the quantizer 3' is related to the relaxed accuracy of the comparators used in the quantizer because in a flash converter the tolerated comparator error is generally indicated as a fraction of the least significant bit (LSB, which is the difference between two subsequent thresholds). In the case the LSB increases, the tolerated error increase.
  • LSB least significant bit
  • the LSB of the quantizer 3' is multiplied by four and therefore the tolerated comparator error of the quantizer 3' is multiplied by four (or, vice-versa, the accuracy of the quantizer 3' is reduced by four), while at the same time the accuracy of the converter 300 remains unchanged.
  • the solution of figure 3 advantageously allows to save cost than the solution of figure 2 maintaining the same performance of the converter.
  • the converter 300 of figure 3 further comprises a second feedback path f2 arranged to provide to the computation block S2 a further feedback analog signal AN2 representative of the output digital signal Y present at the output terminal Od1 of the direct path d1.
  • the computation block S2 is advantageously arranged to subtract said further feedback analog signal AN2 from the first analog signal X1, as previously described.
  • the second feedback path f2 of the converter 300 further comprises a further Digital-to-Analog (DA) converter DA2, analogous to the one described with reference to the converter 200 of figure 2 .
  • DA Digital-to-Analog
  • the direct path d1 comprises a further analog integrator 1 which is analogous to the further analog integrator previously described with reference to the embodiment of fig. 2 .
  • the direct path d1 of the converter 300 further comprises a further computation block S1, e.g. an adder, analogous to the one described with reference to the converter 200 of figure 2 .
  • a further computation block S1 e.g. an adder
  • the second feedback path f2 of the converter 300 is further arranged to provide the feedback analog signal AN2 to the further computation block S1.
  • the further computation block S1 is arranged to subtract the further feedback analog signal AN2 from the first analog signal X1, as previously described.
  • the direct path d1 further comprises a second amplification block A1 interposed between the further computation block S1 and the computation block S2.
  • the second amplification block A1 has a respective gain factor K1.
  • the second amplification block A1 of the direct path d1 can be interposed between the further computation block S1 and the further analog integrator 1 or between the further analog integrator 1 and the computation block S2.
  • the direct path d1 further comprises a digital integrator block 4, e.g. a first order digital integrator, interposed between the output terminal 03' of the quantizer 3' and the output terminal Od1 of the converter 300.
  • a digital integrator block 4 e.g. a first order digital integrator
  • the digital integrator block 4 of the converter 300 is arranged to receive the digital signal DS present at the output terminal 03' of the quantizer 3' and to provide the corresponding output digital signal Y on the output terminal Od1 of the direct branch d1 and on the second feedback path f2 of the converter 300.
  • the input analog signal X of the multi-level sigma-delta AD converter 200 is band limited when used in audio signals.
  • the inventor used this correlation to predict the next digital sample subtracting the predict digital sample present at the output of the quantizer 3 before the quantizer 3 so that the quantizer itself can be configured with a reduced number of quantization levels to work properly.
  • the quantizer 3 introduced an error Err so that the third analog signal X3 at the input terminal 13 of the quantizer 3 has amplitude Y-Err.
  • the previous output digital sample Y (N-1) (digital output signal DS present at the output terminal 03 of the quantizer) is converted in the analog domain by the DA converter DA1 and then subtracted from the first analog signal X1 by the computation block S2.
  • the first term depends on the input analog signal X and on its transfer function.
  • the second term depends on the output quantization noise.
  • the first term can be small if the transfer function f is a low pass filter or if the input analog signal X is band limited, as in the case of audio signals.
  • the input analog signal is filtered externally or by its transfer function f and therefore the first term can be small.
  • the second term is the difference between two successive quantization noises, so it can be assumed that the amplitude of ⁇ Q is roughly 2Q.
  • Err 2 ⁇ Err ⁇ 0 / L wherein Err0 is the quantization error of 2 levels quantizer.
  • the amplitude signal is mainly dependent on the input analog signal X.
  • the same quantizer 3 having 8 quantization levels can be used also in the case of a multi-level sigma-delta AD converter having 64 levels output.
  • the digital audio device 400 is for example a mobile telephone.
  • Such digital audio device 400 comprises a digital audio recorder chain 401 and a digital audio player chain 411.
  • the other electronic components of the mobile telephone 400 operatively connected to both the audio chains, are not illustrated in the figure 4 .
  • the digital audio recorder chain 401 comprises a microphone 402.
  • Such digital audio recorder chain 401 further comprises a microphone pre-amplifier 403.
  • the digital audio recorder chain 401 comprises an Analog-to-Digital Converter 200 (or 300) of the type described above with reference to any of the embodiments of the invention ( figures 2-3 ).
  • the digital audio recorder chain 401 further comprises a digital filter 404.
  • the digital audio player chain 411 comprises:
  • the multi-level sigma-delta AD converter of the invention has the advantage that the quantizer complexity does not change with the increase of the number of output levels of the converter, as explained above.
  • the accuracy and complexity of the quantizer 3 is relaxed respect to the other multi-level sigma-delta DA converter already known because its output digital signal (converted in the corresponding analog signal) is injected in the second stage of the multi-level sigma-delta AD converter (computation block S2, first amplification block A2 and analog integrator 2 of the direct path d1 of both the converter 200 and the converter 300).
  • the converter of the invention has an alternative arrangement which is more simple because it comprises analog integrator of the first order.
  • first amplification block (A1) in the direct path d1 of the converter having a gain factor which is the inverse of the gain factor of the amplification block (A2) present in the first feedback path f1 allows to substantially obtain the cancellation of the amplitude introduced by the first feedback path f1 in the direct path d1, i.e. in the third analog signal X3 present at the input terminal 13 of the quantizer 3.
  • the embodiment of figure 3 allows employing a quantizer 3' having a reduced accuracy than the quantizer of the embodiment of figure 2 by (simply) increasing of a preset value (e.g. 4) the gain factor of the first amplification block A2' of the direct path d1 and reducing of the same preset value the gain factor of the amplification block A0' present in the first feedback path f1.
  • a preset value e.g. 4
  • the gain factor of the first amplification block A2' of the direct path d1 reducing of the same preset value the gain factor of the amplification block A0' present in the first feedback path f1.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
EP11185107.7A 2011-10-13 2011-10-13 Mehrstufen-Sigma-Delta-Analog-zu-Digital-Wandler mit reduzierten Quantifizierungsstufen Not-in-force EP2582050B1 (de)

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Application Number Priority Date Filing Date Title
EP11185107.7A EP2582050B1 (de) 2011-10-13 2011-10-13 Mehrstufen-Sigma-Delta-Analog-zu-Digital-Wandler mit reduzierten Quantifizierungsstufen
PCT/EP2012/069818 WO2013053659A1 (en) 2011-10-13 2012-10-08 Multi-level sigma-delta adc with reduced quantization levels.
US14/351,059 US8890735B2 (en) 2011-10-13 2012-10-08 Multi-level sigma-delta ADC with reduced quantization levels
CN201280050525.5A CN103875184B (zh) 2011-10-13 2012-10-08 具有减少的量化级的多级σ‑δ模数转换器

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EP11185107.7A EP2582050B1 (de) 2011-10-13 2011-10-13 Mehrstufen-Sigma-Delta-Analog-zu-Digital-Wandler mit reduzierten Quantifizierungsstufen

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EP2582050B1 EP2582050B1 (de) 2017-08-09

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US10075181B2 (en) 2015-06-10 2018-09-11 Mediatek Inc. ΔΣ modulator with excess loop delay compensation
US9634687B2 (en) * 2015-06-10 2017-04-25 Mediatek Inc. VCO-based continuous-time sigma delta modulator equipped with truncation circuit and phase-domain excess loop delay compensation
EP4040682A1 (de) * 2021-02-05 2022-08-10 Imec VZW Analog-digital-wandlerschaltung, integrierte schaltvorrichtung, photoplethysmogrammdetektor, wearable-vorrichtung und verfahren zur analog-digital-wandlung

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EP2582050B1 (de) 2017-08-09
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CN103875184A (zh) 2014-06-18
US8890735B2 (en) 2014-11-18

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