EP2513957A2 - Procédé de fabrication d'un module électronique, ainsi que module électronique - Google Patents

Procédé de fabrication d'un module électronique, ainsi que module électronique

Info

Publication number
EP2513957A2
EP2513957A2 EP10792842A EP10792842A EP2513957A2 EP 2513957 A2 EP2513957 A2 EP 2513957A2 EP 10792842 A EP10792842 A EP 10792842A EP 10792842 A EP10792842 A EP 10792842A EP 2513957 A2 EP2513957 A2 EP 2513957A2
Authority
EP
European Patent Office
Prior art keywords
layer
conductive layer
bumps
component
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10792842A
Other languages
German (de)
English (en)
Inventor
Andreas Ostmann
Manessis Dionysios
Lars BÖTTCHER
Stefan Karaszkiewicz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Technische Universitaet Berlin
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Technische Universitaet Berlin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV, Technische Universitaet Berlin filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP2513957A2 publication Critical patent/EP2513957A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper

Definitions

  • the invention relates to a process for preparing an electronic assembly, wherein at least 'one electronic component in an insulating material is at least partially embedded, and an electronic assembly prepared by the method.
  • a method for embedding electronic components is described in which the electronic component is placed on a foil arrangement of conductive layer and carrier foil by means of an adhesive layer and is surrounded by an insulating mass.
  • the carrier layer is removed and holes are drilled from the side of the conductive layer to connect to the bumps or pads of the at least one electronic component. Subsequently, the conductive layer with a
  • An essential feature of the known methods is that it is always necessary to drill a hole from the surface to the chip contacts or contacts of the electronic component. This is associated with a number of disadvantages. This makes it necessary to geometrically bring three elements into a coincident position (chip contact via and trace). Furthermore, the size of holes to the components to be embedded process-related set a lower limit, whereby the smallest achievable contact grid is limited. Finally, the galvanic filling of the hole with metal, generally copper, limits the realizable aspect ratio, ie holes with a small diameter must also have a correspondingly small depth, which in turn meets the requirements for the control of
  • the invention has for its object to provide a method for producing an electronic assembly that is suitable for small contact grid of the components to be embedded and process steps simplified.
  • Trace width lie. It is sufficient if only part of the track is in line with the bump. No vias need to be created, eliminating the associated constraints and reducing overall process costs. By eliminating the vias also reduces the thickness of the structure.
  • a conductive layer is provided as the starting material, which may be formed as a film and which may also be referred to as a film arrangement.
  • This conductive layer preferably of copper, is with
  • openings which are deep-etched as blind holes etched into the layer or structured.
  • the starting material is the film arrangement of two layers, the conductive layer and the carrier layer, preferably of different materials, ie instead of a homogeneous, for example copper foil, a thin film is used on a carrier, the carrier layer being made of polymer ceramic or else a metal, such as aluminum is formed.
  • the openings are made such that they pass through holes as holes through the conductive layer, wherein the film assembly is provided in their entirety from the side of the conductive layer with the holes, for example, depth-controlled etched or
  • the removal of a portion of the conductive layer or the carrier layer in both cases can be done by etching, wherein on the opposite side of the dielectric layer depth controlled etched to expose the bumps in the holes of the conductive film.
  • the carrier layer can also, in particular if it consists of polymer or ceramic components, be deducted.
  • the metallization layer is deposited on the conductive layer and the exposed bumps using the same material as the conductive layer, resulting in a uniform metal layer that makes excellent contact with the bumps.
  • the bumps are advantageously made of copper or copper with a tin layer, or else of nickel and palladium (Ni / Pd) or of gold, but a similarly contactable metallization or alloy can be used.
  • the bumps can be protected by means of an etch-resistant layer which is removed before the application of the metallization layer. This has the advantage that when removing the carrier layer or a part of the conductive layer, the bumps are not damaged.
  • the blind holes in the conductive capable of producing a layer having a depth less than the height of the bumps or the thickness of the conductive layer of the film assembly is less than the height of the bumps, thereby improving the subsequent contacting with the metallization layer.
  • the openings in the conductive layer can be used as alignment marks, so that a positionally accurate arrangement is possible without additional borrowed structures.
  • each opening can each accommodate a bump or an opening or a hole can each be formed so that a plurality of bumps can be recorded. This can happen when the bump distance becomes very small, for example, bumps can be formed as frames along the chip periphery.
  • Fig. 1 shows a sequence of the method steps for
  • Fig. 2 shows a sequence of Maschinenmatschr te for producing an assembly according to the invention according to another embodiment.
  • Fig. Lh an embodiment of the electronic assembly according to the invention is shown schematically, wherein the electronic module 1, the electronic in the Heinrichsverfah- as bumps 3 formed contacts, a
  • the starting point is a film arrangement which is provided according to FIG. 1a, this film arrangement being a copper foil 7 in the exemplary embodiment.
  • the copper foil 7 is structured in this way, i. depth-controlled structures that formed as blind holes openings 8 are formed (Fig. 1b).
  • Fig. 1b On the structured copper foil is at least in the
  • An adhesive layer 5 is applied in the region of the attachment to the component 2, and the component 2, which has been provided on its contact surfaces with the metal bumps or bumps 3 beforehand, is moved with the front side or top side downwards into or into the Adhesive layer 5 and placed on the copper foil 7, such that the bumps 3 engage in the openings or blind holes 8, which simultaneously serve to adjust the component 2 on the copper foil 7.
  • the arrangement according to FIG. 1d is distinguished from the side of the component 2 facing away from the contacts with a dielectric layer 4
  • the dielectric layer is e.g. a thin plate called prepreg, which is laid up. The assembly is then in a conventional in the printed circuit board vacuum lamination
  • the prepreg is e.g. made of fiberglass reinforced epoxy resin.
  • the dielectric layer may also be otherwise formed, e.g. be produced by means of a potting compound.
  • the copper foil 7 is etched so far deep controlled that the surface of the bumps 3 is exposed, wherein a conductive
  • Layer 7 'persists. If the bumps 3 were provided with an etching-resistant layer for their protection beforehand, this layer is removed or the entire surface of the conductive layer 7 'and that of the bumps 3 are cleaned, so that possible residues on both the bump surface and on the bump surface
  • a copper layer is deposited on the exposed surface 7 ', whereby, together with the conductive layer, a copper layer is deposited
  • Layer 7 results in a common thicker metallization layer 6 '.
  • This metallization layer 6 ' is structured such that the desired conductor tracks 6 are formed, which overlap with the bumps 3 for their contacting.
  • Fig. 2a to h is another embodiment in which, instead of the homogeneous copper foil 7, a thin copper foil, for example corresponding to the conductive layer 7 'according to FIG. 1f, is provided, which is connected to a carrier layer 10, for example by a thin adhesive layer.
  • the carrier film 10 may consist of a very wide variety of materials, for example as a polymer layer,
  • Steps 2c) and d) correspond to those of FIGS. 1c) and d), whereby, as in FIG. 1d, a thin adhesive layer remains between component 2 and copper foil. If, for example, the carrier layer
  • etching step (Fig. Le) is replaced by the peeling.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un module électronique, dans lequel au moins un composant électronique est encapsulé au moins partiellement dans un matériau isolant, comprenant les étapes suivantes consistant à : mettre en place un agencement de feuilles comprenant au moins une couche conductrice et une couche porteuse, ou bien uniquement une couche conductrice ; structurer la couche conductrice de manière à ménager des ouvertures en forme de trous borgnes ou de trous traversants pour recevoir des bossages qui sont conectés aux surfaces de contact dudit au moins un composant électronique ; appliquer une couche adhésive sur la couche conductrice dotée des ouvertures ; installer ledit au moins un composant sur l'agencement de feuilles ou dans la couche conductrice de manière que les bossages (3) s'engagent dans les ouvertures de la couche conductrice ; encapsuler partiellement ledit au moins un composant dans une couche de diélectrique par le côté opposé aux bossages (3) ; éliminer la couche porteuse de l'agencement de feuilles ou une partie de la couche conductrice de manière à dégager la surface des bossages ; déposer une couche de métallisation sur le côté de la couche conductrice résiduelle avec les bossages dégagés ; structurer la couche de métallisation et la couche conductrice afin de réaliser des pistes conductrices qui se superposent aux bossages. L'invention concerne en outre un module électronique fabriqué à l'aide d'un tel procédé.
EP10792842A 2009-12-15 2010-12-14 Procédé de fabrication d'un module électronique, ainsi que module électronique Withdrawn EP2513957A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009058764A DE102009058764A1 (de) 2009-12-15 2009-12-15 Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe
PCT/EP2010/007628 WO2011082778A2 (fr) 2009-12-15 2010-12-14 Procédé de fabrication d'un module électronique, ainsi que module électronique

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EP2513957A2 true EP2513957A2 (fr) 2012-10-24

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EP (1) EP2513957A2 (fr)
DE (1) DE102009058764A1 (fr)
WO (1) WO2011082778A2 (fr)

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DE102014210483A1 (de) 2014-06-03 2015-12-03 Conti Temic Microelectronic Gmbh Verfahren zum Herstellen einer Folienanordnung und entsprechende Folienanordnung
RU2597210C1 (ru) * 2015-05-28 2016-09-10 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ изготовления микроэлектронного узла на пластичном основании
US10373856B2 (en) * 2015-08-03 2019-08-06 Mikro Mesa Technology Co., Ltd. Transfer head array
JP6693441B2 (ja) * 2017-02-27 2020-05-13 オムロン株式会社 電子装置およびその製造方法
RU2752013C1 (ru) * 2020-10-26 2021-07-21 Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный электротехнический университет "ЛЭТИ" им. В.И. Ульянова (Ленина) Способ изготовления микросборки бескорпусных электронных компонентов на гибких органических подложках

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US8975116B2 (en) 2015-03-10
WO2011082778A3 (fr) 2011-09-15
WO2011082778A2 (fr) 2011-07-14
DE102009058764A1 (de) 2011-06-16
US20130015572A1 (en) 2013-01-17

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