WO2018069319A1 - Procédé de fabrication d'une carte de circuit imprimé multicouche - Google Patents

Procédé de fabrication d'une carte de circuit imprimé multicouche Download PDF

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Publication number
WO2018069319A1
WO2018069319A1 PCT/EP2017/075812 EP2017075812W WO2018069319A1 WO 2018069319 A1 WO2018069319 A1 WO 2018069319A1 EP 2017075812 W EP2017075812 W EP 2017075812W WO 2018069319 A1 WO2018069319 A1 WO 2018069319A1
Authority
WO
WIPO (PCT)
Prior art keywords
printed circuit
layer
circuit board
contact points
contact
Prior art date
Application number
PCT/EP2017/075812
Other languages
German (de)
English (en)
Inventor
Angelika Schingale
Markus Ochs
Karsten Meier
Mike Röllig
Original Assignee
Continental Automotive Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Automotive Gmbh filed Critical Continental Automotive Gmbh
Publication of WO2018069319A1 publication Critical patent/WO2018069319A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

Definitions

  • Printed circuit boards are carriers for electronic components. They serve the mechanical attachment and connection of the electronic components.
  • a circuit board is made of electrically insulating material with conductive connections adhering thereto, the tracks. Fiber-reinforced plastic is common as insulating material.
  • the tracks are usually etched from a thin layer of copper.
  • the components are soldered to solder pads, the so-called contact pads, or in pads.
  • PCB types There are a variety of different PCB types. For example, one-sided and two-sided printed circuit boards are known in which electrically conductive connections are applied either only on one surface or on the two opposite surfaces of the printed circuit boards.
  • multilayer printed circuit boards or multi-layer printed circuit boards are arranged in multiple layers both on and inside the circuit board. To produce several thin circuit boards are glued to each other with so-called prepregs. These multilayer printed circuit boards can have up to 48 layers. In the field of automotive applications 4 to 8 layers are common. Connections of the connecting layers between the individual layers are by means of so-called
  • the copper layers can be galvanically reinforced after etching in order to achieve the desired layer thickness.
  • metallic protective and contact layers made of tin, nickel or gold can be applied galvanically on partial surfaces or the entire copper surface. Then a solder mask is applied, which covers the tracks and leaves only the solder joints.
  • multilayer printed circuit boards is also associated with a variety of wet chemical processes. For example, after the pressing of a multilayer layer structure into the outer material layer (s) introduced holes are filled by wet-chemical processes, so as to establish a contact individual conductor or connecting layers. As part of a wet chemical process usually copper is deposited in a galvanic. In addition to high demands on process safety, a wet-chemical process is also associated with many ecological aspects. In these acids, alkalis, toxic chemicals are used. Partly the disposal of hazardous waste is required.
  • DE 694 31 740 T2 discloses the production of a multilayer wiring board in which, according to FIGS. 7 and 8, a plurality of printed circuit board layers are pressed together, wherein contact points of the printed circuit board layers are connected to plated-through holes.
  • the pads are provided with connection pads or bumps, both of which are multilayer coated using electrolytic nickel plating and electrolytic gold plating. Layering and in the case of the connection bumps with additional electrolytic tin plating and electrolytic gold plating are produced in sequence. These are very complicated wet chemical processes.
  • the object is achieved by a method for producing a multilayer printed circuit board in which the individual printed circuit ⁇ tenlagen are provided with metallic conductor structures having contact points, which have a uniform thickness of at least 5ym over the PCB surface, and at least a first printed circuit board layer holes metallized with Has walls which are in electrical contact with the contact points of the metallic conductor structure or form such a contact point, in which
  • a structured pre-preg position is applied to the first printed circuit board layer, leaving the contact points of the metallic conductor structures free,
  • the metal of the contact points is remelted at a temperature above its melting temperature.
  • the connections between the printed circuit board layers and possibly their bores for the production of plated-through holes in the printed circuit board are produced by the direct contact of the contact points of the printed circuit board layers.
  • the metal of the contact points is remelted by pressure and heat during pressing, so that the contact points of different circuit board layers connect by forming intermetallic boundary layers, without further material would be necessary.
  • step e) the stack is heated up to a temperature above the
  • step g) Melting temperature of the metal of the contact points heated and this remelted, wherein the step g) is omitted.
  • the holes are filled with a material from the group of materials solder, adhesive, polymer or sintered material after step e) in a step e x ) and this then remelted or cured.
  • the holes can be completely filled.
  • FIGS. 1 to 8 show the individual steps of a first variant of the method according to the invention
  • FIGS. 9 to 11 show a first alternative to the steps of FIG
  • FIGS. 12 and 13 show a second alternative to the steps of FIGS.
  • FIGS. 14 and 15 show a third alternative to the steps of FIGS.
  • a first variant of the method according to the invention for producing a multilayer printed circuit board with plated-through holes is shown in a schematic manner.
  • the dimensions of the individual components are not measured ⁇ scale, but should only illustrate the procedure.
  • the first printed circuit board layer 3 which is cleaned, etched and dried before laying, has in a conventional manner conductor track structures and contact surfaces and holes 5 with metallized walls.
  • the edges of the bore wall metallization lying on the printed circuit board outer side and further regions to be connected to other printed circuit board layers are formed as contact points 4 with a minimum thickness of 5ym, so that the two contact points 4 of two adjacent circuit board layers 3, 7 to be joined together have a total thickness of have at least 10ym.
  • the contact points are released 4 on the first printed circuit board layer 3, the prepreg 1 is applied to the first patterned conductor ⁇ board layer 3 of FIG. 3, so that in particular through the holes 2.
  • a second structured printed circuit board layer 7 is positioned on the prepreg layer 1. This stack construction is processed in a subsequent pressing step according to FIGS. 5 and 6 (with vacuum assistance).
  • a solder stop layer 8 is applied to the surfaces of the stack and optionally structured. Subsequently, as shown in FIG. 8, a remelting of the metal of the contact points 4. If, as shown in FIG. 8 worked with remelting, the
  • FIGS. 9 to 11 the process is shown when, prior to the application of the solder stop layer 8 and the remelting of the metal of the contact points 4, a filling material 9 is introduced into the bores 5.
  • the filler 9 may be a solder, an adhesive, a polymer or a sintered material, which is remelted or cured after introduction.
  • a Lotstopptik 8 is applied to the outer surfaces of the resulting circuit board, which can also be done in a known manner by lamination, spin or curtain coating as in the other variants.
  • FIGS. 14 and 15 show a third variant of the method according to the invention, which is a combination of the first and the second variant, in which the remelting of the Metal of the contact points 4 takes place during the pressing and then before applying a Lotstopp Mrs Rock ⁇ material 9 is introduced into the holes 5.
  • the invention takes advantage provided with bores, ready struc tured ⁇ as mechanically and electrically connecting printed circuit board layers (inner and outer layers) to form throughput contacts in multilayer printed circuit boards.
  • an electrical connection is created during the pressing of the aforementioned circuit board layers or in a downstream temperature process (soldering or curing) in addition to the mechanical one. It completely eliminates any form of galvanic generation of the electrical feedthroughs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une carte de circuit imprimé multicouche, les différentes couches de carte de circuit imprimé (3, 7) étant pourvues de structures conductrices métalliques (4) comportant des plages de contact (4) qui présentent une épaisseur uniforme d'au moins 5μm sur l'ensemble de la surface de la carte de circuit imprimé, et au moins une première couche de carte de circuit imprimé (3, 7) comprenant des trous (5) à parois métallisées qui sont en contact électrique avec la structure conductrice métallique ou qui forment une telle plage de contact (4), ledit procédé comprenant : a) l'application d'une couche de préimprégné structurée (1) sur une première couche de carte de circuit imprimé (3), cette couche de préimprégné laissant à découvert les structures conductrices métalliques (4) de la première couche de carte de circuit imprimé (3), b) l'application d'une seconde couche de carte de circuit imprimé (7) sur la couche de préimprégné, c) éventuellement, l'application de couches additionnelles de péimprégné et de carte de circuit imprimé sur cet empilement, d) pressage desdites au moins deux couches de circuit imprimé (3, 7) et de ladite au moins une couche de préimprégné (1), de manière que les plages de contact (4) de la première couche de carte de circuit imprimé (3) et de la seconde couche de carte de circuit imprimé (7) viennent en contact les unes avec les autres, e) pendant le pressage, le chauffage de l'empilement à une température inférieure à la température de fusion du métal des plages de contact (4), f) l'application d'une couche de réserve de soudage (8) sur chacune des couches externes de l'empilement, puis g) la refusion du métal des plages de contact (4) à une température supérieure à sa température de fusion.
PCT/EP2017/075812 2016-10-11 2017-10-10 Procédé de fabrication d'une carte de circuit imprimé multicouche WO2018069319A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016219733.9A DE102016219733A1 (de) 2016-10-11 2016-10-11 Verfahren zur Herstellung einer mehrlagigen Leiterplatte
DE102016219733.9 2016-10-11

Publications (1)

Publication Number Publication Date
WO2018069319A1 true WO2018069319A1 (fr) 2018-04-19

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ID=60080799

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2017/075812 WO2018069319A1 (fr) 2016-10-11 2017-10-10 Procédé de fabrication d'une carte de circuit imprimé multicouche

Country Status (2)

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DE (1) DE102016219733A1 (fr)
WO (1) WO2018069319A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03289195A (ja) * 1990-04-06 1991-12-19 Casio Comput Co Ltd 多層配線基板の製造方法
DE19842590A1 (de) * 1998-09-17 2000-04-13 Daimler Chrysler Ag Verfahren zur Herstellung von Schaltungsanordnungen
DE69431740T2 (de) 1993-04-21 2003-04-24 Nec Corp Mehrlagige Verdrahtungsplatine und ihre Herstellung
US20080110016A1 (en) * 2006-11-14 2008-05-15 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with solder paste connections

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03289195A (ja) * 1990-04-06 1991-12-19 Casio Comput Co Ltd 多層配線基板の製造方法
DE69431740T2 (de) 1993-04-21 2003-04-24 Nec Corp Mehrlagige Verdrahtungsplatine und ihre Herstellung
DE19842590A1 (de) * 1998-09-17 2000-04-13 Daimler Chrysler Ag Verfahren zur Herstellung von Schaltungsanordnungen
US20080110016A1 (en) * 2006-11-14 2008-05-15 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with solder paste connections

Also Published As

Publication number Publication date
DE102016219733A1 (de) 2018-04-12

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