EP2473865A1 - Procédé et dispositif pour fournir un signal de réflexion - Google Patents

Procédé et dispositif pour fournir un signal de réflexion

Info

Publication number
EP2473865A1
EP2473865A1 EP10742136A EP10742136A EP2473865A1 EP 2473865 A1 EP2473865 A1 EP 2473865A1 EP 10742136 A EP10742136 A EP 10742136A EP 10742136 A EP10742136 A EP 10742136A EP 2473865 A1 EP2473865 A1 EP 2473865A1
Authority
EP
European Patent Office
Prior art keywords
signal
clock
intermediate frequency
frequency
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10742136A
Other languages
German (de)
English (en)
Inventor
Thomas Brosche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2473865A1 publication Critical patent/EP2473865A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/466—Multiplexed conversion systems
    • H03M3/468—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters
    • H03M3/47—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters using time-division multiplexing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G01S7/288—Coherent receivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G01S13/0209—Systems with very large relative bandwidth, i.e. larger than 10 %, e.g. baseband, pulse, carrier-free, ultrawideband
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G01S7/288—Coherent receivers
    • G01S7/2886—Coherent receivers using I/Q processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/40—Arrangements for handling quadrature signals, e.g. complex modulators

Definitions

  • the present invention relates to a method for providing a
  • Reflection signal and a device for providing a
  • Radar measuring systems are used, which are based on the emission of a signal and the measurement of a signal reflected by a body. Since the emitted signals on their way to the measurement object and back from the measurement subject to a variety of types of interference, such as fading or frequency cancellation, and since it can also lead to interference reflections, it is an effort to receive received signals as clearly as possible from the interfering signals or
  • Radar signals may result in unfavorable superimposition of the reflection signals to mutual extinction of mountains and valleys of the electromagnetic wave.
  • a method of providing a reflection signal comprises receiving a received at an intermediate frequency, ie preprocessed received signal at an input, here briefly referred to as intermediate frequency signal or intermediate frequency received signal.
  • the intermediate frequency signal is received at an input of a split device, ie by a preceding analogue stage of the receiver (antenna,
  • the intermediate frequency signal has a low bandwidth compared to the intermediate frequency.
  • the transmit signal and the receive signal which may correspond, for example, to a swept ramp, may be broadband or an ultra wideband signal (UWB signal).
  • an intermediate frequency reference signal is provided at an input of first and second sampling means, which also has the intermediate frequency.
  • the intermediate frequency reference signal is like the intermediate frequency received signal at each one input of the digital signal
  • Signal preprocessing provided and can be used as a sample clock for an analog / digital converter included in the digital signal preprocessing.
  • the reference signal can be provided or received by an internal device for generating the intermediate frequency reference signal.
  • the internal device likes the intermediate frequency
  • the intermediate frequency signal is split into a first channel and a second channel.
  • the splitting device can be used. Dividing into at least two channels provides a first channel signal and a second channel signal in the respective channel.
  • the channel signals may be copies of the intermediate frequency signal.
  • the first channel signal is sampled with a first clock signal and the second channel signal is sampled with a second clock signal, wherein the second clock signal is phase shifted from the first clock signal.
  • the phase shift may be a time shift.
  • the phase shift may be plus 90 degrees in one example or minus 90 degrees in another example. In other words, that means that the phase shift can be ⁇ 90 °.
  • Both the first clock signal and the second clock signal may be derived from the intermediate frequency reference signal.
  • the intermediate frequency reference signal may be obtained by mixing a first output of a first signal generator or a first frequency generator and a second one
  • Output signal of a second signal generator can be generated.
  • the first clock signal and the second clock signal may have the substantially exact intermediate frequency, that is, the substantially exact difference frequency between two signal generators or two frequency generators. These frequency generators may generate a transmission signal or a first reference signal.
  • the received signal may have emerged from the transmitted signal and the received signal and the first reference signal in particular the intermediate frequency received signal.
  • the two sampled channel signals are matched by synchronizing the sampled second channel signal with the clock of the sampled first channel signal. This may refer to a temporal course in accordance Bring. In this way, the phase shift introduced for the sampling can be reversed again. For example, a zero order can be used to synchronize the channel signals
  • Hold (ZOH) member can be used.
  • the sampled signals have a clock that can be specified by the sampling rate.
  • the clock or the clock rate of the sampled first channel signal and the sampled second channel signal can be reduced by means of a decimation device.
  • the clock-reduced first channel signal can be provided at a first output and the clock-reduced second channel signal can be provided at a second output. This means that the method provides to work internally at a high clock rate, whereby, when using a suitable sigma-delta modulator for digitization or quantization,
  • Quantization errors, digitizing noise or quantization noise can be shifted into a frequency range in which the interference of the channel signal does not interfere substantially and can be easily filtered (noise-shaping).
  • the generated signal can be further processed with simple hardware. the, to which, because of the low clock, essentially low demands may be made.
  • the decimation device can be constructed in two stages or in several stages.
  • the synchronization of the clocks between the second channel signal and the first channel signal can be carried out by means of a zero-order hold member and / or by means of an image-frequency filter.
  • the respectively used image frequency filter can be selected as a function of the clock shift of the first clock to the second clock.
  • a sigma-delta modulator For scanning, d. H.
  • the sigma-delta modulator may also include a signal transfer function with low-pass characteristics and / or a noise transfer function with noise shaping.
  • the decimation function present in a sigma-delta ADC may also have low pass characteristics.
  • the sigma-delta ADC thus has a sigma-delta modulator and a decimation low pass.
  • a sigma-delta modulator (ZA modulator or ⁇ modulator) may quantize a signal having a word width of 1 bit or, for example, 3 bits. Because of this small word width, there may be a strong digitizing noise, but this can be substantially eliminated by means of a low-pass filter (decimation filter), in particular in conjunction with a suitable noise transfer function of the modulator (noise shaping).
  • a settling time of a signal generator can be waited for before the preprocessed signals are evaluated. Waiting for the settling time may be necessary because when passing through the ramps of the modulation signal, the setpoint can not be taken substantially immediately after switching, but may be determined by a commute around the setpoint or only approximates (aperiodically) to the setpoint.
  • the transient one can Be provided connection between a PLL and a decimation device.
  • the method may include the clock of the sampled first channel signal and / or the clock of the sampled second
  • Reduce channel signal by means of a respective first decimation or by means of a first stage of a decimation.
  • the method can wait for a settling time of a signal generator. After waiting for the settling time, a further reduction or decimation can be carried out by means of a respective second decimation device or by means of a second decimation stage of the decimation device.
  • an apparatus configured to provide a reflection signal or a reflection parameter.
  • the device comprises a splitting device, a first scanning device, a second scanning device, a synchronizing device, a first provision device, a second provision device and a decimation device.
  • the splitting device can be set up to provide or receive an intermediate frequency signal at an input, in particular an intermediate frequency received signal, and for splitting the intermediate frequency signal into a first channel and into a second channel. Consequently, the splitting device can provide a first channel signal in the first channel and a second channel signal in the second channel.
  • the Device may be constructed in the form of a Y-member, which can be provided in both channels immediately behind the splitting device, the substantially same channel signals.
  • the same signal i. the intermediate frequency received signal is sampled with two different sampling clocks and modulators to obtain the functionality of a Y-element.
  • the sampling device may be used to receive an intermediate frequency reference signal.
  • an input for the intermediate frequency reference signal is present at the sampling device.
  • the scanning device may comprise a first scanning device and a second scanning device for each channel.
  • the first sampling device is adapted to sample the first channel signal with a first clock signal
  • the second sampling device is adapted to sample the second channel signal with a second clock signal.
  • the second clock signal may be phase shifted from the first clock signal.
  • the first sampling device for sampling the channel signal may be set up with a first clock signal having the substantially exact intermediate frequency determined by mixing two PLL output signals.
  • the second sampling means may be adapted to sample the second channel signal with a second clock signal having the exact intermediate frequency determined by mixing the two PLL output signals and a phase difference from the first clock signal of either +90 ° or -90 ° .
  • a synchronizer for example in one of the two channels, is arranged to synchronize the sampled second channel signal with the clock of the sampled first channel signal.
  • the syncronizer may be an image-frequency filter that may be configured to synchronize the clock of the sampled second channel signal with the clock of the sampled first channel signal and to filter unwanted signal components.
  • An unwanted signal may be the image frequency.
  • two equally clocked signals in the two channels can be passed on to a decimation device.
  • the decimation means may be adapted to reduce the clock of the sampled first channel signal and the clock of the sampled second channel signal and, for example, at a first terminal a first clock-reduced channel signal and at a second terminal a second clock-reduced channel signal provide.
  • These two clock-reduced channel signals or I (in-phase) and Q (quadrature) signals can be made available to a further device for further processing.
  • a radar system with direct sampling of a received signal having an intermediate frequency or an intermediate frequency received signal may be realized.
  • a complex sampling, a low-pass filter and a decimation can be provided.
  • the complex sampling can be done by means of mutually time-shifted pulse combs.
  • a two-stage decimation filter can be used.
  • a first sub-filter is extended by an additional Fl R filter after the first decimation.
  • a classical sub-filter can be extended by an additional Fl R filter in a signal propagation direction after the first decimation.
  • the first stage may have a classical decimation filter or CIC filter of order K 0 and a decimation device with a decimation factor OS R, which may be extended by an additional Fl R 2 filter.
  • the CIC decimation filter of order K 0 with the decimation device may be referred to as sinc K0 filter.
  • Another notation for a sinc K0 filter may be ((sin (x) / x) K0 .
  • an additional FI R filter (FI R 2 ) may be arranged between two classical decimation filters and / or between two sinc filters.
  • the second stage may comprise a classical decimation filter of order Ki and a decimation device with a decimation factor N.
  • the complex sampling may be carried out by means of two sigma-delta modulators, which may operate essentially with exactly the intermediate frequency in the I channel and a sampling clock shifted in time with respect to the sampling clock of the I channel by either -V 4 clock or + y 4 clock ,
  • the thus shifted scanning signals may form a pulse comb.
  • a mirror frequency filter may be used.
  • An image-frequency filter may have a hold member (eg, a ZOH zero order hold member).
  • a computer-readable medium having stored thereon program code which, when executed by a processor, executes the inventive method of providing a reflection signal.
  • an FPGA Field Programmable Gate Array
  • a loadable control sequence of the FPGA as
  • the FPGA may be programmed such that when the FPGA receives corresponding input signals, the FPGA executes the inventive method for providing a reflection signal.
  • the program or structure of the FPGA may also be in an EPROM
  • an FPGA Erasable Programmable Read-Only Memory
  • an ASIC application specific integrated circuit
  • FIG. 1 shows a basic block diagram of a UWB measurement system according to an exemplary embodiment of the present invention.
  • Fig. La shows a block diagram of a measuring arrangement as a multi-port
  • FIG. 2a is a block diagram of a UWB radar heterodyne radar system in accordance with an exemplary embodiment of the present invention.
  • FIG. 2b shows a block diagram of a first frequency generator according to an exemplary embodiment of the present invention.
  • FIG. 2c shows a block diagram of a second frequency generator according to an exemplary embodiment of the present invention.
  • FIG. 3 shows a time frequency diagram of a stepped ramp according to an exemplary embodiment of the present invention.
  • FIG. 4a shows a block diagram of a dual heterodyne UWB radar system according to an exemplary embodiment of the present invention.
  • FIG. 4b shows a block diagram of a single sideband mixer according to an exemplary embodiment of the present invention.
  • 4c shows block diagrams of a classical decimation filter with a downstream additional Fl R filter according to an exemplary one
  • 5 is a block diagram of a direct heterodyne UWB direct scan radar system according to an exemplary embodiment of the present invention.
  • 6 is a diagram of pulse combs for describing the complex scan according to an exemplary embodiment of the present invention.
  • FIG. 7 is a block diagram of I / Q demodulation according to an exemplary embodiment of the present invention.
  • FIG. 8 is a block diagram of a complex sample, low pass filtering, and decimation structure of digital signal processing according to an exemplary embodiment of the present invention.
  • Ultra wide band measuring system Such a UWB measuring system 100 can be used for material analysis with the aid of electromagnetic waves, for example for
  • a UWB measurement system is a radar measurement system with a generally very high measurement bandwidth (UWB, Ultra Wide Band), which after the
  • the UWB measurement system has a transmitter 101, which couples a transmission signal generated by the transmitter 101 to the antenna 103 via a directional coupler (shown in FIG. 1 by the arrow 102).
  • the modulated radar signal (TX) generated in the transmitter is emitted via the transmitting antenna 103 in the direction of the target 104.
  • the radiated signal is shown in FIG. 1 by the waves 105.
  • the radiated electromagnetic signal 105, TX is then reflected at a target 104 which may be present in the detection field.
  • the transit time between transmitter 101, 103 and receiver is ⁇ . For example, such a goal may also be a transition between different materials.
  • the frequency response, and in particular the phase of the transmission signal 105 is determined by the reflection or by the penetration into
  • Transmission signal which can be displayed as amount and phase.
  • the course can also be in the Cartesian form (I / Q values) or the Gaussian
  • the termination 108 provides, in particular in monostatic operation, for the wave resistance-adapted termination of the transmission signal TX not coupled to the antenna 103.
  • two separate antennas 103, a transmitting antenna and a receiving antenna may be used (bistatic operation).
  • the termination 108 can be omitted in a bistatic operation. In other words, the termination 108 forms the transmitting antenna 108 in the bistatic mode.
  • a directional coupler 102 is not present in the bistatic mode.
  • the reflected signal is shown in FIG. 1 by the waves 106 running in opposite directions to the transmission direction 105, which run in the direction of the antenna 103. Via the antenna 103, the reflected signal 106 can be received again.
  • the received signal RX can be routed to the receiver 107 and further processed there.
  • the result of the further processing in the receiver 107 may be a complex-valued reflection factor or a complex-valued S-parameter.
  • the complex-valued reflection factor S results from the ratio of the received signal RX to the transmitted signal TX over the
  • Modulation Frequency f mo d or f Mo d-
  • the complex-valued reflection factor plotted against the frequency f mo d indicates the course of the scatter parameter of the radio field.
  • the reflection factor can be represented as I / Q values.
  • a step modulation signal is used whose modulation frequency profile 300 is shown in FIG. 3.
  • Magnification 301 shows a section of the course of the modulation frequency. From this magnification, it can be seen that the steps of the stepped modulation 300 can not run at right angles but at an angle due to transient processes. Transient effects can also occur during a transition
  • FIG. 3 shows a standardized transmission frequency f Mod / f max, that is to say the transmission frequency relative to a maximum frequency. Further, the normalized time
  • the frequency f max can be in the Mega Hertz, Giga Hertz or Tera Hertz range.
  • Received signal RX are represented over the frequency, in particular over the modulation frequency.
  • the result can be, for example, the course of the scattering parameter S of the radio field. It can therefore be for each
  • Measured value S (f) can be determined.
  • the UWB measuring system 100 or the radar 100 works with the stepped modulation 300 (step frequency modulation) in the frequency domain. But instead of the stepped modulation would be another
  • Modulation methods such as the transmission of a pulse or burst, the FMCW (Frequency Modulated Continuous Radar or Frequency Modulated Continuous Wave Radar) or a pseudo-random sequence (PN) can be used with a correspondingly high bandwidth.
  • Fig. 1 a monostatic operation of the UWB system 100 is shown. In monostatic operation, only a single antenna 103 is used for both transmission and reception. Several antennas can also be operated in parallel (for example in bistatic mode).
  • the portion of the transmission power that is not radiated via the antenna 103 may be degraded at the resistor 108.
  • the radar signal TX modulated in the transmitter 101 and modulated according to the stepped modulation 300 is radiated via the transmitting antenna 103.
  • the radiated electromagnetic signal is then optionally in
  • the received signal can be further processed in the receiver 107 and converted into complex-valued reflection factors.
  • a Fourier transformation in the frequency domain is possibly also carried out in a subsequent signal processing unit in order to arrive at the above-mentioned scatter parameters in the frequency domain.
  • broadband digital components such as wideband analog-to-digital converters (ADCs) or broadband amplifiers require increased manufacturing effort and can be costly to procure.
  • ADCs analog-to-digital converters
  • Ultra-wideband (UWB) radar systems can be used in a variety of ways Applications are used. In addition to communication technology, UWB systems can be used for target recognition or target tracking.
  • UWB systems can be used for target recognition or target tracking.
  • care must be taken to use as few multiplication units as possible for the signal processing. Further, when implemented as an integrated circuit, high suppression of spurious signals outside the useful band may be desirable. It may also be important to ensure the best possible compensation of I / Q errors.
  • UWB systems 100 can be implemented as homodyne systems with a single oscillator or as heterodyne systems with at least two oscillators PLL1, PLL2.
  • frequency-dependent reflection factor in the frequency domain can be realized in a double-oscillator design PLL1, PLL2.
  • the use of two high-frequency oscillators PLL1, PLL2 serves to be able to generate an intermediate frequency in the receiver. On this intermediate frequency filtering and amplification of the received signal takes place. By means of this filtering and amplification can be a high suppression of noise outside the receiver bandwidth and high sensitivity of the
  • Receiver 107 can be realized by, inter alia, the 1 / f noise is substantially suppressed, which can lead to interference in direct receivers.
  • Receive signal leads.
  • a DC offset may be due to spurious signals or internal crosstalk in the receive mixer.
  • a bandpass signal is generated, which is outside the baseband.
  • ZF (intermediate frequency) filtering for interference suppression can be performed with the ZF filter 204.
  • the reference signal 221 and the received signal RX may have the same signal components or the same frequency components f Mo d.
  • Reference signal 221 different oscillators used, which are based on the same basic clock 208, 209.
  • PLLs Phase Lock Loop
  • Both oscillators PLL1, PLL2 have a phase noise.
  • the PLLs may also be based on independent clock generators 208, 209 with an independent master clock.
  • a measuring arrangement for measuring with a four-port (4 gate) is shown. These are two UWB systems 100 arranged in parallel. A first transmission signal is emitted via the antenna 103 'and also received via antenna 103' (monostatic operation). Thus, the antenna 103 'as a transmission gate and receiving gate, so be construed as a two-port. The same applies similarly to the antenna 103 ". In bistatic operation, each gate is assigned a separate antenna.
  • the signals propagate from the second UWB system 101 ", 107".
  • the transmitters 101 ', 101 are synchronized with each other, and the receivers 107', 107" are synchronized with each other.
  • the Transmitters 101 ', 101 are synchronized with the receivers 107', 107", ie are based on the same clock signal or use the same signal source.
  • N may be any natural number
  • N 2 is a 4-port arrangement.
  • the N UWB systems can be integrated into a single device and their clock can be derived from a single clock f Q.
  • the antennas 103 ', 103 "of the 2N or 2N + M ports can be polarized differently, which can be used to achieve cross-polarization
  • Polarization is sent and received with a second, different (for example, rotated by 90 ° to each other), polarization.
  • a second, different for example, rotated by 90 ° to each other
  • Polarization is sent and received with a second, different (for example, rotated by 90 ° to each other), polarization.
  • a broadcasting channel may be in
  • a transmission gate may correspond to a receiving gate.
  • a receiving channel may correspond to a receiving gate.
  • Fig. La therefore a system with 2 transmit / receive channels or 2 channels or 4 gates is shown.
  • FIG. 1a shows a system with a first transmit (TX ') / receive channel (RX') or a first two-port 103 '(first transmit / receive second) and with a second transmit (TX ") / receive channel (RX").
  • first reception gate RX 'or the first two-port 103' (reception port / second input) is assigned to the first transmission port RX '
  • a channel 120 or path 120 may include the first transmit channel and the associated receive channel. This can be a pairwise assignment.
  • a channel 121 or path 121 may have the first transmit channel and the second receive channel (eg, in cross-polarization).
  • All transmitters and receivers in a system are synchronized with each other and are preferably based on the same clock f Q.
  • the parallel arrangement of UWB systems 100 allows execution as a multi-channel measuring system or measuring by means of a plurality of transmitting / receiving channels or channels, wherein the plurality is greater than 2 and corresponds to the number of parallel systems 100.
  • An associated method provides for providing multiple channels.
  • An N channel measurement system provides N parallel UWB systems 100.
  • Fig. 2a shows a block diagram of a simple heterodyne UWB radar system.
  • Fig. 2a shows in particular an embodiment in which the
  • Payload from a receive intermediate frequency signal 206 (substantially unfiltered and unamplified at the output of mixer M2) by sampling (direct sampling) with a sample signal 215a, 215b
  • FIG. 4a shows an exemplary embodiment in which a reception intermediate frequency signal 401 is generated by mixing with a further signal 405, having a second reference frequency f Re f2, from a first signal
  • the first reference signal 22 inter alia, by mixing the both output signals 220, 221 of the PLLs PLL1, PLL2 or the
  • Frequency generators PLL1, PLL2 generated.
  • Scanning signals 215a, 215b according to the exemplary embodiment of FIG. 2a may not lead to different transient response of the PLLs substantially to phase errors in the measurement signal.
  • the special way of generating the sampling frequency f s may mean that the sampling frequency likewise has the first intermediate frequency f Z Fi as the reception intermediate frequency signal 206.
  • FIG. 2a thus shows an apparatus for directly sampling a reception intermediate frequency signal 206.
  • the first reference signal 221, f Re fi may be generated by mixing the two output signals 220, 221 of the frequency modulators PLL1, PLL2.
  • the mixer Ml generates a signal 213 with the
  • f Z Fi fMod _ fRefi-
  • the frequency of the signal results from the filtering by means of low-pass ZFl, 212 from the frequencies fMod _ fRefi and f Mo d + fRefi generated during mixing.
  • the PLL2 receives this frequency f Z Fi as input 213 and regulates to this frequency.
  • the first reference signal 221 simultaneously serves for mixing, in particular for down-mixing, the received signal RX to the intermediate frequency f IF i. Further, the signal 213 is directed to the splitting device 214 whereby the
  • Sample clock signals 215a, 215b also have the intermediate frequency f ZF i and, in particular, the sampling clock f s with which the intermediate frequency signal
  • the intermediate frequency f ZF i contains.
  • phase noise of the oscillators PLL1 and PLL2 uniformly both in the first reference signal 221 as well as in the sampling clock f s contain, so that the phase noise picks up.
  • the transmission signal 220 or output signal 220 of the PLU may be a first one
  • Phase noise of the first oscillator PLU have. One of them initially independent second phase noise has the first reference signal 221 or output 221 of the PLL 2 .
  • the mixer signal 210 is produced, which after the low-pass filter ZF1, 212 becomes the intermediate frequency reference signal 213 or ZF reference signal 213 and which is the first intermediate frequency
  • the IF reference signal serves as a signal 213 both for controlling the PLL2 and as a base for the sampling clock f s.
  • the mixer M2 Transmitted TX signal but shifted as the transmission signal TX with the frequency f Mo d) and the first reference signal 221 in the mixer M2 after filtering 204 and amplifying 205, the intermediate frequency received signal 206 or IF received signal 206, which the first intermediate frequency and a combination phase noise from the first phase noise of the PLL1 and the second phase noise of the PLL2.
  • the output signal of the mixer M2 may also be referred to as the intermediate frequency received signal 206.
  • the IF reference signals 210, 213, 215a, 215b and the IF signal Receive signal 206 substantially similar phase noise, ie the combination phase noise, and are thus correlated, although the phase noise of the PLLs PLLi, PLL 2 is uncorrelated.
  • the combination phase noise of the IF reference signal 210, 213, 215a, 215b and the IF receive signal 206 is substantially correlated to low-delay receive signals ⁇ . Consequently, an IF receive signal 206 is sampled, each with a sample signal 215a, 215b, whose phase noise is substantially correlated with the phase noise of the IF received signal.
  • the final receive signal 206, 206 ' has the suppressed phase noise characteristics due to the structure of the receiver 107, after sampling in digital signal pre-processing 207 with fs. Since the first reference signal 221 has a frequency shifted from the transmission frequency f Mo d by f Z Fi by mixing the reference signal 221 with the
  • phase noise of the two or more frequency generators PLL1, PLL2 in the intermediate frequency signal 206 can thus be eliminated in at least two ways.
  • the intermediate frequency signal 206 can be sampled with a sampling signal 215a, 215b, in which also the first one in the same direction
  • Intermediate frequency f Z Fi is included with the combination phase noise.
  • the intermediate frequency signal 401 can be mixed with a signal 405, which has been formed from a stabilized second intermediate frequency f Z F2 and the first intermediate frequency f ZF i. This will be discussed in Fig. 4a.
  • the wide frequency range of a UWB signal may be a signal over many Distribute frequencies and thus be more reliable than a comparable narrowband signal, as the failure or interference of individual frequencies relative to the total bandwidth may not be significant in the weight.
  • the frequency used may depend on the application.
  • a 20 GHz signal may be less suitable for measuring tubes in a wall than a 1 GHz signal, because in a wall a 20 GHz signal may be subject to high attenuation.
  • a 1 GHz signal can achieve an optical resolution of 15cm.
  • a 2 GHz signal already reaches a resolution of 7.5 cm, ie objects at a distance of 7.5 cm from each other can be resolved.
  • the resolution is therefore inversely proportional to the used frequency of the PLLs.
  • a method and a device for providing a reflection signal may be provided, wherein a first reference signal 221 is generated by mixing M2 of two output signals 220, 221 from frequency generators PLL1, PLL2 and wherein the first reference signal 221 for demodulation M2 of a received signal RX serves.
  • a heterodyne radar system has two oscillators.
  • the PLL1, 200 or PLU, 200 is part of the transmission signal device 101 or the transmitter 101.
  • the offset PLL PLL2 201 or PLL 2 201 generates the
  • the simple heterodyne UWB radar system 100 comprises a first controlled high-frequency oscillator PLL1, 200 for generating the step-shaped
  • the output signal 220 of the PLL1, 200 is output via an output amplifier 202 and the transmitting / receiving switch 102 or directional coupler 102 and the low pass 203 of the antenna
  • the low-pass filter 203 serves to suppress unwanted harmonics.
  • the first high frequency oscillator PLL1, 200 is included in the transmitter 101.
  • the second controlled high-frequency oscillator PLL2, 201 is contained in the receiver 107 and generates the first reference signal f Re
  • the frequency of the reference signal f Re fi is a frequency-shifted ramp by f Z Fi relative to the frequency of the transmission signal f mo d.
  • the received signal RX which has the frequency f Mo d like the transmission signal TX, is mixed with the reference signal f Re fi in the mixer M2 and supplied to a first intermediate frequency filter 204 and an amplifier 205.
  • the received signal RX is obtained by mixing in the mixer M2 and the as
  • Bandpass or low-pass filter performed first intermediate frequency filter 204 as a received at the frequency f Z Fi received signal or as receiving intermediate frequency signal at the interface 206 of the digital
  • Receiving signal RX contains the modulation frequency f Mo d, by the performed by the mixer in the frequency domain folding of f Mo d on the
  • supported means that f IF i the intermediate frequency or carrier frequency for the
  • the digital signal preprocessing 207 at the interface 206 is directly carried at the frequency f ZF i
  • Receive signal 206 provided. It will thus be appreciated that substantially no analog (i.e., substantially analogous) implementation of the carried received signal into the baseband is performed, but that the digital signal preprocessing 207 directly accesses the carried payload RX. In the case of a direct scan, therefore, a supported signal 206 is accessed directly.
  • the frequency control in the first high-frequency oscillator PLL1, 200 is realized by means of a standard PLL circuit.
  • the high frequency signal f Mo d via a frequency divider and a
  • the Frequency divider and the phase detector of the PLLI are not shown in Fig. 2a.
  • the external quartz reference f Q is via the clock generator G, 209 in a
  • the clock signal from the clock generator 209 is also provided in parallel to the PLL2.
  • the PLL1 and the PLL2 are run or based on
  • Reference frequency f Re fi can be controlled.
  • the mixed signal ZFi may be in the MHz range, while the step-shaped modulation of the PLL1, 200 may be in the lower GHz range as a UWB signal.
  • the signal 213 After the low-pass filtering 212, the signal 213 essentially has the actual intermediate frequency f Z Fi, which may also deviate slightly from the nominal IF frequency f Z Fi, in particular when the two PLLs PLL1, PLL2 settle.
  • the frequency response represents the PLL2, in a preferential manner
  • one to the intermediate frequency f ZF i shifted ramp 300 is.
  • Frequency range after the low-pass filtering means of the low-pass filter ZFi, 212 results in a signal having only the frequency f ZF i.
  • This low pass The filtered signal is taken as the control signal for the PLL2, 201 to obtain the step function of the PLL2 shifted by the frequency f Z Fi.
  • the output function or the output frequency characteristic corresponds to the PLL1, 200 and the PLL2, 201 of the stepped ramp 300, which is controlled at the PLL1.
  • the PLL1 Since due to the internal interconnection of the PLL2, 201, the course of the signal PLL2 the PLL1 corresponds to the frequency characteristic 300 of the signal PLL1, which is only shifted by the low pass ZFi, 212 filtered shift frequency f Z Fi or intermediate frequency f Z Fi, the stepped ramp runs 300 of the PLL2 of the stepped ramp 300 of the PLL1 in the frequency range by f Z Fi for or has a correspondingly higher or lower frequency.
  • the transmit signal TX settles to the modulation frequency f mo d, which corresponds to the respective current stage of the stepped ramp 300
  • the PLL 2 generates a reference signal f Re fi with a frequency reduced or increased by f Z Fi.
  • the frequency f Z Fi thus provides an offset for the
  • Stepped ramp 300 which shifts the valid for the PLL2 step ramp 300 by the amount of offset along the frequency axis.
  • the intermediate frequency signal generated by means of the low pass ZFi, 212 is forwarded via the connection 213 to a splitting device 214.
  • the splitting device 214 divides the intermediate frequency signal having the frequency f Z Fi into two substantially phase shifted signals of either + 90 ° or -90 ° with the actual difference frequency f Z Fi or intermediate frequency f IF i.
  • the signals in the parallel channels 215a, 215b are shifted in time relative to one another by + / "90 ° or have a phase of + /" 90 ° with respect to one another.
  • the other channel 215b has a phase of + 90 ° or -90 °.
  • the signals in the parallel branches 215a, 215b have a phase shift of + / _ 90 ° to one another.
  • Intermediate frequency f Z Fi at the output 206 received signal 206 to an in-phase component I and a quadrature component Q to decompose or demodulate. Since both receive intermediate frequency signal 206 on line 206 and the first sample signal and the second sample signal in channels 215a and 215b are substantially actual
  • the digitization takes place in the digital signal preprocessing 207 with the bandpass signal 206 or at the IF level.
  • references numerals of links or interfaces may also designate a signal carried by the particular link.
  • the signal generated by the digital signal preprocessing 207 may be provided to the data processing unit 216 or the microcontroller ( ⁇ ) 216 for further processing.
  • Fig. 2b shows the structure of the PLL1.
  • the stabilized crystal frequency f Q is provided to the 1 / M1 splitter 253 and forwarded to the phase frequency detector 251.
  • the phase frequency detector (PFD) 251 also receives the transmission signal 220 fed back via the high-frequency 1 / N1 divider 254 with the transmission frequency f Mod .
  • the signal passed from node 211 to mixer M1 is not shown in Fig. 2b).
  • the time-variable ratio of the programmable integer divider coefficients Nl and Ml determines the frequency response of the PLL.
  • the coefficients can be changed in such a way that the ramp 300 shown in FIG. 3 is traversed over the course of time, ie the associated frequencies are taken over the course of time.
  • the signal is applied to the loop filter 252, which determines how fast the settling occurs during a jump between the stages fl, f2 of the ramp.
  • the generator 255 generates the transmission signal 220 at the frequency f Mod .
  • the PFD 251 receives a high-frequency signal in the GHz range.
  • the PFD 253 receives a signal of a low (in the MHz range) frequency f Q of the quartz 208.
  • the second frequency generator PLL2 is shown in FIG. 2c.
  • the 1 / N2 divider 264 receives no signal fed back from the PLL PLL2 but receives the IF signal 213 with the frequency f IF i.
  • This frequency f Z Fi is in the MHz range.
  • the first reference signal 221 has a frequency f Re fi which is a transmission frequency f Mo d shifted by the first intermediate frequency f Z Fi.
  • the 1 / M2 splitter 263 receives the stabilized quartz signal f Q , which is also in the MHz range.
  • the outputs of the dividers 263, 264 are connected to the PFD 261.
  • the divider coefficients M2 and N2 are integer and
  • the divider 264 receives the IF signal 213, it controls the IF frequency f IF i.
  • the value of the ZF1, ie the value of the shift with respect to the frequency curve 300 of the PLL1, is determined by the selection of the coefficients M2, N2.
  • the output signal of the PFD 261 reaches the Loopfilter 262 and from there to the generator 265, which determines, for example, the ramp-shaped course of the first reference signal 221 of the PLL2.
  • the PLL2 will follow the PLL1.
  • the temporal frequency profile shown in FIG. 3 can also be referred to as frequency modulation 300. As will be explained in more detail in FIG. 2b, this frequency modulation 300 can be achieved by adjusting the divider coefficients N1 and / or M1 temporally.
  • the temporal adjustment of the divider coefficients Nl 254 and / or Ml 253 but also the divider coefficients N2 264 and / or M2 263 can be achieved with correspondingly set up controls 250, 450.
  • the divider 264 operates at a lower frequency than the divider 254, resulting in a lower power consumption of the divider 264 over the divider 254.
  • FIG. 4a shows a schematic block diagram of a double heterodyne UWB radar system.
  • the structure corresponds essentially to the structure of the simple heterodyne UWB radar system according to FIG. 2a.
  • the double heterodyne radar system 400 has a second implementation of the
  • Intermediate frequency f Z F2 is lower than the first intermediate frequency f ZF i.
  • the dual heterodyne radar system has more components in the RF analog portion than the single heterodyne system, that is, in the circuit prior to digital signal preprocessing 207 '.
  • the received signal RX also passes through the low-pass filter 217 and the gain 218 before being mixed on the mixer M2 with the reference signal f Re fi generated by the PLL 2.
  • Reception intermediate frequency signal or IF reception signal which is now provided with the carrier ZFi, is provided via the terminal 401 to the mixer M4.
  • the signals generated by splitter 214 in the two channels 215a, 215b are not directly provided to digital signal preprocessor 207 as a clock signal, as in the single heterodyne case. Rather, these two signals 215a, 215b in the double heterodyne system are provided to a single sideband mixer (ESB) M3, which may refer to either the lower sideband (USB) or the upper sideband (OSB).
  • ESD single sideband mixer
  • the clock signal generated by the clock generator 209 is made available to the mixer M3 as a second intermediate frequency signal with the frequency f Z F2 on the two channels 403a, 403b with a phase difference of 90 ° of the two signals.
  • Intermediate frequency f ZF 2 is thus derived by dividing the crystal frequency f Q by the factor M.
  • the quartz 208 is the frequency stabilizing element.
  • G for example a square-wave frequency generator, generates the frequency f Q , which underlies all the signals of the UWB radar system 100, for example also the clock signal 404 for the digital one
  • the division in the frequency divider 402 takes place in such a way that two clocks shifted by 1/4 clock or 90 ° clockwise with respect to one another are generated. In other words, not only a parallelization of the clock signal is performed in the divider 402, but at the same time, comparable to the splitting device 214, a
  • the crystal frequency f Q is also distributed via the line 404 and serves as a clock for the digital signal preprocessing 207 ', which with the second
  • Signal preprocessing 207 the received signal RX.
  • the second reference frequency is shifted from the first reference frequency, ie either greater or less than the first reference frequency, ie the first reference frequency and the second reference frequency
  • the second reference signal 405 having the second reference frequency f ZF 2 is provided on a single channel. That is, the mixer M3 has the parallel channels 215a, 215b, 403a, 403b grouped together on one channel.
  • each mixing also likes filtering with one associated filter to provide only one of the frequency pairs, for example filtering with the filter 212, 204, 208th
  • the mode of operation of a single-sideband mixer (ESB) or single-reading tape mixer (SSB) is shown in FIG. 4b.
  • the divider 1 / M 402 provides a signal with the second intermediate frequency in one channel 403a and a signal with a phase shifted by + 90 ° or -90 ° with respect to the first channel 403a in the other channel 403b (In FIG. 4b a signal shifted by + 90 ° is shown).
  • the two signals 403a, 403b are each provided with a signal 215a having the first intermediate frequency, and a signal 215b also having the first intermediate frequency and one shifted by either + 90 ° or -90 ° with respect to the phase angle of the signal 215a
  • the second reference signal with the frequency f Re f 2 is mixed with the receive signal RX, 401 carried with fz F i and at the
  • Output 406 of the mixer M4, the received signal is now provided with the second intermediate frequency f Z F2 supported.
  • the received signal RX is converted to the second lower intermediate frequency f Z F2 ⁇ fzFi.
  • This receive signal 406 carried with fzF2 can be made available via a gain 407 and a bandpass filter 408 adapted for ZF 2 via the output 206 'of the digital signal preprocessing 207'.
  • the order of gain 407 and bandpass filter 408 may be reversed.
  • the result of the pre-processed in the digital signal preprocessing 207 'measurement signal is then for example via an SPI interface (Serial
  • Peripheral interface 208 to a subsequent drive unit and / or data processing unit ⁇ or the microcontroller 216 transmitted.
  • Phase noise of the PLLs PLL1 and PLL2 can be minimized. In other words, this means that the phase noise of the oscillators or the PLLs PLL1, PLL2 is not correlated with each other.
  • the signals 401, 405 are based on signals propagating in different ways within the radar system 100, 400.
  • the signals 401, 405 are essentially shifted in time relative to each other only by a transit time ⁇ of the radar signal in the radar channel, ⁇ may be the transit time from the transmission of a signal TX to the reception of a signal RX.
  • ⁇ may be the transit time from the transmission of a signal TX to the reception of a signal RX.
  • the signals 401, 405 are essentially identical in terms of time.
  • phase noise in the signals 401 and 405 is substantially approximately correlated since it is due to the same signals. Therefore, phase errors similarly affect the different branches of the circuit and cancel each other out substantially. Thus, one obtains substantially coherent signals with uniform phase position, which allow a good signal-to-noise ratio.
  • the UWB measurement system 100, 400 supplies at the output 208 the transmission signal RX reflected by the measurement object 104 as a function of the modulation frequency f Mo d or of the transmission frequency f Mo d to the following
  • the received signal RX also has the transmission frequency f Mo d.
  • the received signal RX has a signal bandwidth, preferably in the kHz range.
  • the transmission / reception decoupling or transmission / reception separation takes place with the aid of a directional coupler 102.
  • the directional coupler 102 forwards the reception signal RX from the antenna 103 to the receiver 107 with a minimum attenuation.
  • the Transmission signal TX coupled with typically 6 dB attenuation in the antenna.
  • the non-coupled into the antenna transmission signal is at the
  • Terminator 108 terminates.
  • the transmission power can be varied with the aid of an adjustable transmission amplifier.
  • the transmission amplifier 202 may be formed with an adjustable gain. This measure allows adaptation to specific circumstances, in particular to
  • a plurality of transmit channels and / or receive channels can be provided, which allow a simultaneous operation of multiple antennas 103 or an antenna array (for example, with different polarization).
  • multiple antennas can provide better results in material detection or line detectors.
  • the stepped modulation f is designed so that it can be measured from the outside.
  • an ultra-wideband radar system having a modulation PLL PLL1 and an offset PLL PLL2 and a two-stage
  • the intermediate frequency reference signal 213 has the frequency f.
  • the signal 213 may serve as an internal reference to the variable receive signal RX or Rx.
  • the received signal may have been changed on its way in the radar channel 105, 106.
  • the signal 213 may help to show the difference between the signal 213 and the received signal Rx.
  • one aspect of the present invention may be to provide an ultra-wideband radar system having a modulation PLL PLL1, an offset PLL, PLL2, and a single-stage (single heterodyne) implementation of the
  • Signal preprocessing 207 takes place a decomposition of the high-frequency IF signal into two signal components I and Q. As a result, a second mixer stage can be avoided. For sampling the high-frequency IF signal, however, a fast A / D converter is necessary. For sampling so high quality A / D
  • Transducers are needed to be placed high demands.
  • Analog / digital converters to which low demands are placed, take place and a division into the I / Q components can again take place on a digital level.
  • a reference signal can be compared with a received signal.
  • the two signals for example, by
  • a receive signal 206 carried by f ZF i can be sampled with an IF signal 215a, 215b.
  • Both signals 206, 215a, 215b contain the IF Frequency f ZF i and the substantially same phase noise or
  • phase noise can cancel each other out substantially.
  • a received signal 401 carried by f Z Fi may be mixed with a second reference signal 405 having the second intermediate frequency f Re f 2 , whereby a receive signal 206 'carried by a second intermediate frequency f Z F2 may be generated.
  • This received signal then contains a substantially exact IF (intermediate frequency) f Z F2- Also in the mixing, the phase noise contained in the intermediate frequency f ZF i or the contained combination phase noise is canceled out.
  • a signal may be applied to one
  • Intermediate frequency f ZF i are implemented and so the influence and in particular disturbances of a transmission frequency f Mo d are essentially eliminated from the signal.
  • the receive signal 206 carried by f IF i may still contain noise that has occurred during generation of the intermediate frequency f ZF i.
  • These errors of the intermediate frequency signal 206 may be substantially removed by, in one example, sampling the intermediate frequency signal 206 with a sampling signal 215a, 215b that contains the substantially same errors as the intermediate frequency signal 206.
  • the errors of the intermediate frequency signal 401 may also be substantially removed, in another example, by adding the intermediate frequency signal 401 to another intermediate frequency signal 406, 206 'or second
  • Intermediate frequency received signal 406, 206 ' is mixed.
  • the mixer M4 receives the intermediate frequency signal 401 and another
  • the further intermediate frequency f ZF 2 is in such a low frequency range that it can be scanned with simple components. It may therefore be a method and an apparatus for providing a
  • Reflection signal are given, wherein a first reference signal 221 u.a. is generated by mixing the two output signals from two frequency generators PLL1, PLL2 and wherein the first reference signal 221 is used for demodulation M2 of a received signal RX and for generating the sampling clock or for generating a second reference signal 405 for further demodulation M4 of the received signal.
  • a first reference signal 221 u.a. is generated by mixing the two output signals from two frequency generators PLL1, PLL2 and wherein the first reference signal 221 is used for demodulation M2 of a received signal RX and for generating the sampling clock or for generating a second reference signal 405 for further demodulation M4 of the received signal.
  • the first intermediate frequency received signal 206 together with the sampling clock 215 a, 215 b to a subsequent
  • the intermediate frequency receive signal 206 may be at an output and the clock signal 215a, 215b are provided with the output clock at two separate outputs.
  • a second intermediate frequency receive signal 406, 206 'along with a clock 404 may be used to clock the digital
  • Signal preprocessing 207 ' which may have the frequency f Q.
  • the sampling clock may be generated by dividing the clock signal 404 in the signal preprocessing 207 '.
  • the second intermediate frequency f Z F2 by division 402 by the factor M can be generated.
  • the second intermediate frequency received signal 406, 206 'and the clock signal 404 may each be provided at one output.
  • the second intermediate frequency f Z F2 can be provided at two outputs 403a, 403b.
  • FIG. 4c shows three block diagrams 461, 462, 463 of the first stage 804a of the decimation filter arrangement 505 according to an exemplary embodiment of the present invention.
  • the first block diagram 461 in FIG. 4c shows the structure of the first stage 804a of the order K 0 of a two-stage decimation or a two-stage decimation device 804, 805, 505.
  • the first part of the first decimation means 804a forms the classical decimation filter of the order K 0 470, which has the first FI R filter Fl Ri 464 and the clock reduction means OSR 465.
  • order K 0 expresses the number of individual feedback elements 464a and feedforward elements 464b in the implementation of decimation filter 462 as CIC and sinc filters, respectively.
  • the feedback links 464a or integration sub-filters 464a realize the addition of a current input value with an added value delayed by a time step z "1.
  • the feedforward links 464b or differentiation sub-filters realize the addition of a current value with a value delayed by a time step z " 1 , wherein the delayed value is provided with an inverted sign before adding.
  • the feedforward links 464b differentiate the output values of the clock reducer OSR 465.
  • the feedback gates 464a integrate the input signal.
  • the integration method used can be a very simple numerical integration method, which simplifies the implementation of a corresponding filter.
  • This implementation variant, including the additional filter Fl R 2 is shown in the block diagram 462 of FIG 4c.
  • the Fl R 2 filter thus connects to a decimation filter which has the same number of integration filters 464 a and differentiation filters 464 b and exactly one clock reduction device 465.
  • decimation filter By ordering a decimation filter, its stage limit can be specified.
  • One stage of a decimation filter may range from the first integration filter 464a, 604a to the last differentiation filter 604b, 464b, the number of which is predetermined by order.
  • the classical decimation filter 464, 465 can be a sine-filter, sine-filter or CIC-filter (cascaded integrator-differentiator-filter), for example with the order K 0 .
  • a sinc decimation filter or sincO decimation filter can be used in two parallel channels of parallel construction.
  • the two channels can be referred to as I-channel and Q-channel.
  • An input signal is added in a sine-decimation filter of order K 0 K 0 -fold on an adder with a signal of the same sequence delayed by one time step (z 1 ) (feedback link 464a) and a clock reducer with the factor OSR (iOSR) 465 or N (iN) provided.
  • the so reduced in clock signal is K 0 times instantaneously, and a time step (z 1 ) delayed and multiplied by -1 is provided to a summer (feedforward link 464 b).
  • the output signal of the last summer also forms the output signal of the sine decimation filter, in particular of a channel of the sine filter, the frequency or the clock of the output signal having been reduced by the factor OSR or N.
  • This realization of the classical decimation filter with downstream Fl R filter Fl R 2 466 is shown in block diagram 462 in FIG. 4 c.
  • the filters 464c connected in series correspond to the Fl R filter FI Ri, 464 in block diagram 461.
  • a classical sinc K0 decimation filter with the decimation factor OSR and the order K 0 forms, mathematically speaking, at each time step or clock the sum or mean over a number of OSR successive samples.
  • This corresponds to a Fl R filter with a number of identical coefficients corresponding to the decimation factor OSR, for example B [1, 1
  • the second part of the first decimation device 470, 464, 465 has the additional FI R filter FL R 2 466.
  • the block diagram 463 shows a further alternative realization variant of the first decimation device 804a.
  • This implementation variant differs from the realization variant according to block diagram 462 in the computational accuracy and in the implementation effort.
  • This equivalent structure 463 depends on the mathematical equivalent notation. Weite-
  • the order K 0 expresses how many individual sub-filters 464 c the FIR filter FIR 1, 46 4 has.
  • the classical decimation filter of order K 0 464, 465 has, according to the embodiment in block diagram 463, the number K 0 times repeated adder blocks 464 c and exactly one clock reduction element 465.
  • the K 0 adder blocks 464c have a series connection of the number of OSR-1 delays z "1 467.
  • an input for the clock An FIR filter or adder block 464c forms the sum of the number of clock values delayed by OSR-1 and the undelayed signal
  • the number of OSRs may be the number of clocks by which number the OSR element 465 delays the clock signal In a signal propagation direction in front of and behind the delay elements 467, the actual signals of the clock signals are tapped and supplied to the adder 468. The added signals serve as input to the subsequent stage of the adder blocks 464c.
  • the second decimation filter 805 (not shown in FIG. 4c) has a similar structure to that of the first decimation filter 804a.
  • the second decimation filter 805 does not have K 0 adder blocks 464c but Ki adder blocks.
  • the number K 0 and Ki may depend on the design specifications of a filter circuit (requirements and the transfer function of the filter).
  • the second decimation filter 805 is a decimation filter of order Ki, with the decimation factor N and an additional hold input 807.
  • K 0 can be different from Ki.
  • the product of the values OSR and N corresponds to an overall clock reduction, which allows an intermediate frequency receive signal 206, 504i, 504q of a sample clock f Z Fi or of a high internal clock rate used for quantization in a modulator 502i, 502q substantially to a high internal clock rate the representation of the useful signal, taking into account the sampling theorem, according to the bandwidth of the useful signal suitable lower clock rate to implement. Disturbing signal components and noise, in particular outside the bandwidth of the useful signal, are largely suppressed.
  • I / Q demodulation with a conversion of an intermediate frequency carrier-carried signal 206 into a complex-valued I / Q signal in baseband, without carrier.
  • a two-stage filter structure may be used in a plurality of parallel channels, for example, in the parallel construction of I / Q channels.
  • the second stage 805 of the two-stage decimation filter is discussed in FIG.
  • FIG. 5 shows a simple heterodyne UWB system 500, in which the analog part 501 (ie the part of the circuit up to the terminal 206 of the digital part 207) substantially corresponds to the simple heterodyne UWB system of FIG.
  • the digital part 207 or the digital signal preprocessing 207 will be considered in more detail.
  • the digital part 207 is based on the so-called principle of direct sampling of an intermediate frequency signal.
  • the use of direct sampling allows a reduction in the implementation cost of integration on an integrated circuit (IC). For example, by using the principle of direct sampling, the expenditure for implementation can be reduced in relation to the area required for the integration of the IC.
  • the principle of direct sampling envisages switching to digital components as early as possible in the demodulation chain of the receiver 107.
  • the use of digital components eliminates the need for analog components and thus eliminates the problems due to tolerances, matching, etc. of the replaced analog circuit parts, thereby avoiding errors.
  • a functionality of analog circuit parts is shifted into the digital part 207.
  • Direct sampling also minimizes the power requirements of a corresponding UWB device or integrated circuit (IC).
  • the signal evaluation was designed in such a way that unwanted signals are substantially suppressed by high attenuation using the direct sampling principle with a low implementation effort.
  • a bandpass signal of the received signal RX, the intermediate frequency signal or IF received signal is provided.
  • the digital part 207 receives from the previous analog part via the input 206 a received signal RX carried with the IF (intermediate frequency) f Z Fi. This carried signal may still be at a relatively high frequency level f Z Fi compared to the output signal 508i, 508q. In order to be able to process this signal 206 with simple analog / digital converters, it would have to be mixed down, for example, into the baseband.
  • the receive intermediate-frequency signal 206 is split via the splitting device 503 to two channels 504i and 504q and to the analog / digital converters 502i and 502q or the delta-sigma modulators 502i, 502q equally provided.
  • the splitting device 503 receives the high-frequency receive intermediate-frequency signal 206 directly directly by direct sampling.
  • Device 503 may be a Y-element that copies the input signal to both channels. Instead of a Y-gate, the receive intermediate frequency signal 206 may be sampled directly with two different sample clocks 215a, 215b and different modulators 502i, 502q. The various sampling cycles are discussed in more detail in FIG.
  • the substantially same intermediate frequency signal 206 is present at the inputs of the two analog / digital converters 502i, 502q.
  • connections signals which are routed via the connections, and / or inputs of function blocks or of blocks with the same or similar reference symbols may be named.
  • a signal may be designated by the associated reference numeral of the respective channel.
  • the sampling clocks are provided as first clock signal 215a and second clock signal 215b.
  • the intermediate frequency f Z Fi essentially corresponds to the
  • the displacement member 214 may be integrated in a scanner 502i, 502q, so that the scanner 502i, 502q, via a single input, the
  • the digital signal preprocessing 207 has an input for the sampling clock.
  • the digital signal preprocessing 207 can also have at least two inputs 215a, 215b via which it receives the shifted sampling clock signals 215a, 215b.
  • the intermediate frequency signal 206 phase-shifted channel signals or time-shifted channel signals 509i, 509q.
  • this means that the first sample clock signal 215a in the first channel 509i is phase-shifted by + 90 degrees or -90 degrees with respect to the second sample clock signal 215b in the second channel 509q.
  • the first sampling clock signal and the second sampling clock signal have been derived from the difference frequency of the PLLs f Z Fi, ie the IF reference signal 213 with the actual intermediate frequency f Z Fi serves as the basis for the sampling clock signals 215a, 215b.
  • the clock signals in the clock channels 215a, 215b which are phase-shifted by either +90 ° or -90 °, drive the ADCs 502i, 502q with signals having a different phase angle and consequently generate signals 509i, 509q sampled at different times.
  • the first modulator 502i receives from the splitting device 503 the first channel signal 504i and provides at its output the first sampled digitized received signal 509i or sampled first channel signal 509i.
  • the second modulator 502q provides the second sampled digitized received signal 509q or the second sampled channel signal 509q.
  • the sampled digitized receive signals are independently low pass filtered 506i, 506q and decimated 507i, 507q in the decimation means in the sampling rate.
  • sampling devices or modulators 502i, 502q may be implemented as sigma-delta (A) modulators. Further, the sigma-delta modulators may also include an additional low-pass filter 506i, 506q.
  • a sigma delta modulator may be implemented as a low-pass sigma delta modulator ( ⁇ - ⁇ ).
  • a ⁇ - ⁇ modulator may have a small word width but a nem high sampling clock, for example, with the frequency of the sampling clock signal 215a, 215b.
  • the word width may be 1 bit, a few bits or a plurality of bits. Due to the usually small word width, digitization noise or quantization noise may arise. Due to the high clock rate of the ⁇ - ⁇ modulators 502i, 502q and a suitable noise transfer function, which corresponds substantially exactly to the carrier frequency f Z Fi, the digitization noise may be shifted into frequency ranges which are substantially eliminated by the low-pass filter 506i, 506q can be. This shifting of the digitization noise to a higher frequency range may be referred to as noise shaping.
  • the noise shaping may essentially only affect the digitizing noise of the sampler in the ⁇ - ⁇ modulator 502i, 502q.
  • phase noise contained in the receive intermediate frequency signal 206 remains substantially unaffected by the low pass filtering, the phase noise is substantially eliminated by the particular type of sampling in the samplers 502i, 502q.
  • This particular type of sampling provides that the frequency of the sampling signal 215a, 215b and the frequency of the intermediate frequency signal 206 are based essentially on the same frequency f Z Fi.
  • the intermediate-frequency signal 206 and also the sampling signal 215a, 215b are derived from the same difference signal between the PLLs PLLi and PLL 2 , whereby their phase noise is correlated.
  • Both the receive intermediate frequency signal 206 and the sampling signal 215a, 215b are essentially identical to the ben frequency, for example, the intermediate frequency f Z Fi supported. Consequently, these signals are correlated such that the transient effects and the phase noise do not affect too much, since they act in substantially the same sense on both the intermediate frequency signal 206 and the clock signals 215a, 215b.
  • the phase noise and the phase error are approximately equally mapped or correlated in both signals, substantially compensating and suppressing the phase noise and the phase error during sampling.
  • the demodulation of the received intermediate frequency signal 206 into the baseband essentially takes place digitally in the digital signal preprocessing 207.
  • the UWB measuring system 500 supplies the scattering parameter Sil at the two outputs 508i and 508q of the digital signal preprocessing 207 as a function of the modulation frequency f Mo d or Transmission frequency f Mo d to the following signal processing unit 216 ( ⁇ ). In other words, the scatter parameter becomes
  • the signals at the outputs 508i, 508q of the decimation means 505, 507i, 507q are the clock-reduced first channel signal 508i and the clock-reduced second channel signal 508q. These signals may be, for example, baseband signals.
  • the provision of the output signal in the two channels 508i and 508q or as separate signals 508i, 508q takes account of the fact that the scattering parameter Sil is a complex value. Due to the division into an in-phase component (I) and a quadrature component (Q), it is also possible, in terms of circuitry, to calculate complex scattering parameters, i. Scattering parameters with a real and an imaginary part, to be processed by a digital circuit.
  • I in-phase component
  • Q quadrature component
  • the division into two ADCs 502i, 502q makes it possible, especially when using ⁇ modulators, to set low quality requirements for the ADCs used and thus to be able to process the high-frequency IF signal 206 even with easily realizable ADCs.
  • the intermediate frequency signal 206 or IF signal 206 may be a high frequency signal.
  • the ADCs 502i and 502q are driven in a special manner, for example by the controller 550, to realize a complex sampling or demodulation. This particular type of scanning is described with the pulse combs 600 of FIG. This type of scanning causes a
  • I / Q demodulation of the signal to be sampled can be done in the baseband.
  • the signals 215a and 215b which are present in parallel are shown on the normalized time axis 601 t * f a .
  • T a is the sampling period and f a is the sampling frequency.
  • the second clock signal 215b or the Q clock is shifted by ⁇ ⁇ clock compared with the first clock signal 215a or with respect to the I clock or has a phase shift of + 90 °.
  • the Q-clock 215b precedes the I-clock 215a by V *, ⁇ / 2 or 90 degrees.
  • a corresponding image frequency filter 801a, 801b in the I channel 504i are selected.
  • the Zero-Order Hold (ZOH) element 802 is transitioned to the zero-degree phase of the I-channel.
  • the zero-order hold element 802 is used to synchronize the sampled digitized received signals 509i, 509q.
  • FIG. 7 shows a section of a block diagram of an implementation variant of the digital part 207 with reduced components according to an exemplary embodiment of the present invention.
  • the image frequency filter 801a, 801b, 803, 802 and 806 is represented by a simplified embodiment, a single ZOH gate 802.
  • the detailed structure of the image frequency filter in the original form or according to another embodiment of the present invention is shown in FIG. 8.
  • the two ADCs 502i, 502q and the zero-order hold (ZOH) member 802 are provided.
  • the first ADC 502i is driven 215a with the same clock as the zero-order hold member 802.
  • the second ADC 502q is operated with a corresponding ⁇ 90 degree leading or lagging sampling clock to achieve I / Q demodulation.
  • simplified "mirror frequency filtering" still implicitly occurs here:
  • an expanded or improved image frequency filter can be provided in the circuit according to FIG. 7; in particular, the simple image frequency filter 802 can be expanded by further components 801a, 801b, 803, 806.
  • the two-stage decimation following the outputs 701, 702 is not shown in FIG. 7, but corresponds to the two-stage decimation described in FIG. 8.
  • FIG. 8 describes how such an additional image frequency filter 801a, 801b, 803, 806 or an expanded image frequency filter 801a, 801b, 803, 802, 806 can be used with reference to FIG.
  • FIG. 8 shows the two-stage decimation by means of first decimation filter 804 and second decimation filter 805.
  • Such a two-stage decimation filter 804, 805 is used in the circuit according to FIG. 7, but is not shown in FIG.
  • the image frequency filter 801a, 801b, 803, 802, 806 according to FIG. 8 can be realized with little effort since it can do without multiplication and uses only a few simple shift-add operations.
  • the ADCs 502i, 502q generate a high frequency sampled first channel signal 509i and a high frequency sampled second channel signal 509q.
  • the frequency or rate of these high frequency sampled channel signals 509i, 509q can be reduced with a subsequent first decimation filter 804 and second decimation filter 805.
  • the high-frequency sampled channel signals which essentially correspond to a non-transmitted received signal, are in the baseband. Consequently, the sampled channel signals are no longer high frequency.
  • the sampling theorem can be taken into account by dimensioning the factor N such that the sampling rate of the output signals I, Q is as small as possible, ie N is chosen to be large, but, in comparison to the useful signal bandwidth, is still large enough to satisfy the sampling theorem.
  • N should be chosen large, N should not be too large, so that no aliasing occurs.
  • the first decimation filter 804 and the second decimation filter 805 described in FIG. 8 can be realized with little effort and essentially without multiplication stages by a few simple shift-add operations.
  • FIG. 8 shows a detailed representation of the digital signal processing unit 207, which has a ⁇ modulator 502i, 502q, a first clock reduction 507i, 507q, with the decimation factor OSR (Over Sampling Rate) and a second clock reduction device with the decimation factor N.
  • the ZA modulators 502i, 502q in conjunction with the decimation low pass 804, 805 form a specific (adapted to the specific requirements of the radar system) ⁇ AD converter.
  • the ADC Analog Digital Converter or Analog Digital Converter
  • a corresponding image frequency filter 801a, 801b can be switched on by means of the switch 803 as a function of the phase position selected using the sampling signal 215b.
  • a lagging phase of -90 degrees is selected for the quadrature scan 215b, and the tracking mirror frequency filter 801b is selected. If a leading phase of +90 degrees is selected for the quadrature scan 215b, the forward mirror frequency filter 801a is selected by means of the switch 803.
  • the switch 803 can be dispensed with and either a leading mirror frequency filter or tracking mirror frequency filter can be fixedly provided in the I channel 509i.
  • the decimation of the decimation filter 505, 804, 805 is realized as a two-stage decimation with low-pass filtering.
  • the decimation device 505 has the first decimation device 804 or first decimation step
  • the sampling rate f s , f a , f if i or f ZF i, in particular the sampled channel signal 509 i, 509 q with a corresponding clock rate, is reduced by the factors OSR and N in the first stage 804 and in the second stage 805.
  • the last mixer stage M2 and the intermediate frequency filter 204 which serves as an anti-aliasing (AA) filter, provide the intermediate frequency signal with the frequency f Z Fi 206 for the digital part 207.
  • the values OSR and N, respectively, by which the clock reduction devices OSR and N respectively reduce the clock of the ZA modulator output signals 509i, 509q or the high-frequency sampled channel signals 509i, 509q, depend on the configuration of the UWB system.
  • the higher frequency the sampling clock f Z Fi fs 215a, 215b is selected, the higher or higher the value of the clock reduction OSR or N may be selected.
  • the higher frequency the sampling clock f Z Fi fs 215a, 215b is selected, the more accurate the low-pass filtered and clock-reduced received signal 508i, 508q may be formed. In other words, the decimation device 505 may then have a higher signal-to-noise ratio (SNR) or a higher wordwidth at the output.
  • SNR signal-to-noise ratio
  • the first decimation filter 804 represents a decimation filter K 0 -th order (K 0 ), and the second decimation filter 805 represents a decimation filter Ki-th order (Ki).
  • K 0 corresponds to the number of feedback links 464a and the feedforward links 464b 4 c, which are used in the first decimation stage 804.
  • the value Ki corresponds in each case to the number of feedback elements 464a and the forward coupling elements 464b which are used in the second decimation stage 805 corresponding to the block diagram 462 (the second decimation stage 805 is not shown in FIG. 4c).
  • the decimation factor N is used instead of the decimation factor OSR in the demimulator 465.
  • Fl R 2 is not included in the second decimation step.
  • the complex sampling of the received intermediate frequency signal 206 carried by f Z Fi is performed by the two sigma-delta modulators 502i, 502q delayed by ⁇ 1 A clock or by ⁇ 90 ° out of phase, ie +1 compared to the other channel / 4 or -1/4 or offset by + 90 ° or -90 °.
  • the intermediate frequency signal 206 is copied in the splitting device 503 into the two channels 504i and 504q.
  • the corresponding selecting image frequency filters 801a, 801b in I channel 509i can be made for example by means of the selector 803.
  • the Zero-Order Hold (ZOH) element 802 makes a transition to the 0 degree phase of the I-channel or a synchronization of both channels.
  • FI R 2 FI R filter
  • the second decimation filter 805 is also a sine decimation filter, but having the order Ki (sinc K1 ) and the decimation factor N.
  • An additional filter comparable to Fl R 2 809i, 809q is not present in the second decimation stage 805.
  • the hold signal is derived from PLL1 and / or PLL2 (not shown in FIG. 8) and serves to hide the time interval in which the two PLL stages PLL1, PLL2 settle to their desired value.
  • the hold signal is adapted such that the hold signal 807 during the oscillation of at least one of the PLL stages PLL1, PLL2 to their desired value, the I-channel signal and / or the Q-channel signal can hide.
  • a transient of the PLL stage may occur after changing a frequency, for example when passing through the staircase ramp 300.
  • the carrier is substantially eliminated. So a complex reflection factor can be provided.
  • the method and apparatus for providing a reflectance signal may demodulate an intermediate frequency intermediate frequency signal in I / Q components substantially without intermediate frequency. So a complex reflection factor can be provided.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Theoretical Computer Science (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

L'invention concerne un procédé et un dispositif pour fournir un signal de réflexion. Selon l'invention, un signal d'une fréquence intermédiaire élevée peut être démodulé de manière numérique en composantes I/Q sans fréquence intermédiaire par l'intermédiaire d'un échantillonnage sur deux canaux. Ceci permet d'obtenir un facteur de réflexion complexe.
EP10742136A 2009-09-01 2010-08-06 Procédé et dispositif pour fournir un signal de réflexion Withdrawn EP2473865A1 (fr)

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DE102009029051A DE102009029051A1 (de) 2009-09-01 2009-09-01 Verfahren und Vorrichtung zum Bereitstellen eines Reflexionssignals
PCT/EP2010/061489 WO2011026711A1 (fr) 2009-09-01 2010-08-06 Procédé et dispositif pour fournir un signal de réflexion

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DE102009029051A8 (de) 2011-06-01

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