EP2360664A1 - Affichage avec mécanisme d'ajustement automatique de phase CLK et son procédé de commande - Google Patents

Affichage avec mécanisme d'ajustement automatique de phase CLK et son procédé de commande Download PDF

Info

Publication number
EP2360664A1
EP2360664A1 EP20100165000 EP10165000A EP2360664A1 EP 2360664 A1 EP2360664 A1 EP 2360664A1 EP 20100165000 EP20100165000 EP 20100165000 EP 10165000 A EP10165000 A EP 10165000A EP 2360664 A1 EP2360664 A1 EP 2360664A1
Authority
EP
European Patent Office
Prior art keywords
clock
clock signal
display
signals
training code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP20100165000
Other languages
German (de)
English (en)
Inventor
Chien-Fu Huang
Chun-Fan Chung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Publication of EP2360664A1 publication Critical patent/EP2360664A1/fr
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates generally to a display, and more particularly to a display that utilizes a CLK phase auto-adjusting mechanism in source drivers to increase the operation frequency of the display and a method of driving same.
  • a typical driving system of a flat panel display includes a timing controller, source drivers and gate drivers.
  • the timing controller generates data, clock and synchronization signals, which are transmitted to the source drivers in a bus manner.
  • the source drivers receive data from the timing controller according to the rising and falling edges of the clock signal.
  • Transmission interfaces commonly used for signal transfer between the timing controller and the source drivers are interfaces with two signal levels, such as reduced swing differential signaling (RSDS) and mini low voltage differential signaling (mini-LVDS) interfaces.
  • RSDS reduced swing differential signaling
  • mini-LVDS mini low voltage differential signaling
  • the data transmission rate in the driving system is substantially increased.
  • transmission of data and clock signals employs the bus transmission interface.
  • the signaling lines coupling to the timing controller and different source drivers have great line length difference. Accordingly, the signaling lines corresponding to different source drivers may work under different loads, resulting in rising and falling rates of transmission signals.
  • the source drivers since the source drivers jointly receive the data signals via a bus, the data signals received by different source drivers may have different phase delays due to different transmission line lengths. As a result, data and clock skews may occur in the transmission signals, thereby resulting in erroneous data reception in the source drivers and therefore deteriorating the performance of the flat panel display.
  • TCON timing controller
  • CLK clock training code
  • SD source driver
  • each source driver comprises a multi-phase clock generator for generating the plurality of clock signals, ⁇ CLKj ⁇ ; and a clock selector for obtaining the optimal clock signal from the plurality of clock signals ⁇ CLKj ⁇ according to the clock training code.
  • the multi-phase clock generator comprises buffer delays, delay locked loops (DLL) or phase locked loops (PLL).
  • DLL delay locked loops
  • PLL phase locked loops
  • the clock training code is transmitted from the timing controller to the plurality of source drivers during a blanking.
  • the timing controller is configured to further provide a synchronization signal, SYNC, to the plurality of source drivers, wherein the synchronization signal SYNC has a high voltage period defining a clock training period in which the clock training code occurs.
  • the timing controller is configured to further provide a receiving setup signal, DIO, and/or an output setup signal, STB, used to define a clock training period in which the clock training code occurs.
  • the clock signal is transmitted from the timing controller to the plurality of source drivers in a bus type
  • the plurality of data signals is transmitted from the timing controller to the plurality of source drivers in one of a bus type, a point-to-point type and a cascade type.
  • the display may have a scrambler coupled with the timing controller for scrambling the plurality of data signals before it is provided to the plurality of source drivers; and a plurality of descramblers, each descramble coupled with a corresponding source driver for descrambling scrambled data signals received from the scrambler.
  • the present invention relates to a method for driving a display for data display.
  • Each of the plurality of clock signals ⁇ CLKj ⁇ has a frequency that is identical to that of the at least one clock signal CLK and a phase that is different from each other and from that of the clock signals CLK.
  • step (a) is performed with a timing controller, and wherein steps (b)-(d) are performed with a plurality of source drivers.
  • the generating step is performed with a multi-phase clock generator, wherein the multi-phase clock generator comprises buffer delays, DLL or PLL.
  • the selecting step is performed with a clock selector.
  • the selecting step comprises the steps of comparing each of the plurality of clock signals ⁇ CLKj ⁇ with the clock training code; determining whether a rising or falling edge of each of the plurality of clock signals ⁇ CLKj ⁇ falls within the clock training code; and selecting the one of which its rising edge or falling edge falls in the most middle of the clock training code as the optimal clock signal.
  • the clock signal is transmitted from the timing controller to the plurality of source drivers in a bus type
  • the plurality of data signals is transmitted from the timing controller to the plurality of source drivers in one of a bus type, a point-to-point type and a cascade type.
  • the clock training code is transmitted from the timing controller to the plurality of source drivers during a blanking.
  • the method may have the step of providing a synchronization signal, SYNC having a high voltage period defining a clock training period in which the clock training code occurs.
  • the method may have the step of providing a receiving setup signal, DIO, and/or an output setup signal, STB, used to define a clock training period in which the clock training code occurs.
  • the method also includes the step of displaying the latched data signals. Moreover, the method may include steps of scrambling the plurality of data signals before the providing step is performed; and descrambling the scrambled data signals before the latching step is performed.
  • the present invention relates to a display for displaying data.
  • the providing means comprises a timing controller.
  • the generating means comprises a multi-phase clock generator, and wherein the selecting means comprises a clock selector.
  • the multi-phase clock generator and the clock selector constitute a source driver.
  • this invention in one aspect, relates to a display that utilizes a CLK phase auto-adjusting mechanism in source drivers to increase the operation frequency of the display and improve the performance of the display and a method of driving same.
  • the display 100 includes a timing controller (TCON) 110 and a plurality of source drivers 120 coupled with the timing controller 110.
  • TCON timing controller
  • the timing controller 110 receives low voltage differential signals (LVDS) from one or more upstream devices and responsively generates clocks, control signals and data signals to be displayed.
  • the generated clocks, control signals and data signals are transmitted to the source drivers 120 via one or more transmission interfaces.
  • the source drivers 110 convert the received data signals into analog voltage driving signals in accordance with the clocks and control signals.
  • the converted analog voltage driving signals is used to drive a display panel (not shown) for display of the data signals.
  • the timing controller 110 is configured to provide a plurality of data signals, DATA, to be displayed, at least one clock signal, CLK, a clock training code corresponding to the plurality of data signals DATA, and a synchronization signal, SYNC.
  • the synchronization signal SYNC is adapted for controlling the time of outputting the voltage driving signals, i.e., the synchronization signal SYNC functions to notify each source driver 120 of the time, the timing controller 110 transmits the data signals.
  • the synchronization signal SYNC is also adapted for initializing a process of clock phase selection, which its high voltage period is used to define a clock training period in which the clock training code occurs.
  • the clock training code is transmitted from the timing controller 110 to the plurality of source drivers 120 during a blanking.
  • Each source driver (SD) 120 has a multi-phase clock generator 121 and a MUX (clock selector) 122 and a data latch unit 123.
  • the multi-phase clock generator 121 includes buffer delays, delay locked loops (DLL) or phase locked loops (PLL).
  • Each of the plurality of clock signals ⁇ CLKj ⁇ has a frequency that is identical to that of the at least one clock signal CLK and a phase that is different from each other and from that of the clock signals CLK.
  • the MUX 122 of the source driver 120 selects one clock signal from the plurality of clock signals ⁇ CLKj ⁇ as an optimal clock signal according to the clock training code.
  • the selected optimal clock signal is used to latch the one or more corresponding data signals in the data latch unit 123.
  • the latched data signals are adapted for driving the display panel to display the data signals.
  • the synchronization signal SYNC, the at least one clock signal CLK and the data signals DATA are transmitted from the timing controller 110 to the source drivers 120 in the bus type manner. As shown below, they can be transmitted from the timing controller 110 to the source drivers 120 in other manners, such as in a cascade type and a point-to-point type.
  • Fig. 2 shows schematically a partially block diagram of a display 200 according to one embodiment of the present invention.
  • the display 200 includes a timing controller 210 and a source driver 220, which both are essentially same as those of the display 100 shown in Fig. 1 .
  • the source driver 220 has a multi-phase clock generator 221 for generating multiple phase clock signals, CLK1, CLK2, CLK3, ...., and a clock phase comparator (clock phase selector) 222 for receiving the multiple phase clock signals, CLK1, CLK2, CLK3, ..., from the multi-phase clock generator 221, and comparing each of them to a clock training code (or clock correction code) received from the timing controller 210, and selecting one clock of which its rising edge or falling edge falls in the most middle of the clock correction code as the optimal clock signal CLKOP.
  • the optimal clock signal CLKOP will be used to latch the data signal DATA received from the timing controller 210.
  • Figs. 3 and 4 are two embodiments of the source driver 220.
  • the multi-phase clock generator 221A of the source driver 220 includes buffer delays.
  • the multi-phase clock generator 221B of the source driver 220 includes buffer delays, as shown in Fig. 4 .
  • FIG. 5 a block diagram of a display 500 and its flow chart for a clock phase selection are schematically shown according to one embodiment of the present invention.
  • the timing controller 510 generates data signals DATA, a clock signal CLK, a clock training code corresponding to the data signals DATA, and a synchronization signal SYNC, and transmits them to the source driver 520 via one or more transmission interfaces.
  • the at least one clock signal CLK is received by the multi-phase CLK generator 521, it generates multiple phase clock signals, CLK1, CLK2, CLK3, ..., responsively.
  • the multiple phase clock signals, CLK1, CLK2, CLK3, ... have the same frequency as that of the at least one clock signal CLK and different phases, as shown in Figs. 7 and 8 .
  • the generated multiple phase clock signals, CLK1, CLK2, CLK3, ..., along the data signals DATA, the clock training code and the synchronization signal SYNC, are transmitted to the CLK selector 522 of the source driver 520.
  • the synchronization signal SYNC has a high voltage period that is used to define a clock training period, as shown in Fig. 6 .
  • the CLK selector 522 compares each of the generated multiple phase clock signals, CLK1, CLK2, CLK3,..., with the clock training code at step 523.
  • the one of which its rising edge or falling edge falls in the most middle of the clock training code is selected as the optimal clock signal CLKOP (at step 524).
  • clock signals CLK1-CLK8 having different phases are generated.
  • the rising edges of CLK1, CLK2, CLK3, CLK7 and CLK8 are corresponding to the jitter portion of the DATA
  • the rising edges of CLK4, CLK5 and CLK6 fall into the clock training code that are defined between two neighboring data jitters.
  • the rising edge of CLK5 is in the most middle of the clock training code. Therefore, CLK5 is selected as the optimal clock signal CLKOP.
  • the display data is received at step 525. Otherwise, if no rising or falling edge of the generated multiple phase clock signals, CLK1, CLK2, CLK3, ..., falls in the clock training code, the multi-phase CLK generator 521 is requested to re-generate second multiple phase clock signals in accordance with the at least one clock signal CLK, which will be send to the CLK selector 522 for CLK phase selection.
  • a display of the invention is shown according to three different embodiments 900, 1000 and 1100, where data different transmission interfaces are employed respectively.
  • the synchronization signal SYNC and the at least one clock signal CLK are both transmitted from the timing controller TCON to the source drivers SD in the bus type manner.
  • the data signals DATA are transmitted in the point-to-point type manner.
  • the synchronization signal SYNC and the at least one clock signal CLK and the data signals DATA are all transmitted from the timing controller TCON to the source drivers SD in the bus type manner.
  • the synchronization signal SYNC is transmitted from the timing controller TCON to the source drivers SD in the bus type manner, while the at least one clock signal CLK and the data signals DATA are both transmitted in the cascade type manner.
  • Fig. 12 shows schematically a partially block diagram of a display 1200 according to one embodiment of the present invention.
  • the display 1200 has essentially same structure as the display 100 shown in Fig. 1 , except that the clock training and selection of the multi-phase clock signals generated by the multi-phase clock generator of the source driver are controlled by a receiving setup signal, DIO, or an output setup signal, STB, as shown in Fig. 13 , rather than by a synchronization signal SYNC.
  • Both the receiving setup signal DIO and the output setup signal STB are generated by the timing controller.
  • the receiving setup signal DIO indicates the source drivers to prepare for data reception, while the output setup signal STB controls the time the source drivers output signals.
  • Fig. 14 shows schematically a partially block diagram of a display 1400 according to another embodiment of the present invention.
  • the display 1400 has essentially similar structure to the display 100 shown in Fig. 1 , except that scramblers and descramblers are utilized to reduce the EMI among the clock training code.
  • the display 1400 had a scrambler 1412 coupled with a data memory 1411 of the timing controller 141.
  • the scrambler 1412 is adapted for scrambling the plurality of data signals and thus the clock training code, before they are transmitted to the source drivers 1420.
  • the scrambled clock training code is used for selecting the optimal clock signal.
  • the scrambled data signals need being restored/descrambled before they are sent to a display panel. This can be implemented by a plurality of descramblers 1424 with each coupled with the data latch unit 1423 of a corresponding source driver 1420 for descrambling scrambled data signals received from the scrambler 1412.
  • Fig. 15 shows schematically (a) scrambling and (b) descrambling of data according to one embodiment of the present invention.
  • the key generator may change the scrambler key
  • the timing controller TCON and the source driver are configured to change the key synchronously.
  • Fig. 16 shows scrambled clock phase signals of 250 phase data according to one embodiment of the present invention.
  • the real data, 10101010 greylevel 170
  • the regulated data 10101010 is no longer the regulated data 10101010, but irregulated data, thereby reducing the EMI.
  • a display having scramblers and descramblers is shown according to three different embodiments 1700 and 1800, where data different transmission interfaces are employed respectively.
  • the data signals DATA and the at least one clock signal CLK are both transmitted from the timing controller TCON to the source drivers SD in the bus type manner.
  • the at least one clock signal CLK is transmitted from the timing controller TCON to the source drivers SD in the bus type manner, while the data signals DATA are transmitted in the point-to-point type manner.
  • One aspect of the present invention relates to a method for driving a display for data display.
  • Each of the plurality of clock signals ⁇ CLKj ⁇ has a frequency that is identical to that of the at least one clock signal CLK and a phase that is different from each other and from that of the clock signals CLK.
  • Step (a) is performed with a timing controller, and wherein steps (b)-(d) are performed with a plurality of source drivers.
  • the clock training code is transmitted from the timing controller to the plurality of source drivers during a blanking.
  • the selecting step comprises the steps of comparing each of the plurality of clock signals ⁇ CLKj ⁇ with the clock training code; determining whether a rising or falling edge of each of the plurality of clock signals ⁇ CLKj ⁇ falls within the clock training code; and selecting the one of which its rising edge or falling edge falls in the most middle of the clock training code as the optimal clock signal.
  • the method also includes the step of providing a synchronization signal, SYNC having a high voltage period defining a clock training period in which the clock training code occurs.
  • the method may have the step of providing a receiving setup signal, DIO, and/or an output setup signal, STB, used to define a clock training period in which the clock training code occurs.
  • the providing means comprises a timing controller.
  • the generating means comprises a multi-phase clock generator, and the selecting means comprises a clock selector.
  • the multi-phase clock generator and the clock selector constitute a source driver.
  • the present invention recites a display that utilizes a CLK phase auto-adjusting mechanism in source drivers to increase the operation frequency of the display and improve the performance of the display and a method of driving same. Accordingly, there is no need to increase the frequency of the at least one clock signal CLK, and therefore the integrity of the at least one clock signal CLK is reserved during operation. Additionally, the use of the rising edge of a clock signal to latch the data signal causes no issue of the internal duty. Further, no data skew occurs according to the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP20100165000 2010-02-12 2010-06-04 Affichage avec mécanisme d'ajustement automatique de phase CLK et son procédé de commande Ceased EP2360664A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/704,658 US8362996B2 (en) 2010-02-12 2010-02-12 Display with CLK phase auto-adjusting mechanism and method of driving same

Publications (1)

Publication Number Publication Date
EP2360664A1 true EP2360664A1 (fr) 2011-08-24

Family

ID=44022798

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20100165000 Ceased EP2360664A1 (fr) 2010-02-12 2010-06-04 Affichage avec mécanisme d'ajustement automatique de phase CLK et son procédé de commande

Country Status (2)

Country Link
US (1) US8362996B2 (fr)
EP (1) EP2360664A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015190925A3 (fr) * 2014-06-11 2016-02-04 Hj Forever Patents B.V. Système de pilote d'affichage à papier électronique
CN107689203A (zh) * 2016-08-04 2018-02-13 瑞鼎科技股份有限公司 显示装置及其驱动电路

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474304B (zh) * 2012-11-09 2015-02-21 Novatek Microelectronics Corp 時序控制器、源極驅動器、顯示驅動電路及顯示驅動方法
TWI466086B (zh) * 2012-12-10 2014-12-21 Novatek Microelectronics Corp 時序擾亂方法及其時序控制裝置
US9112655B1 (en) * 2013-07-30 2015-08-18 Altera Corporation Clock data recovery circuitry with programmable clock phase selection
CN103839528B (zh) * 2014-02-20 2016-02-10 北京京东方显示技术有限公司 拼接显示屏的同步显示方法、时钟控制器及拼接显示屏
CN103943079B (zh) * 2014-03-06 2016-05-18 京东方科技集团股份有限公司 一种显示系统中数据传输的方法及相关装置
KR102260670B1 (ko) 2015-03-27 2021-06-08 삼성디스플레이 주식회사 데이터 구동회로, 그것을 포함하는 표시 장치 및 그것의 동작 방법
TWI585741B (zh) 2016-08-04 2017-06-01 友達光電股份有限公司 驅動裝置與驅動方法
CN109887458B (zh) * 2019-03-26 2022-04-12 厦门天马微电子有限公司 显示面板和显示装置
KR20210129327A (ko) * 2020-04-20 2021-10-28 주식회사 엘엑스세미콘 데이터구동장치 및 이의 구동 방법
KR20220085319A (ko) 2020-12-15 2022-06-22 주식회사 엘엑스세미콘 데이터 구동 회로
CN112732619B (zh) * 2021-01-11 2023-08-11 合肥中科君达视界技术股份有限公司 一种高速lvds接口通信训练方法及装置
KR20230071309A (ko) * 2021-11-16 2023-05-23 주식회사 엘엑스세미콘 타이밍 컨트롤러, 이를 포함하는 디스플레이 구동장치 및 타이밍 컨트롤러를 구동하는 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002057891A1 (fr) * 2001-01-22 2002-07-25 Mayo Medical Foundation For Medical Education And Research Circuit d'alignement en phase bit-horloge de donnees avec une premiere capacite de capture de bits
US20070211010A1 (en) * 2006-03-10 2007-09-13 Che-Li Lin Display system capable of automatic de-skewing and method of driving the same
US20080106510A1 (en) * 2006-11-03 2008-05-08 Yin Xinshe Intra-system interface unit of flat panel display
US20090303217A1 (en) * 2008-06-04 2009-12-10 Novatek Microelectronics Corp. Transmission interface for reducing power consumption and electromagnetic interference and method thereof
US20100060557A1 (en) * 2008-09-10 2010-03-11 Himax Technologies Limited Data de-skew block device and method of de-skewing transmitted data

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US6125157A (en) 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US20010013802A1 (en) 1999-07-07 2001-08-16 Ghene Faulcon System and process for high speed interface clock skew correction
US6633288B2 (en) 1999-09-15 2003-10-14 Sage, Inc. Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display
US6873318B1 (en) 2001-05-23 2005-03-29 National Semiconductor Corporation Method and apparatus for addressing beat patterns in an integrated video display system
US6954201B1 (en) 2002-11-06 2005-10-11 National Semiconductor Corporation Data bus system and protocol for graphics displays

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002057891A1 (fr) * 2001-01-22 2002-07-25 Mayo Medical Foundation For Medical Education And Research Circuit d'alignement en phase bit-horloge de donnees avec une premiere capacite de capture de bits
US20070211010A1 (en) * 2006-03-10 2007-09-13 Che-Li Lin Display system capable of automatic de-skewing and method of driving the same
US20080106510A1 (en) * 2006-11-03 2008-05-08 Yin Xinshe Intra-system interface unit of flat panel display
US20090303217A1 (en) * 2008-06-04 2009-12-10 Novatek Microelectronics Corp. Transmission interface for reducing power consumption and electromagnetic interference and method thereof
US20100060557A1 (en) * 2008-09-10 2010-03-11 Himax Technologies Limited Data de-skew block device and method of de-skewing transmitted data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015190925A3 (fr) * 2014-06-11 2016-02-04 Hj Forever Patents B.V. Système de pilote d'affichage à papier électronique
CN107689203A (zh) * 2016-08-04 2018-02-13 瑞鼎科技股份有限公司 显示装置及其驱动电路

Also Published As

Publication number Publication date
US8362996B2 (en) 2013-01-29
US20110199368A1 (en) 2011-08-18

Similar Documents

Publication Publication Date Title
EP2360664A1 (fr) Affichage avec mécanisme d'ajustement automatique de phase CLK et son procédé de commande
US8362997B2 (en) Display with CLK phase or data phase auto-adjusting mechanism and method of driving same
KR101642849B1 (ko) 구동 장치의 동기화 방법 및 이를 수행하기 위한 표시 장치
KR101125504B1 (ko) 클럭 신호가 임베딩된 단일 레벨의 데이터 전송을 이용한 디스플레이 구동 시스템
JP5700706B2 (ja) 液晶表示装置及びその駆動方法
US20060092100A1 (en) Display controlling device and controlling method
US8314763B2 (en) Display device transferring data signal with clock
KR20160129934A (ko) 표시장치
KR101891710B1 (ko) 클럭 임베디드 인터페이스 장치 및 이를 이용한 영상 표시장치
KR20090105334A (ko) 디스플레이
KR101337897B1 (ko) 표시장치의 구동 제어회로
KR101318272B1 (ko) 데이터 전송 장치 및 이를 이용한 평판 표시 장치
KR101607155B1 (ko) 표시 장치 및 이의 구동 방법
US8674924B2 (en) Display device comprising normal/multiplied speed drive switching circuit and data driver and operating method thereof
US20120154356A1 (en) Timing Controller, Source Driving Device, Panel Driving Device, Display Device and Driving Method
US9054939B2 (en) Method of processing data and a display apparatus performing the method
KR102547086B1 (ko) 표시장치 및 이의 구동방법
KR20090096999A (ko) 타이밍 콘트롤러와 디스플레이 구동회로 사이의 전송 채널주파수를 감소시킨 디스플레이 장치
CN115083324A (zh) 时序控制装置以及其控制方法
US20100166129A1 (en) Data transmitting device and data receiving device
US9928799B2 (en) Source driver and operating method thereof for controlling output timing of a data signal
KR101696467B1 (ko) 액정표시장치
KR101552983B1 (ko) 액정표시장치의 구동회로 및 구동방법
US9984613B2 (en) Substrate and display apparatus
KR20150063796A (ko) 평판 표시 장치의 데이터 인터페이스 장치 및 방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20100702

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME RS

17Q First examination report despatched

Effective date: 20121001

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20150924