EP2347455A2 - Composant émettant un rayonnement et procédé pour sa fabrication - Google Patents

Composant émettant un rayonnement et procédé pour sa fabrication

Info

Publication number
EP2347455A2
EP2347455A2 EP09771686A EP09771686A EP2347455A2 EP 2347455 A2 EP2347455 A2 EP 2347455A2 EP 09771686 A EP09771686 A EP 09771686A EP 09771686 A EP09771686 A EP 09771686A EP 2347455 A2 EP2347455 A2 EP 2347455A2
Authority
EP
European Patent Office
Prior art keywords
radiation
semiconductor chip
layer
contact
emitting component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP09771686A
Other languages
German (de)
English (en)
Other versions
EP2347455B1 (fr
Inventor
Siegfried Herrmann
Sebastian Taeger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2347455A2 publication Critical patent/EP2347455A2/fr
Application granted granted Critical
Publication of EP2347455B1 publication Critical patent/EP2347455B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G61/00—Macromolecular compounds obtained by reactions forming a carbon-to-carbon link in the main chain of the macromolecule
    • C08G61/02—Macromolecular compounds containing only carbon atoms in the main chain of the macromolecule, e.g. polyxylylenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • a radiation-emitting component according to claim 1 is specified.
  • a common problem of radiation emitting devices is the generation of efficient encapsulation of these devices.
  • Encapsulation is used on the one hand have a very good barrier effect against, for example, acids, alkalis, gases and water vapor, but at the same time form very thin uniform layers and be transparent to the radiation emitted by the device.
  • An embodiment of the invention relates to a radiation-emitting component, comprising a carrier, a semiconductor chip arranged on the carrier, wherein the semiconductor chip has an active layer for generating electromagnetic radiation and a radiation exit surface, a first and a second contact structure for electrically contacting the semiconductor chip, a first and a second contact layer, wherein the semiconductor chip is electrically conductively connected to the first contact structure via the first contact layer and to the second contact structure via the second contact layer, a passivation layer arranged on the semiconductor chip, wherein the passivation layer comprises or consists of an organic polymer of general formula (I):
  • radicals R 1 to R 16 may each independently be H, CH 3 , F, Cl or Br, and n has a value of 10 to 500,000.
  • a passivation layer comprising an organic polymer having the above formula has a good one hydrophobic and chemical resistance.
  • the passivation layer thus has a good barrier effect against, for example, acids, alkalis, gases and water vapor.
  • the passivation layer is furthermore transparent to the radiation emitted by the component.
  • Another advantage of the passivation layer is that very thin and uniform layers can be formed.
  • the passivation layer has a good temperature resistance. It also has good resistance to mechanical stress such as abrasion. By virtue of these properties, the parts of the radiation-emitting component which are coated with the passivation layer are very well protected against environmental influences.
  • R 1 , R 2 , R 7 , R 8 , R 9 , R 10 , R 15 and R 16 are each H.
  • n has a value of 100 to 100,000.
  • radicals are present on one aromatic, they are preferably the same radicals.
  • An organic polymer of this formula has a particularly good barrier effect against environmental influences.
  • the passivation layer comprises an organic polymer of the formula
  • a passivation layer comprising such an organic polymer has a very good dielectric strength, in addition to which the dielectric constant is independent of the frequency of the electric field. Furthermore, with a passivation layer comprising such an organic polymer, particularly uniform layers can be formed. This material is particularly well small spaces, gaps and edges filled. The passivation layer is also particularly suitable as an insulating layer due to the dielectric
  • the passivation layer comprises an organic polymer of the formula:
  • a passivation layer comprising the above organic polymer has very good electrical properties such as also physical properties. Thus, the passivation layer has a very good barrier to moisture and gases.
  • a passivation layer comprising such an organic polymer adheres more quickly to the surface to which it is applied as compared to the corresponding organic polymer which does not comprise chlorine atoms.
  • the passivation layer comprises an organic polymer of the formula:
  • a passivation layer comprising an organic polymer whose aromatic has two chlorine atoms has a higher thermal stability than the passivation layers whose organic polymers comprise aromatics which have only one or no chlorine atom.
  • the passivation layer represents, at least in some areas, the outermost layer of the component.
  • the passivation layer may represent the outer layer of the component.
  • outer layer is to be understood as meaning a layer which, in the case of a layer sequence of, for example, a plurality of horizontal layers superimposed on one another, represents the uppermost or lowermost layer at least in partial regions.
  • the outer layer is a layer which is arranged between other layers and has contact with the environment only on the vertical side surfaces.
  • the passivation layer is arranged on the radiation exit surface.
  • the layer thickness in this embodiment may be in a range from 100 nm to 2000 nm, preferably in a range from 200 nm to 1000 nm.
  • the passivation layer Due to the transparency of the passivation layer, it can be applied to the radiation exit surface of the semiconductor chip. Thus, the semiconductor chip can be encapsulated by the passivation layer against environmental influences.
  • the passivation layer is arranged directly on the radiation exit surface.
  • At least one optical element is arranged on the radiation exit surface of the semiconductor chip.
  • the radiation emitted by the semiconductor chip can be spatially redirected or its wavelength modified by the optical element.
  • the optical element comprises a conversion layer or a filter.
  • the radiation emitted by the semiconductor chip can be modified in its wavelength. This can also be done, for example, only with a certain wavelength range of the emitted radiation.
  • the modification can be carried out, for example, by absorption of the radiation by a conversion substance, which
  • the filter may be an angle or edge filter.
  • the passivation layer is arranged at least on partial regions of the surface of the optical element facing away from the semiconductor chip.
  • the semiconductor chip not only the semiconductor chip but also additionally the optical element arranged on the semiconductor chip is encapsulated by the passivation layer.
  • a compensation layer is additionally arranged between the semiconductor chip and the optical element.
  • the compensation layer here represents a special form of
  • Passivianss slaughter and thus includes the same substances as the passivation layer. This can serve, for example, for straightening the surface of the semiconductor chip.
  • the passivation layer electrically insulates the first contact structure from the second contact structure.
  • the passivation layer can also be used as an electrical insulator.
  • the first can be electrically insulated from the second contact structure.
  • the passivation layer electrically insulates the second contact layer against the first contact structure.
  • Passivation layer not only has very good electrical insulating properties, but also very thin and uniform layers can be formed with her, It is also possible to fill in small gaps with the passivation layer. Furthermore, it is also possible to guide contact layers in the manner of a ramp over a base, which is formed by the passivation layer. Under ramp-like is to be understood that the
  • Contact layer is passed directly over another layer without a gap between the contact layer and the layer over which it is guided is formed. This makes it possible to realize particularly flat components. In this embodiment, which has such a contact ramp, no contact wire (a so-called bonding wire) is needed.
  • the second contact layer is on the
  • Radiation exit surface of the semiconductor chip arranged in a frame Radiation exit surface of the semiconductor chip arranged in a frame.
  • the semiconductor chip has a more uniform voltage supply than when the contact layer is only on one side of the
  • Radiation exit surface would be arranged.
  • the semiconductor chip is supplied with more uniform voltage, it has a more homogeneous radiation, compared with a semiconductor chip, which is supplied only at certain points or via an edge with voltage.
  • the frame-shaped arrangement of the second contact layer on the surface of the semiconductor chip improves the current widening of the semiconductor chip, which improves the efficiency of the radiation generation.
  • the frame-shaped contact geometry of the second contact layer is suitable especially for chips with a side length of less than 400 ⁇ m.
  • the second contact layer has contact lands which are arranged on the radiation exit area of the semiconductor chip.
  • the second contact layer also makes it possible to provide the semiconductor chip with homogeneous voltage, which in turn leads to a homogeneous radiation of the semiconductor chip.
  • the contact webs can be transparent to the emitted radiation.
  • the second contact layer is preferably additionally arranged in the shape of a frame on the surface of the semiconductor chip, wherein contact webs are arranged in this frame contact, which preferably do not intersect on the surface of the semiconductor chip and particularly preferably run parallel to each other.
  • the contact bars are in partial areas in direct contact with the frame contact.
  • the contact webs improve the current spreading of the semiconductor chip, whereby larger chip dimensions are possible.
  • Such a contact structure is particularly advantageous for chips with a side length of greater than 400 microns.
  • a first and a second plated-through hole are present in the carrier, wherein the first plated-through hole is electrically conductively connected to the first contact structure and the second plated-through hole is electrically conductively connected to the second contact structure.
  • very flat components can be realized.
  • Contact areas can be soldered directly to a printed circuit board, for example. As a result, very dense assemblies are possible, which reduces the space required. This allows a high packing density.
  • the component is formed as a thin-film chip.
  • the semiconductor body is a thin-film light-emitting diode chip. In particular, he points to his
  • the first and the second connection layer are arranged at least in places between the semiconductor layer sequence and the carrier substrate.
  • Radiation-generating semiconductor layer sequence which is in particular a radiation-generating epitaxial layer sequence, is a reflective Applied or formed layer that reflects back at least a portion of the electromagnetic radiation generated in the semiconductor layer sequence in this;
  • the thin-film light-emitting diode chip has a carrier element, which is not the growth substrate on which the semiconductor layer sequence has been epitaxially grown, but a separate carrier element which has subsequently been attached to the semiconductor layer sequence;
  • the semiconductor layer sequence has a thickness in the range of 20 ⁇ m or less, in particular in the range of 10 ⁇ m or less;
  • the semiconductor layer sequence is free of a growth substrate.
  • free from a growth substrate means that a growth substrate which may be used for growth is removed from the semiconductor layer sequence or at least heavily thinned. In particular, it is then thinned such that it alone or together with the epitaxial layer sequence is not self-supporting. The remainder of the highly thinned growth substrate is in particular unsuitable as such for the function of a growth substrate; and
  • the semiconductor layer sequence contains at least one semiconductor layer with at least one surface which has a mixing structure which, in the ideal case, leads to an approximately ergodic distribution of the light in the semiconductor layer sequence, that is to say it has a possibly ergodically stochastic scattering behavior.
  • a basic principle of a thin-film light-emitting diode chip is described, for example, in the publication I. Schnitzer et al. , Appl. Phys. Lett. 63 (16) 18 October 1993, pages 2174 - 2176, the disclosure of which is hereby incorporated by reference.
  • Examples of thin-film light-emitting diode chips are described in the publications EP 0905797 A2 and WO 02/13281 A1, the disclosure content of which is hereby also incorporated by reference.
  • the device appears completely white.
  • Passivation layer a change in the color impression through the passivation layer can be avoided.
  • passivation layer components such as LED chips
  • the passivation layer components can be encapsulated, whose contacts are formed both as intermediate layers, as well as components in which the contacts are for electrical contacting on the surface.
  • the passivation layer may, for example in the case that it is arranged on the chip flanks, also be used as electrical flashover protection against an electrically conductive base body / carrier. Furthermore, the passivation layer can also be used for passivation for a mirror layer, for example in the semiconductor chip.
  • a variant for producing the radiation-emitting component comprises the method steps of providing a carrier which has a first and a second contact structure as method step A), the mechanical and electrically conductive connection of the semiconductor chip to the first contact structure via the first contact layer as method step B) mechanically and electrically conductively connecting the semiconductor chip to the first contact structure via the second contact layer as method C), applying the passivation layer to at least partial areas of the semiconductor chip as process step D), wherein a material comprising an organic polymer is used for the passivation layer general formula (I):
  • radicals R 1 to R 16 may each independently be H, CH 3 , F, Cl or Br and n has a value of 10 to 500,000.
  • a radiation-emitting device as claimed in claim 1 can be produced.
  • components can be realized which are very well protected against environmental influences such as acids, alkalis, gases and water vapor.
  • very flat components can be realized with the aid of this method. Further advantageous embodiments of the method result analogously to the advantageous embodiments of the radiation-emitting component.
  • the passivation layer is applied using a plasma method.
  • the corresponding dimer of the respective polymer can serve as the starting substance.
  • This can for example be thermally split into the monomer, from which the chain formation then takes place to the polymer.
  • the polymerization then takes place at a temperature which is lower than that for
  • the polymerization can be carried out at a pressure in the range of 0.05 to 0.5 mbar.
  • the condensation of the polymer can then take place directly on the surface to be coated.
  • the deposition of the passivation layer can also be done by chemical vapor deposition (CVD) or plasma assisted chemical vapor deposition (PECVD).
  • CVD chemical vapor deposition
  • PECVD plasma assisted chemical vapor deposition
  • Figure 1 shows a schematic side view of a
  • Embodiment of the radiation-emitting device in which the second contact layer is formed as a ramp is formed as a ramp.
  • FIG. 2 shows a schematic plan view of an embodiment of the radiation-emitting component wherein partial regions of the second contact layer are formed as contact webs.
  • Figure 3 shows a schematic plan view of an embodiment of the radiation-emitting device in which the MixStege are connected frame-shaped.
  • FIG. 4 shows a schematic plan view of a further embodiment of the radiation-emitting component which has a symmetrical construction.
  • FIG. 5 shows a schematic side view of an embodiment of the radiation-emitting component in which the entire outer surface, with the exception of the contact surface, is surrounded by the passivation layer.
  • FIG. 6 shows a schematic side view of an embodiment of the radiation-emitting component which has an optical element in the form of a converter.
  • Figure 7a shows a schematic side view of a
  • Embodiment of a radiation-emitting component which has an optical element in the form of pyramid filters.
  • FIG. 7b shows a schematic side view of an embodiment of the radiation-emitting component which has a passive component.
  • the sequence of figures 8a to 8d shows a plurality of radiation-emitting components in different process stages.
  • FIGS. 9a to 9d shows a radiation-emitting component in a schematic plan view in various process stages.
  • FIG. 1 shows a schematic side view of an embodiment of the radiation-emitting component.
  • the first contact structure 4a and the second contact structure 4b are arranged.
  • the two contact structures are electrically insulated from one another by the passivation layer 5.
  • the semiconductor chip 2 is connected both mechanically and electrically conductively to the first contact structure 4a via the first contact layer 21.
  • the semiconductor chip 2 has a radiation exit surface 3.
  • the semiconductor chip 2 is electrically conductively connected to the second contact structure 4b at the radiation exit surface 3 via the second contact layer 6.
  • the second contact layer 6 is guided in a ramp over the passivation layer 5, wherein the passivation layer 5 is the second
  • Contact layer 6 in this case electrically insulated against the first contact structure 4a.
  • the areas of the radiation exit surface 3 which are not in contact with the second contact layer 6 and the side surfaces of the semiconductor chip 2 are coated with the passivation layer 5.
  • the passivation layer 5 is transparent to the radiation emitted by the semiconductor chip 2, the radiation can be emitted via the radiation exit surface 3 through the passivation layer 5.
  • optical elements By contacting the semiconductor chip 2, which can be done without bonding wire, optical elements can be arranged close to the chip on the semiconductor chip 2.
  • the carrier 1 preferably contains a ceramic, silicon or aluminum nitride.
  • the carrier 1 may be an intermetallic ceramic, a metal or a metal
  • Metal alloy with an electrically insulating layer disposed thereon, such as a dielectric include.
  • the semiconductor chip 2 has an active layer, which may have a pn junction, a double heterostructure, a single quantum well structure (SQW) or a multiple quantum well structure (MQW) for generating radiation.
  • an active layer which may have a pn junction, a double heterostructure, a single quantum well structure (SQW) or a multiple quantum well structure (MQW) for generating radiation.
  • the semiconductor chip 2 is preferably based on a nitride, a phosphite or an arsenide compound semiconductor. "Based on nitride, phosphite or Arsenidharmschleitern” means in the present context that the active epitaxial layer sequence or at least one layer thereof a III / V semiconductor material in particular with the composition In x GayAli_ x _yP or In x GayAli_ x _yN or In x GayAli_ x _y As, each with O ⁇ x ⁇ l, O ⁇ y ⁇ l and x + y ⁇ 1.
  • the semiconductor chip 2 of the radiation-emitting component has no growth substrate.
  • the semiconductor chip 2 is thus designed as a substrateless semiconductor chip.
  • a substrathom semiconductor chip 2 results in a particularly low height of the device with advantage.
  • the semiconductor chip 2 preferably has a height of less than 100 ⁇ m, particularly preferably less than 40 ⁇ m.
  • the dimension of the component can thus be almost in the region of the thickness of an epitaxial layer sequence.
  • the first contact layer 21 preferably serves not only for the electrical contacting of the semiconductor chip 2, but can also assume the function of an optical mirror. This means that the first contact layer 21 preferably reflects back the radiation emitted by the semiconductor chip 2, which is emitted in the direction of the carrier 1, in the direction of the radiation exit surface 3 of the semiconductor chip 2.
  • the second contact layer 6 is transparent and is in particular a TCO layer (TCO: Transparent Conductive Oxide).
  • TCO Transparent Conductive Oxide
  • the second contact layer particularly preferably comprises IZO (indium zinc oxide), ITO (indium tin oxide) or ZnO (zinc oxide).
  • the second contact layer 6 has a thickness in a range between 50 nm inclusive and 300 nm inclusive.
  • the semiconductor chip 2 preferably has a height of less than 40 ⁇ m.
  • FIG. 2 shows the schematic plan view of two radiation-emitting components. The two components are identical and arranged on the same support 1. In each case a first contact structure 4a is arranged on the carrier 1 via which the semiconductor chip or the first contact layer 21 which is arranged between the semiconductor chip 2 and the first contact structure 4a can be contacted. The upper side of the semiconductor chip 2 is electrically conductively connected via the second contact layer 6 to the second contact structure 4a.
  • the second contact structure 4a is electrically conductively connected via the second contact layer 6 to the second contact structure 4a.
  • Contact layer 6 is in this case formed on the radiation exit surface 3 as contact webs 61. These contact webs 61 enable the semiconductor chip 2 to be supplied more homogeneously with voltage, which leads to a more homogeneous emission of the semiconductor chip 2.
  • the two semiconductor chips 2 are each surrounded in a frame shape by the passivation layer 5. As shown in FIG. 1, the second contact layer 6 is guided in a ramp shape over a partial region of the passivation layer 5 to the radiation exit surface 3.
  • FIG. 3 shows a schematic plan view of a further embodiment of the radiation-emitting component.
  • a first contact structure 4a and a second contact structure 4b are arranged on the carrier 1.
  • Radiation exit surface 3 of the semiconductor chip 2 is electrically conductively connected to the second contact structure 4b via the second contact layer 6.
  • the arranged on the radiation exit surface 3 portion of the second contact layer 6 is in partial areas as
  • Contact webs 61 formed and in addition as a frame which connects the outer ends of the contact webs 61 with each other.
  • the Semiconductor chip 2 homogeneously supplied with voltage.
  • the semiconductor chip 2 is surrounded by the passivation layer 5.
  • the passivation layer 5 also represents the base for the second contact layer 6, which is guided by the second contact structure 4b to the radiation exit surface 3.
  • FIG. 4 shows an embodiment of the radiation-emitting component in the schematic plan view. This embodiment is characterized by having a symmetrical structure with respect to the broken line.
  • the second contact layer 6 is again formed here on the radiation exit surface 3 of the semiconductor chip 2 as contact webs 61.
  • the symmetrical construction of the component ensures a particularly homogeneous
  • Embodiment there are in each case also embodiments in which the radiation exit surface 3 is completely coated with the passivation layer 5 at least in the regions in which there are no webs or contact layers. For clarity, this is not shown in the figures. Thus, the semiconductor chip 2 is completely protected against environmental influences.
  • the contact webs 61 are also provided with a passivation layer 5, so that the entire area above the
  • FIG. 5 shows an exemplary embodiment of the radiation-emitting component in the schematic side view.
  • the carrier 1 has a first through-connection 8a and a second through-connection 8b. Through the vias, the first
  • Contact structure 4a and the second contact structure 4b are electrically conductively contacted from the bottom of the device ago.
  • the second contact layer 6 is shaped like a frame in the region where it extends on the radiation exit surface 3 of the semiconductor chip 2.
  • the radiation exit surface 3 is electrically conductively connected to the second contact structure 4b via the second contact layer.
  • the component shown in Figure 5 is preferably formed by means of the first and the second via 8a, 8b as a surface mountable device.
  • the embodiment shown in Figure 6 of the schematic side view has a similar structure, as the embodiment shown in Figure 5.
  • the embodiment shown in FIG. 6 additionally has an optical element 9.
  • the embodiment shown in FIG. 6 is a conversion layer.
  • This conversion layer 9 can comprise, for example, a converting substance, by means of which the radiation emitted by the semiconductor chip 2 or only wavelength ranges of this radiation in its Wavelength is modified. This can be done, for example, by absorbing the radiation emitted by the semiconductor chip 2 from the conversion substance and by emitting a radiation having a different wavelength from the conversion substance than the radiation which was absorbed by the conversion substance.
  • the entire radiation emitted by the semiconductor chip 2 passes through the optical element 9.
  • the embodiment shown in Figure 7a has a similar structure, as the embodiment which is shown in Figure 5. However, the embodiment illustrated in FIG. 7 a additionally has an optical element 9. On the radiation exit surface 3 is a compensation layer 15 on which the optical element 9 is arranged.
  • the leveling layer 15 may inter alia for planarization of the surface of the
  • Radiation exit surface 3 serve.
  • Passivation layer 5 provided.
  • the optical element 9 is a pyramid filter in this embodiment.
  • the passivation layer 5 can also have a uniform layer thickness in the region in which it runs on the pyramid filters. With the aid of these filters, the radiation emitted by the semiconductor chip 2 can be deflected in its spatial direction.
  • the embodiment shown in Figure 7b corresponds to the embodiment as shown in Figure 7a, but additionally includes a passive device 100.
  • This passive device 100 is disposed on the second contact structure and also entirely of the Passivation layer 5 enclosed.
  • the passive device 100 may be, for example, a protective diode or a resistor.
  • FIG. 8 a a first contact structure 4 a is arranged on the carrier 1, and a semiconductor chip 2, which is connected to the first contact structure 4 a both mechanically and electrically conductively via the first contact layer 21.
  • the entire carrier 1 and the three components are each completely surrounded by the passivation layer 5.
  • the passivation layer 5 has been exposed above the semiconductor chip 2 and above the first contact structure 4a in a partial region on which no first contact layer 21 is arranged.
  • the removal of the passivation layer 5 can be carried out, for example, by means of RIE plasma etching ("reactive ion etching") with a fluorinated gas (for example NF 3 , CHF 3 , CF 4 or SF 6 ).
  • an optical element 9 was applied to the semiconductor chip 2.
  • the optical element 9 is a conversion layer in this embodiment.
  • the application of the conversion layer can in this case be carried out, for example, by means of platelets which comprise a converter material.
  • the thickness of the conversion layer can be, for example, 20 ⁇ m.
  • the thickness would be, for example, 100 microns.
  • a partial region of the passivation layer 5 which extends over the optical element 9 has been removed again.
  • This removal of the passivation layer can be effected, for example, by means of RIE plasma etching ("reactive ion etching") with a fluorinated gas
  • RIE plasma etching reactive ion etching
  • fluorinated gas By exposing the optical element 9, the absorption of the emitted radiation can be reduced.
  • FIGS. 9a to 9d an exemplary embodiment of the radiation-emitting component in four different process stages is shown schematically in plan view.
  • FIG. 9a shows the carrier 1 on which the first contact structure 4a and the second contact structure 4b are respectively illustrated for components which emit two radiation-emitting components.
  • FIG. 9b shows an exemplary embodiment which could emerge, for example, from the components illustrated in FIG. 9a, in which a semiconductor chip 2 was applied in each case to a partial area of the first contact structure 4a.
  • the application of the semiconductor chip 2 can be done for example by bonding, soldering or gluing.
  • a first contact layer 21 can be arranged between the semiconductor chip 2 and the first contact structure 4a.
  • the process stage shown in FIG. 9c can be obtained, for example, from the process stage as shown in FIG. 9b is shown, in that a passivation layer 5 has been applied.
  • the passivation layer 5 encloses the semiconductor chips 2 in each case.
  • the passivation layer 5 can be deposited, for example, by means of chemical vapor deposition (CVD), preferably by means of plasma-assisted vapor deposition (PECVD).
  • the process stage shown in FIG. 9d corresponds to the exemplary embodiment, as shown in FIG.
  • the second contact layer 6 is formed as contact webs 61 in the subregions in which it extends on the semiconductor chip 2.
  • the invention is not limited by the description based on the embodiments of this, but includes each new feature and any combination of features, which in particular includes any combination of features in the claims, even if this feature or this combination itself is not explicitly in the

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Medicinal Chemistry (AREA)
  • Polymers & Plastics (AREA)
  • Organic Chemistry (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Polyoxymethylene Polymers And Polymers With Carbon-To-Carbon Bonds (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un composant émettant un rayonnement, avec un support, avec une puce de semi-conducteur placée sur le support, la puce de semi-conducteur comprenant une couche active pour la production d'un rayonnement électromagnétique et une surface de sortie du rayonnement, avec une première et une deuxième structure de contact pour le contactage électrique de la puce de semi-conducteur et avec une première et une deuxième couche de contact. La puce de semi-conducteur est reliée dans une liaison conductrice électriquement par la première couche de contact à la première structure de contact et par la deuxième couche de contact à la deuxième structure de contact. Sur la puce de semi-conducteur est disposée une couche de passivation, qui comprend un polymère organique de formule générale (I), où les radicaux R1 à R16 peuvent être, indépendamment les uns des autres, H, CH3, F, C1 ou Br et où n a une valeur de 10 à 500 000.
EP09771686A 2008-11-14 2009-11-05 Composant émettant un rayonnement et procédé pour sa fabrication Active EP2347455B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008057350A DE102008057350A1 (de) 2008-11-14 2008-11-14 Strahlungsemittierendes Bauelement und Verfahren zu dessen Herstellung
PCT/DE2009/001571 WO2010054628A2 (fr) 2008-11-14 2009-11-05 Composant émettant un rayonnement et procédé pour sa fabrication

Publications (2)

Publication Number Publication Date
EP2347455A2 true EP2347455A2 (fr) 2011-07-27
EP2347455B1 EP2347455B1 (fr) 2013-03-27

Family

ID=42105044

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09771686A Active EP2347455B1 (fr) 2008-11-14 2009-11-05 Composant émettant un rayonnement et procédé pour sa fabrication

Country Status (7)

Country Link
US (1) US8552459B2 (fr)
EP (1) EP2347455B1 (fr)
JP (1) JP5538416B2 (fr)
KR (1) KR101609012B1 (fr)
CN (1) CN102216365B (fr)
DE (1) DE102008057350A1 (fr)
WO (1) WO2010054628A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010031732A1 (de) * 2010-07-21 2012-01-26 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102010033963A1 (de) * 2010-08-11 2012-02-16 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements
US8653542B2 (en) * 2011-01-13 2014-02-18 Tsmc Solid State Lighting Ltd. Micro-interconnects for light-emitting diodes
DE102011010504A1 (de) * 2011-02-07 2012-08-09 Osram Opto Semiconductors Gmbh Optoelektrischer Halbleiterchip
DE102011013821B4 (de) 2011-03-14 2024-05-23 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung zumindest eines optoelektronischen Halbleiterchips
DE102011113428A1 (de) * 2011-09-14 2013-03-14 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102012209325B4 (de) * 2012-06-01 2021-09-30 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronisches Modul
DE102012109083A1 (de) * 2012-09-26 2014-03-27 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zu dessen Herstellung
EP2830087A1 (fr) * 2013-07-26 2015-01-28 Hamilton Sundstrand Corporation Procédé d'interconnexion de composants électriques sur un substrat
KR102311791B1 (ko) * 2015-10-16 2021-10-08 한국전기연구원 아민계 폴리머를 포함한 다이오드 제조방법
DE102017112223A1 (de) 2017-06-02 2018-12-06 Osram Opto Semiconductors Gmbh Halbleiterlaser-Bauteil und Verfahren zur Herstellung eines Halbleiterlaser-Bauteils
CN107978613A (zh) * 2017-12-15 2018-05-01 中芯集成电路（宁波）有限公司 半导体感光器件及其感光表面处理方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9018698D0 (en) * 1990-08-24 1990-10-10 Lynxvale Ltd Semiconductive copolymers for use in electroluminescent devices
US5973337A (en) * 1997-08-25 1999-10-26 Motorola, Inc. Ball grid device with optically transmissive coating
EP2169733B1 (fr) 1997-09-29 2017-07-19 OSRAM Opto Semiconductors GmbH Source lumineuse à semi-conducteur
JP3641122B2 (ja) * 1997-12-26 2005-04-20 ローム株式会社 半導体発光素子、半導体発光モジュール、およびこれらの製造方法
US20020017652A1 (en) 2000-08-08 2002-02-14 Stefan Illek Semiconductor chip for optoelectronics
US6740906B2 (en) * 2001-07-23 2004-05-25 Cree, Inc. Light emitting diodes including modifications for submount bonding
JP2003133589A (ja) * 2001-10-23 2003-05-09 Mitsubishi Cable Ind Ltd ＧａＮ系半導体発光ダイオード
DE102004029412A1 (de) * 2004-02-27 2005-10-13 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterchip und Verfahren zur Herstellung eines solchen Halbleiterchips
EP1774598B1 (fr) * 2004-06-30 2011-09-14 Cree, Inc. Procedes d'encapsulation en boitier-puce de dispositifs electroluminescents et dispositifs electroluminescents encapsules en boitier-puce
JP4457826B2 (ja) * 2004-09-22 2010-04-28 三菱化学株式会社 窒化物半導体を用いた発光ダイオード
DE102004050371A1 (de) * 2004-09-30 2006-04-13 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit einer drahtlosen Kontaktierung
US8318519B2 (en) * 2005-01-11 2012-11-27 SemiLEDs Optoelectronics Co., Ltd. Method for handling a semiconductor wafer assembly
JP4692053B2 (ja) * 2005-04-15 2011-06-01 セイコーエプソン株式会社 画像登録装置、画像確認方法、および画像プレビュープログラム
KR101047683B1 (ko) * 2005-05-17 2011-07-08 엘지이노텍 주식회사 와이어 본딩이 불필요한 발광소자 패키징 방법
CN100480168C (zh) * 2005-07-07 2009-04-22 上海交通大学 反应离子深刻蚀加工微结构的侧壁钝化方法
DE102005063106A1 (de) * 2005-12-30 2007-07-05 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Optoelektronischer Halbleiterchip und optoelektronisches Bauelement mit solch einem Halbleiterchip
JP4203087B2 (ja) * 2006-07-25 2008-12-24 株式会社沖データ 半導体複合装置、ｌｅｄプリントヘッド及び画像形成装置
WO2008016110A1 (fr) * 2006-08-04 2008-02-07 Mitsubishi Chemical Corporation Couche isolante, dispositif électronique, transistor à effet de champ, et polyvinylthiophénol
DE102006045702A1 (de) 2006-09-27 2008-04-03 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil
JP4846506B2 (ja) * 2006-10-10 2011-12-28 株式会社フジクラ 発光装置およびその製造方法
WO2008156121A1 (fr) * 2007-06-21 2008-12-24 Idemitsu Kosan Co., Ltd. Transistor à couches minces organique et transistor électroluminescent à couches minces organique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2010054628A2 *

Also Published As

Publication number Publication date
WO2010054628A2 (fr) 2010-05-20
US20110278621A1 (en) 2011-11-17
WO2010054628A3 (fr) 2010-12-23
JP2012508971A (ja) 2012-04-12
US8552459B2 (en) 2013-10-08
KR20110095342A (ko) 2011-08-24
CN102216365B (zh) 2013-07-03
CN102216365A (zh) 2011-10-12
EP2347455B1 (fr) 2013-03-27
DE102008057350A1 (de) 2010-05-20
JP5538416B2 (ja) 2014-07-02
KR101609012B1 (ko) 2016-04-04

Similar Documents

Publication Publication Date Title
EP2347455B1 (fr) Composant émettant un rayonnement et procédé pour sa fabrication
EP2002176B1 (fr) Phare avant optoélectronique
EP1769540B1 (fr) Systeme de couches reflechissantes comportant une pluralite de couches, destine a etre applique sur un materiau semi-conducteur compose iii/v
EP2193553A1 (fr) Puce semi-conductrice optoélectronique, composant optoélectronique et procédé de fabrication d'un composant optoélectronique
DE102010051286A1 (de) Optoelektronischer Halbleiterchip und Verfahren zu dessen Herstellung
WO2008101524A1 (fr) Liaison électrique pour structures semi-conductrices, son procédé de production, et son utilisation dans un élément d'éclairage
WO2016156329A1 (fr) Puce semi-conductrice optoélectronique, composant semi-conducteur optoélectronique et procédé de fabrication d'une puce semi-conductrice optoélectronique
WO2012110147A1 (fr) Procédé de fabrication d'au moins un composant semi-conducteur optoélectronique
DE102008028886B4 (de) Strahlungsemittierendes Bauelement und Verfahren zur Herstellung eines strahlungsemittierenden Bauelements
DE102014108373A1 (de) Optoelektronischer Halbleiterchip
WO2016180897A1 (fr) Procédé de fabrication de composants optoélectroniques et composant optoélectronique à montage en surface
DE102012221191B4 (de) Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements
DE102015107588B4 (de) Verfahren zur Herstellung optoelektronischer Bauelemente und oberflächenmontierbares optoelektronisches Bauelement
DE102006055884B4 (de) Strahlungsemittierende Vorrichtung und Verfahren zu ihrer Herstellung
WO2012010377A1 (fr) Composant optoélectronique
WO2014124854A1 (fr) Procédé de fabrication d'un composant à semi-conducteur optoélectronique
DE102013208223B4 (de) Verfahren zum Herstellen eines optoelektronischen Bauelements
EP2619807B1 (fr) Puce à semi-conducteur optoélectronique et son procédé de production
DE102004047061B4 (de) Optoelektronisches Bauelement und Verfahren zum Herstellen eines optoelektronischen Bauelements
DE102015107591B4 (de) Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
DE102017117164A1 (de) Optoelektronischer Halbleiterchip, Hochvolthalbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
DE102010044987A1 (de) Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung
WO2010043205A1 (fr) Conducteur de raccordement électrique pour un élément semi-conducteur, élément semi-conducteur et procédé de fabrication d'un conducteur de raccordement électrique

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20110216

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

AX Request for extension of the european patent

Extension state: AL BA RS

DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 502009006672

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0033560000

Ipc: H01L0033440000

RIC1 Information provided on ipc code assigned before grant

Ipc: C08G 61/10 20060101ALI20120404BHEP

Ipc: C08G 61/02 20060101ALI20120404BHEP

Ipc: H01L 31/02 20060101ALI20120404BHEP

Ipc: H01L 33/44 20100101AFI20120404BHEP

Ipc: H01L 31/0216 20060101ALI20120404BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 603903

Country of ref document: AT

Kind code of ref document: T

Effective date: 20130415

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502009006672

Country of ref document: DE

Effective date: 20130523

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130627

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130627

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130628

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130729

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130727

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130708

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

26N No opposition filed

Effective date: 20140103

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502009006672

Country of ref document: DE

Effective date: 20140103

BERE Be: lapsed

Owner name: OSRAM OPTO SEMICONDUCTORS G.M.B.H.

Effective date: 20131130

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131130

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131130

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131105

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131105

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20091105

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130327

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 7

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 603903

Country of ref document: AT

Kind code of ref document: T

Effective date: 20141105

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20141105

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 8

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 9

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230825

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20231123

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20231120

Year of fee payment: 15

Ref country code: DE

Payment date: 20231121

Year of fee payment: 15