WO2010043205A1 - Conducteur de raccordement électrique pour un élément semi-conducteur, élément semi-conducteur et procédé de fabrication d'un conducteur de raccordement électrique - Google Patents

Conducteur de raccordement électrique pour un élément semi-conducteur, élément semi-conducteur et procédé de fabrication d'un conducteur de raccordement électrique Download PDF

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Publication number
WO2010043205A1
WO2010043205A1 PCT/DE2009/001414 DE2009001414W WO2010043205A1 WO 2010043205 A1 WO2010043205 A1 WO 2010043205A1 DE 2009001414 W DE2009001414 W DE 2009001414W WO 2010043205 A1 WO2010043205 A1 WO 2010043205A1
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WO
WIPO (PCT)
Prior art keywords
conductor
conductor layer
electrical connection
layer
connection conductor
Prior art date
Application number
PCT/DE2009/001414
Other languages
German (de)
English (en)
Inventor
Michael Zitzlsperger
Original Assignee
Osram Opto Semiconductors Gmbh
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Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2010043205A1 publication Critical patent/WO2010043205A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • the present application relates to an electrical connection conductor which is suitable for a semiconductor component, and to a method for producing an electrical connection conductor. Furthermore, a semiconductor component is specified with an electrical connection conductor.
  • leadframes are often used for the production of semiconductor components.
  • Another word for leadframe is leadframe, for example.
  • a leadframe has electrical connection leads for an electronic one
  • a leadframe often consists at least essentially of stamped copper sheet.
  • At least one semiconductor chip is often mechanically and electrically connected to the intended electrical connection conductors. Subsequently, the chip and a part of each of the leads are encapsulated with a capsule mass.
  • the electrical connection conductors protrude, for example laterally on opposite sides of the capsule mass out.
  • a particularly advantageous semiconductor component with the electrical connection conductor and a method for producing the electrical connection conductor should be specified.
  • An electrical connection conductor for a semiconductor component in particular for an optoelectronic semiconductor component, is specified.
  • This has a first conductor layer and a second conductor layer, which are interconnected via mutually facing main surfaces.
  • the first conductor layer, the second conductor layer or both the first and the second conductor layer has at least one thinned region in which its layer thickness is less than its maximum layer thickness.
  • Both the electrical connection conductor and each of the conductor layers per se are in particular self-supporting or self-supporting elements, that is to say they are dimensionally stable, in particular in a state in which they are free of further material, and can be moved and transported as such while retaining their shape.
  • Electrically conductive coatings such as thin metal coatings or thin layers of transparent, electrically conductive oxides deposited on material surfaces are not covered by the term "first conductor layer” or "second conductor layer”. This is especially true if the coating is in a mold in which it is not on another material applied, but is free of further material, would not be suitable for conventional processing due to lack of dimensional stability.
  • both the first conductor layer and the second conductor layer have a maximum thickness of at least 50 ⁇ m, preferably of at least 80 ⁇ m or at least 90 ⁇ m. That is, the conductor layer must have a thickness at least at one point which is at least as large as one of the specified thicknesses, the thickness being measured perpendicular to a main extension plane of the conductor layer.
  • the first conductor layer, the second conductor layer or both the first and the second conductor layer is a metal plate or has a metal plate.
  • the conductor layers each have a flat shape with opposing major surfaces, through
  • Side surfaces are interconnected. The side surfaces are each smaller than the main surfaces.
  • the electrical connection conductor can be formed with a plurality of additional properties which exceed conventional properties, such as electrical conductivity and, where appropriate, the suitability as a carrier for a semiconductor chip, go out.
  • the term "thinned area” does not imply any particular manufacturing process for the formation of such areas. It may be expedient, starting from a conductor layer with a constant thickness thinned areas, for example by removing material, for example by etching, or by impressing produce. However, this is not mandatory.
  • the conductor layer can be formed from the outset with thinner and thicker areas.
  • Thiinned area is generally defined by the layer thickness of the conductor layer being smaller than its maximum layer thickness, regardless of a manufacturing method. Conveniently, the thinned area has a thickness that is at least 10%, at least 25% or at least 35% less than the maximum thickness of the conductor layer. For example, a thinned region may have a thickness that is about 40% or about 50% less than the maximum thickness of the conductor layer.
  • Connecting conductor is formed on a first side of the electrical connection conductor, a capsule mass having a silicone. In other words, then the capsule mass forms a housing ground for the two conductor layers.
  • Silicones have the advantage, when irradiated by short-wave electromagnetic radiation, much lower than other capsule materials, for example optical resins, for aging. Furthermore, silicones have a significantly increased temperature resistance than, for example, epoxides. While
  • Epoxies can typically be heated to a maximum of about 150 ° C without damage, this is possible with silicones up to about 200 ° C.
  • the capsule composition consists of one or more of the silicones described herein, wherein additionally in the silicone radiation-reflecting or radiation-absorbing fillers such as TiC> 2 or carbon black can be introduced.
  • hybrid materials such as mixtures of silicones and epoxides or mixtures of silicones with other organic materials such as vinyl or acrylic-containing materials are also suitable for the capsule composition.
  • Hybrid materials of the type described are advantageously more radiation-stable and thermally more stable than pure epoxides and also have good mechanical properties (for example
  • the electrical connection conductor is at least partially free of the encapsulation compound and of electrically insulating material on a second side opposite the first side in an area laterally overlapping the encapsulation compound.
  • the electrical connection conductor is surface mountable.
  • the first conductor layer is part of a first leadframe and the second conductor layer is part of a second leadframe.
  • the two leadframes are linked together in a single, composite leadframe.
  • a leadframe which can also be called a leadframe, is a metal plate in which a plurality of electrical connection conductors for a semiconductor component are connected to one another, wherein the electrical connection conductors in the metal plate are formed and shaped by corresponding recesses in the plate.
  • leadframe is familiar to the person skilled in the art, in particular also to a person skilled in the field of optoelectronics.
  • conductor layer does not necessarily imply a one-piece layer. Rather, the conductor layer may also have a plurality of spaced apart, juxtaposed partial layers.
  • both the first and the second conductor layer each have at least one thinned region in which their layer thickness is less than their maximum layer thickness.
  • Sleiter allows regarding the formation of additional functions or special shapes and structures in the electric Anschlus'.
  • the thinned region of the first conductor layer overlaps laterally with the thinned region of the second conductor layer.
  • Lateral in the context of the present application means a direction, which runs parallel to a main extension plane of the corresponding conductor layer or the electrical connection conductor.
  • the first conductor layer has at least one opening.
  • the breakthrough may be, for example, a hole in the conductor layer. or a recess extending through the entire thickness of the conductor layer.
  • the recess may be open on at least one side, that is to say it is not necessarily surrounded on all sides laterally by material of the conductor layer.
  • the recess is a gap between the partial layers.
  • the first conductor layer has a thinned region which adjoins the opening.
  • the second conductor layer has a thinned region which overlaps laterally with the breakdown of the first conductor layer.
  • the breakthrough and the thinned area can completely overlap with each other. However, they may overlap only partially, that is, the aperture may be partially laterally offset from the thinned area.
  • an opening area of the opening in a plan view of the first conductor layer is smaller than a surface of the thinned area of the second conductor layer, which overlaps with the opening the top view.
  • Top view means a viewing angle perpendicular to a main plane of extension of one of the conductor layers or the electrical connection conductor.
  • the opening area of the opening is larger than the area of the thinned area of the second conductor layer overlapping with the opening, viewed in plan view.
  • the first conductor layer has a part which forms part of the second
  • Laterally projecting conductor layer wherein a region between the part of the first conductor layer and the laterally projected part of the second conductor layer is free of material of the electrical connection conductor. In particular, there is a gap between the parts.
  • the part of the first conductor layer adjoins the opening.
  • a part of the first conductor layer projects laterally beyond a part of the second conductor layer, wherein between the part of the first conductor layer and the part of the second conductor layer is a region free of material of the electrical
  • Connecting conductor is. In particular, there is a gap between the parts.
  • Conductor layer are interconnected by means of a connecting means.
  • the connecting means is in one embodiment, an electrically and / or thermally well conductive Material.
  • the connecting means may advantageously be a solder or an electrically conductive adhesive.
  • a chip mounting region is provided on a part of the second conductor layer.
  • the first conductor layer is arranged downstream of the second conductor layer on the side of the chip mounting region.
  • the chip mounting region is provided or formed in particular in a recess of the electrical connection conductor.
  • At least one inner wall whose main extension plane extends obliquely to a main extension plane of the electrical connection conductor and is tilted towards the chip mounting region compared to the main extension plane of the electrical connection conductor.
  • An inner wall formed in this way can serve as a reflector for an electromagnetic radiation emitted or to be received by a semiconductor chip in the case of an optoelectronic component.
  • a semiconductor component which has the electrical connection conductor in at least one of its embodiments or embodiments.
  • the electrical connection conductor is provided on a first side with a semiconductor chip and with a capsule mass, wherein the encapsulant surrounds the semiconductor chip and is integrally formed on the electrical connection conductor.
  • the capsule mass can be integrally formed and encapsulates the chip and in places the electrical connection conductor.
  • the semiconductor device according to one embodiment is an optoelectronic semiconductor device.
  • the semiconductor chip is in particular suitable for emitting and / or receiving electromagnetic radiation.
  • the electrical connection conductor is at least partially free of the encapsulation compound and any other insulating material on a second side opposite the first side in a region laterally overlapping the encapsulation compound. This means that the electrical connection conductor on the second side in such areas is at least partially free of the encapsulant in which encapsulant is present on the opposite first side.
  • the exposed part of the electrical connection conductor on its second side functions, in particular, as an external electrical connection of the semiconductor component.
  • connection conductor is completely enclosed by the latter in the region of the encapsulation compound and a further part of the connection conductor protrudes from the encapsulation compound and is bent onto a rear side of the encapsulation compound, do not fall under the previously described embodiment.
  • the semiconductor component can also have such features.
  • a region of the electrical connection conductor on the second side, which overlaps laterally with the semiconductor chip, is free of the encapsulation compound and also free of any other electrically insulating material.
  • the semiconductor chip is in particular a light-emitting diode chip, wherein the term "light-emitting diode chip” is not limited to chips which emit visible light but is generally used for all semiconductor chips which emit electromagnetic radiation.
  • the semiconductor chip has an epitaxial semiconductor layer sequence comprising an active layer in which the electromagnetic radiation is generated.
  • the capsule mass is formed according to a further embodiment to a large part or completely transparent to radiation.
  • the radiation-transmissive parts it has a transmittance of at least 50%, preferably of at least 70%, for electromagnetic radiation from the wavelength spectrum of the semiconductor chip.
  • the latter has a second electrical connecting conductor, which likewise has a first and a second conductor layer, which face one another
  • the second electrical connection conductor may be formed according to at least one of the described embodiments of the electrical connection conductor.
  • the electrical connection conductor overlaps completely or at least 80%, preferably at least 90% laterally, with the encapsulation compound. According to a further embodiment, this additionally or alternatively applies to the second electrical connection conductor.
  • a method for producing an electrical connection conductor for a semiconductor component is specified. The method provides a first conductor layer and a second conductor layer. The conductor layers each have major surfaces facing away from each other. The first and second conductor layers are connected to each other via two of their major surfaces such that these major surfaces face each other. The connecting of the first and the second conductor layer takes place, in particular, after the provision of the conductor layers. Furthermore, at least one thinned region is formed in the first conductor layer, the second conductor layer or both in the first and the second conductor layer, in which the layer thickness of the corresponding conductor layer is less than its maximum layer thickness.
  • the thinned region can be formed before or after the first or the second conductor layer is connected to one another.
  • the formation of the thinned region can in particular also take place during the provision of the corresponding conductor layer, for example during the production of the conductor layer.
  • the conductor layer can be formed from the outset with a thinned area.
  • the thinned area can also be formed in particular by material removal or by material deformation.
  • Figure 1 is a schematic sectional view of the first and the second conductor layer during a
  • Figure 2 is a schematic sectional view of the electrical connection conductor according to the first embodiment with the conductor layers shown in Figure 1;
  • Figure 3 is a schematic sectional view of
  • Figure 4 is a schematic sectional view of
  • Figure 5 is a schematic sectional view of
  • Figure 6 is a schematic sectional view of the semiconductor device according to a fourth
  • Figure 7 is a schematic sectional view of
  • Figure 8 is a schematic sectional view of
  • Figure 9 is a schematic sectional view of
  • FIG. 10 shows a first exemplary schematic plan view of that shown in FIG. 3, 5, 8 or 9
  • Figure 11 is a second exemplary schematic plan view of the semiconductor device shown in Figure 3, 5, 8 or 9;
  • FIG. 12 shows an exemplary detail of the component shown in FIG. 4 in a schematic sectional view.
  • FIG. 1 schematically shows a first conductor layer 11 and a second conductor layer 12. Both the first and the second conductor layer have a plurality of thinned areas, which will be explained below in connection with FIG.
  • the first conductor layer 11 also has several breakthroughs.
  • the breakthroughs may be formed, for example, as holes. However, they can also be recesses which are open on at least one side or which separate the various parts of the first conductor layer 11 visible in FIG. In other words, the first conductor layer 11 may also have a plurality of separate parts.
  • Both the first and the second electrical conductor layer comprises electrically conductive material.
  • the conductor layers may in particular also consist entirely of electrically conductive material. Alternatively, they may only partially consist of electrically conductive material. However, they preferably consist to a large extent of electrically conductive material, for example more than 50%, more than 75% or more than 80%.
  • the conductor layers 11, 12 comprise or consist of metallic material. Both conductor layers may for example consist to a large extent of copper.
  • the conductor layers may be e.g. be coated with at least one other metal, such as gold, silver or tin.
  • the maximum thickness of both conductor layers 11, 12 or one of the conductor layers is for example 0.1 mm, 0.15 mm or 0.2 mm.
  • conductor layers with different maximum thicknesses can also be used.
  • the first conductor layer 11 may have a maximum thickness 13 of about 0.15 mm and the second conductor layer 12 a maximum thickness 23 of 0.4 mm, or vice versa.
  • the connection material 3 is, for example, a solder or an electrically conductive adhesive. In principle, an electrically insulating connection material can also be used.
  • At least some of the thinned regions of the first conductor layer 11 as well as some of the openings 4 could in principle also be produced only after the first conductor layer 11 and the second conductor layer 12 have been connected to one another by means of the connection means 3.
  • the use of at least two conductor layers 11, 12 allows the electrical connection conductor 10 to be provided in a technically simple manner with a multiplicity of three-dimensional structures which would otherwise not be realizable or only with significantly higher outlay.
  • the first conductor layer 11 has a thinned region 111 on a first edge, which projects laterally beyond a thinned region 121 of the second conductor layer 12. Between the thinned portion 111 of the first conductor layer and the thinned portion 121 of the second conductor layer is a region which is free of material of the electrical connection layer. In the illustration in FIG. 2, the complete area between the thinned areas is at the edge
  • connection conductor 111, 121 free of material of the connection conductor.
  • part of this area could also be material of Connecting conductor, for example, connecting material 3 could protrude into the area.
  • Such a gap at an edge of the electrical connecting conductor can, in the case of a component to be produced, act like an anchoring element for a capsule mass, by means of which the risk of delamination of the encapsulation compound and the electrical connecting conductor can be significantly reduced.
  • the other structures of the electrical connection conductor shown in Figure 2 can act as an anchor element for a capsule mass when the respective gaps between parts of the first conductor layer 11 and the second conductor layer 12 are at least partially filled by a capsule mass.
  • the thinned regions 112, 113 of the first conductor layer 11 shown in FIG. 2 adjoin an opening 4.
  • the cross-sectional area of the recess increases, as viewed in a plan view, in the course from an outer side of the first conductor layer 11 to the second conductor layer 12.
  • Such depressions can be used for example as a pure anchor element of the electrical connection conductor 10.
  • the bottom of such a recess can also be used as a mounting surface for a semiconductor chip, which is arranged correspondingly in the recess.
  • a further recess is formed in the middle of the electrical connection conductor 10 according to Figure 2.
  • Thinned regions 114, 115 of the first conductor layer adjoin an opening 4 in this depression and project laterally beyond a thinned region 123 of the second conductor layer 12. Between the thinned regions 114, 115 of the first conductor layer 11 and the thinned region 123 of the second conductor layer 12 is a gap.
  • this depression has a different course of the size of the cross-sectional area. Starting from the outside of the first conductor layer 11, the cross-sectional area of the recess within the aperture initially decreases to become larger again in the region of the second conductor layer 12.
  • a further thinned region 116 of the first conductor layer 11 is present, which laterally projects beyond a part of the second conductor layer 12.
  • a thinned area 124 of the second conductor layer 12 only partially with the thinned Area 116 overlaps.
  • the thinned region 124 of the second conductor layer 12 overlaps also only partially laterally with another opening 4, to which the thinned area 116 adjoins.
  • Structural elements such as protruding parts or openings, are formed as in each case in one of the conductor layers 11, 12. If, for example, the thinned areas and the openings are made by etching in conductor layers made of metal, then there is a minimum size of a lateral extension of the thinned areas and the breakdown on the order of the maximum thickness of the unstructured conductor layer.
  • the first conductor layer 11 has an unthinned part 118 which laterally projects beyond a part 125 of the second conductor layer 12, wherein a gap exists between these parts 118, 125 of the conductor layers 11, 12. These can also serve as anchoring element for a capsule mass.
  • FIGS. 3 to 9 each illustrate an exemplary embodiment of a semiconductor component.
  • the semiconductor component is, for example, an optoelectronic component, for example a
  • the LEDs component has in each case a first electrical connection conductor 10 and a second electrical connection conductor 20.
  • the first electrical connection conductor 10 in each case has a chip mounting region 5, on which a semiconductor chip 50 is mounted mechanically and electrically conductive.
  • the semiconductor chip 50 is, for example, a light-emitting diode chip.
  • This has, for example, an epitaxial semiconductor layer sequence comprising active layer.
  • the active layer can in particular be composed of several partial layers, which in particular can also have different material compositions.
  • the semiconductor layer sequence has, for example, III / V compound semiconductor materials.
  • a III / V compound semiconductor material comprises at least one element of the third main group such as B, Al, Ga, In, and a fifth main group element such as N, P, As.
  • the term "III / V compound semiconductor material” includes the group of binary, ternary or quaternary compounds containing at least one element from the third main group and at least one element from the fifth main group, for example nitride and phosphide compound semiconductors.
  • Such a binary, ternary or quaternary compound may also have, for example, one or more dopants and additional constituents.
  • the active layer 11 preferably comprises a pn junction, a double heterostructure, a single quantum well (SQW) or, more preferably, one
  • Quantum well structure for generating radiation.
  • the term quantum well structure unfolds no significance with regard to the dimensionality of the quantization. It thus includes u.a. Quantum wells, quantum wires and quantum dots and each
  • the chip mounting region 5 is formed in each case on an outer surface of the second conductor layer 12 of the first electrical connection conductor 10.
  • the first conductor layer 11 follows the second conductor layer 12 on the side of the chip mounting region 5.
  • the semiconductor chip 50 is at least partially laterally surrounded by material of the first electrical connection layer 10. In other words, it is arranged in a depression of the first electrical connection layer 10.
  • the first electrical connection conductor 10 and the semiconductor chip 50 are provided with a capsule mass 9 of the semiconductor component.
  • the capsule mass 9 encapsulates the semiconductor chip 50 and is molded onto the electrical connection conductor 10.
  • the latter is free of the encapsulation compound and of other electrically insulating material.
  • This region of the outer surface of the first electrical connection conductor 10 serves, for example, as an external electrical contact surface 81 of the semiconductor component.
  • the chip mounting portion 5 is formed on an outer surface of a thinned portion 122 of the second conductor layer 12.
  • the distance between the Chip mounting area 5 and the external electrical connection surface 81 with advantage particularly small.
  • a particularly low thermal resistance between the semiconductor chip 50 and the electrical connection surface 81 can be achieved, which can have a positive effect on the operation, the performance and the resistance of the semiconductor component.
  • the thickness of the conductor layer for thermal resistance plays only a minor role.
  • the chip mounting portion 5 is formed on an outer surface of the first conductor layer (i.e., the "upper" conductor layer downstream of the second conductor layer), heat accumulation may occur between the second and first layers depending on the configuration. This could have a negative effect on the thermal resistance. Nevertheless, it is basically also possible to form the chip mounting region 5 on an outer surface of the second conductor layer, see FIGS. 6 and 7.
  • the chip mounting portion 5 is formed on an outer surface of a part of the second conductor layer 12 whose thickness a maximum thickness 23 of the second conductor layer corresponds.
  • the second conductor layer 12 has thinned regions 121, 122 at the edges.
  • the semiconductor component according to FIG. 9, for example, has a second conductor layer 12 of the first electrical connection conductor 10, which has no thinned areas.
  • the second conductor layer 12 may be formed of, for example, a metal plate having a substantially constant thickness.
  • the depression in which the semiconductor chip 50 is arranged is designed as an anchoring element, in which gaps are present between parts of the first conductor layer 11 and of these laterally projected parts of the second conductor layer 12, which are filled by the encapsulation compound 9.
  • the exemplary semiconductor device illustrated in FIG. 4 has a depression with edges that can act as reflectors.
  • the chip mounting portion 5 is surrounded by at least two inner walls of the recess whose main extension plane 51 extends obliquely to a main extension plane of the electrical connection conductor 10 and compared to the main extension plane of the electrical connection conductor 10 is tilted to the chip mounting region 5 out.
  • the inner walls are shown as being formed of a plurality of rectangular steps. In reality, however, these are generally not rectangular steps, but rather partially curved and rounded surfaces.
  • concave bulges are formed by etching the apertures 4, the thinned portions 112, 113 of the first conductor layer, and the thinned portion 122 of the second conductor layer 121 in a substantially constant thickness metal plate.
  • a schematic exemplary representation of such concave curvatures of the steps of an inner wall is given in the detail shown in FIG.
  • the inner walls can also be formed in other ways.
  • additional measures can be taken to smooth the inner walls.
  • dashed lines exemplify what the shape or shape of a smoothed inner wall might look like. Smoothing or removal of the edges may e.g. be done by electropolishing or similar methods.
  • the inner walls are largely shaped so that electromagnetic radiation of the semiconductor chip 50 can be deflected in an emission direction of the semiconductor component.
  • the connecting conductor 10 is formed as a reflector, as exemplified in Figures 4 and 12, then it is advantageous if "the bottom of the recess on which the chip mounting portion 50 is formed, is as deep as possible, so that the 'reflectors' possible high over the chip 5.
  • the thinned region 122 of the second conductor layer 12 is at least 60%, at least 70%, or at least 80%. thinner than the maximum thickness of the second conductor layer.
  • the entire connecting conductor 10 for example, a total thickness of at least 4 mm, at least 5 mm or at least 6 mm.
  • the chip mounting region 5 is formed on an outer surface of the first conductor layer 11, respectively.
  • the second conductor layer 12 is arranged on a side of the first conductor layer 11 facing away from the chip mounting region 5.
  • the first conductor layer 11 has, for example, no breakdown.
  • the first conductor layer 11 of the first electrical connection conductor 10 has an opening 4, against which the thinned areas 112, 113 adjoin, so that an anchoring element is formed.
  • the recess of this anchoring element is free of a semiconductor chip 50, for example.
  • the capsule mass 9 has, for example, silicone or consists at least to a large extent of this.
  • a part of the capsule mass 9 is formed into a lens 91.
  • the capsule mass 9 can, for example, a side remote from the semiconductor chip 50 side of the electrical connection conductor, contrary to the illustrations in the figures, to a Cover part as well. However, a further part of the electrical connection conductors 10, 20 remains free in this case of the capsule mass 9 and of other electrically insulating material and forms an electrical connection surface 81 in the case of the first connection conductor 10 and an electrical connection surface 82 in the case of the second electrical connection conductor 20 ,
  • the second electrical connection conductor 20 likewise has, for example, at least one first conductor layer 21 and a second conductor layer 22 analogous to the first electrical connection conductor.
  • the first electrical connection conductor 10 and / or the second electrical connection conductor 20 may in principle also have further electrical conductor layers, which are not shown in the exemplary embodiments.
  • the semiconductor chip 50 is electrically conductively connected, for example by means of a bonding wire 6, to an internal electrical connection surface 7 of the second electrical connection conductor 20.
  • the second electrical connection conductor On a side opposite the internal electrical connection surface 7, the second electrical connection conductor has an external electrical connection surface 82, which is free of insulating material.
  • a bonding wire 6 other electrical connection means for the electrically conductive connection of the semiconductor chip 50 to the second electrical connection conductor 20 can in principle also be used.
  • At least one of the electrical connecting conductors 10, 20 may in principle also be formed in one piece or in one piece.
  • the second electrical connection conductors are formed in the embodiments according to Figures 3, 4, 5, 7, 8 and 9, for example, the same in each case. They each have a first thinned region 211 in the first conductor layer 21, which projects laterally beyond a first thinned region 221 of the second conductor layer 22. There is a gap between the first thinned areas 211, 221.
  • the first conductor layer 21 has a second thinned region 212 which projects laterally beyond a second thinned region 222 of the second conductor layer 22. There is also a gap between these thinned areas 212, 222.
  • the first conductor layer of the second electrical connection conductor 20 has thinned regions 211, 212 which adjoin an opening 4 of the first conductor layer 21.
  • the second conductor layer 22 of the second electrical connection layer 20 has, for example, no thinned areas.
  • the internal contact surface 7 is formed by an outer surface of the second conductor layer 22.
  • FIG. 10 shows a first exemplary embodiment of a plan view of the semiconductor component shown in FIG. 3, 4, 5, 8 or 9.
  • the semiconductor chip 50 is laterally completely off the first one
  • Terminal layer 11 and optionally surrounded by parts of the second connection layer 12.
  • the depression in which the semiconductor chip 50 is formed is arranged, an open on two opposite sides trench.
  • the cross-sectional views may alternatively be 'lateral plan views of the semiconductor device according to Figure 3, 4, 5, 8 and 9, since the recess on two sides is open laterally.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un conducteur de raccordement électrique pour un élément semi-conducteur, en particulier un élément semi-conducteur optoélectronique. Ce conducteur comprend une première couche conductrice et une deuxième couche conductrice qui sont reliées ensemble par l'intermédiaire de surfaces principales orientées l'une vers l'autre. La première couche conductrice, la deuxième couche conductrice ou tant la première que la deuxième couche conductrice comprennent au moins une zone amincie dans laquelle leur épaisseur de couche est moindre que leur épaisseur de couche maximale. L'invention concerne également un élément semi-conducteur muni du conducteur de raccordement électrique ainsi qu'un procédé de fabrication du conducteur de raccordement électrique.
PCT/DE2009/001414 2008-10-16 2009-10-12 Conducteur de raccordement électrique pour un élément semi-conducteur, élément semi-conducteur et procédé de fabrication d'un conducteur de raccordement électrique WO2010043205A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008051928A DE102008051928A1 (de) 2008-10-16 2008-10-16 Elektrischer Anschlussleiter für ein Halbleiterbauelement, Halbleiterbauelement und Verfahren zur Herstellung eines elektrischen Anschlussleiters
DE102008051928.6 2008-10-16

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WO2010043205A1 true WO2010043205A1 (fr) 2010-04-22

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Publication number Priority date Publication date Assignee Title
DE102010023815A1 (de) 2010-06-15 2011-12-15 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Bauelement und Verfahren zur Herstellung eines oberflächenmontierbaren optoelektronischen Bauelements

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US7071545B1 (en) * 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
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TW201025537A (en) 2010-07-01
DE102008051928A1 (de) 2010-04-22

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