TW201025537A - Electric connection conductor for a semiconductor component, semiconductor component and method for the production of an electric connection conductor - Google Patents

Electric connection conductor for a semiconductor component, semiconductor component and method for the production of an electric connection conductor Download PDF

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Publication number
TW201025537A
TW201025537A TW098134743A TW98134743A TW201025537A TW 201025537 A TW201025537 A TW 201025537A TW 098134743 A TW098134743 A TW 098134743A TW 98134743 A TW98134743 A TW 98134743A TW 201025537 A TW201025537 A TW 201025537A
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TW
Taiwan
Prior art keywords
conductor
electrical connection
conductor layer
layer
connection conductor
Prior art date
Application number
TW098134743A
Other languages
Chinese (zh)
Other versions
TWI404186B (en
Inventor
Michael Zitzlsperger
Original Assignee
Osram Opto Semiconductors Gmbh
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Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of TW201025537A publication Critical patent/TW201025537A/en
Application granted granted Critical
Publication of TWI404186B publication Critical patent/TWI404186B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

An electric connection conductor for a semiconductor component, especially for an optoelectronic semiconductor component, is provided. The conductor has a first conductor layer and a second conductor layer, which are connected through mutually oriented main surface. The first conductor layer, the second conductor layer or both the first and the second conductor layer has at least one thin area, in which its layer thickness is smaller than its maximal layer thickness. In addition, a semiconductor component with the electric connection conductor as well as a method for the production of the electric connection conductor is given.

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201025537 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種半導體組件用之電連接導體、以及電連 接導體之製造方法。此外，本發明提供一種具有電連接導 體之半導體組件。 本專利申請案主張德國專利申請案10 2008 05 1 928.6之 優先權，其已揭示的整個內容在此一倂作爲參考。 I 【先前技術】 〇 製造半導體組件時，通常使用所謂導線架。導線架具有 用於電子組件（例如，半導體組件）之電連接導體。電連接 導體例如藉由導線架之框而連接且固定在該框中。導線架 通常至少由沖製之銅片所構成。吾人通常將導線架稱爲金 屬板，其中藉由空白區而形成電連接導體。 在製造習知的半導體組件時，通常使至少一個半導體晶 片在機械上與電性上與預設之電連接導體相連接》然後， Φ 使晶片和每一電連接導體之一部份都以一種包封物質來包 封。電連接導體例如在互相面對的側面上由該包封物質突 出來。 【發明內容】 本發明的目的是提供一種半導體組件用之電連接導體， 其可較傳統的電連接導體有更多個方面的應用。此外，本 發明提供一特別有利的具有電連接導體之半導體組件以及 電連接導體之製造方法。 201025537 本發明提供一種半導體組件（特別是光電半導體組件）用 之電連接導體’具有第一導體層和第二導體層，其經由互 相面對的主面而互相連接。第一導體層、第二導體層或此 二者具有至少一薄化的區域，其中此區域的層厚度小於該 二個導體層的最大層厚度。 電連接導體及其每一導體層是特殊的自我承載元件或無 承載性的元件，即’其特別是處於一種狀態中，此狀態中 該電連接導體未具備其它材料、外形穩定且可在保持其外 Ο 形的情況下移動及輸送。可導電的塗層例如薄的金屬塗層 或透明的導電氧化物之薄層施加在材料面上，這些塗層不 屬於”第一導體層”或”第二導體層”。這在一種處於” 不是施加在另一材料上而是未具有其它材料”的形式中的 塗層由於缺乏外形穩定性而不適於一般的處理時特別適 當。 依據一適當的實施形式，第一導體層和第二導體層所具 〇 有的最大厚度至少是50微米，較佳是至少80微米或至少 90微米。即，導體層在至少一位置處必須具有一至少與上 述厚度之一種一樣大的厚度，其中此厚度是指垂直於導體 層之主延伸面之厚度。 依據至少一實施形式’第一導體層、第二導體層以及此 二者是一種金屬板或具有一個金屬板。 該些導體層分別具有一種面形式，其具有互相面對的主 面’各主面經由側面而互相連接，各側面分別都小於主面。 201025537 第一導體層 至少一導體 有多個其它 ，例如包括 〇 域之特定的 始，薄化的 然而，這不 的區域來形 體層的層厚 化的區域” 厚度至少小 有的厚度可 接導體之第 ，該包封物 射時，老化 此外，砂樹 環氧化物典 脂可加熱至 在一種措施中形成電連接導體，其至少具有 和第二導體層形式之二個部份，且此措施中使 層設有一薄化的區域，則藉此措施可形成一具 特性的電連接導體，這些特性超過傳統的特性 導電性以及可作爲半導體晶片用之載體之特性 術語”薄化的區域”未指出用來形成此種區 製造方法。明確而言，由固定厚度之導體層開 I 區域例如藉由鈾刻或模壓使材料剝除而形成。 〇 是必要的。例如，導體層主要是以較薄或較厚 成。”薄化的區域”通常定義成：該區域中導 度小於最大的層厚度，這與製造方法無關。”薄 可適當的具有一種厚度，其較該導體層之最大 1 0 %、2 5 %或3 5 %。例如，”薄化的區域”所具 較該導體層之最大厚度小40%或5 0%。 依據電連接導體之至少一實施形式，在電連 φ —側上形成一具有矽樹脂之包封物質。換言之 質形成二個導體層用之外殻物質。 矽樹脂之優點在於：在短波長之電磁輻射人 速率較其它包封物質（例如，光樹脂）小很多。 脂所具有的耐溫性例如較環氧化物者高很多。 型上可加熱至最多大約150 °C而未受損，但矽樹 200〇C 。 該包封物質較佳是使用矽樹脂，其硬度在折射率1.41至 201025537 1.57時是在ShoreA = 20至D = 90之範圍中。 因此’該包封物質可由此處所述之一種或多種矽樹脂所 構成，其中另外可在砂樹脂中施加對輻射具有反射性或吸 收性的塡料，例如，Ti〇2或炭黑。 又’該包封物質亦可使用混合材料，例如，矽樹脂和環 氧化物之混合物或矽樹脂與其它有機材料（例如，含有乙烯 基或丙烯基之材料）之混合物。 上述形式之混合材料之輻射穩定性和熱穩定性較純環氧 〇 化物還佳且另外具有良好的機械特性（例如，堅韌性）。 依據電連接導體之至少一實施形式，電連接導體在一橫 向中與該包封物質重疊之區域中的與第一側相面對的第二 側上至少一部份未具有該包封物質及電性絕緣材料。該電 連接導體較佳是可表面安裝者。有利的是可在該電連接導 體之裸露的部份（即，第二側）上達成一種外部電性接觸。 依據電連接導體之至少一實施形式，第一導體層是第一 Φ 導線架之一部份且第二導體層是第二導線架之一部份。第 二導線架在一唯一之組合式導線架中互相連接。如本文開 頭所述，導線架是一種金屬板，其中半導體組件用的多個 電連接導體互相連接，各電連接導體在金屬板中藉由板中 對應的空白區而形成。術語”導線架”已爲人所知，特別 是已爲光電領域的專家所知悉。 術語”導體層”未必隱含單件式的層。反之，導體層亦 可具有多個互相隔開且相鄰配置之多個部份層。 201025537 依據電連接導體之至少一實施形式，第一和第二導體層 分別具有至少一薄化的區域，其中該層之厚度小於最大的 層厚度。因此，該電連接導體中就形成其它的功能或特殊 形式和結構而言仍有更大的可變化性。 在此種形式的佈置中，第一導體層之薄化的區域在橫向 中是與第二導體層之薄化的區域相重疊。本申請案中所謂 橫向是指一種與對應的導體層或電連接導體之主延伸面平 ^ 行而延伸的方向。 ❹ 依據至少另一實施形式，第一導體層具有至少一缺口。 此缺口例如可以是導體層中之洞或空白區，其經由該導體 層之整個厚度而延伸。該空白區可在至少一側上敞開，即， 該空白區未必在全部的側面上橫向地由導體層之材料所包 圍。在第一導體層具有多個互相隔開之部份層時，空白區 是一種介於多個部份層之間的間隙。 依據該實施形式之至少一佈置方式，第一導體層具有一 〇 與該缺口相鄰的薄化的區域。 依據該實施形式之至少一佈置方式，第二導體層具有一 薄化的區域，其在橫向中是與第一導體層之缺口相重疊。 此缺口和該薄化的區域可完全重疊。然而，其亦可只一部 份互相重疊，即，該缺口可一部份在橫向中對該薄化的區 域形成偏移。 依據另一佈置方式，該缺口在第一導體層之俯視圖中的 開口面積小於第二導體層之與該缺口重疊之薄化的區域在 -7- 201025537 該俯視圖中的面積。俯視圖是指在與導體層或電連接導體 之一之主延伸面相垂直之觀看角度下所看到的圖式。或 是，該缺口之開口面積在俯視圖中大於第二導體層之與該 缺口相重疊的區域在該俯視圖中觀看時的面積。 依據至少一實施形式，第一導體層具有一個部份，該部 份在橫向中與第二導體層之一部份重疊，其中該第一導體 層之該部份與該第二導體層之橫向中重疊之該一部份都不 ©具有該電連接導體之材料。在上述二個部份之間特別是存 在一間隙。 在一佈置中，第一導體層之一部份與該缺口相鄰接。 依據該電連接導體之至少另一佈置方式，在一邊緣上存 在第一導體層的一部份，其與第二導體層之一部份重疊， 其中在第一導體層之該部份和第二導體層之該部份之間是 一種區域，其未具有該電連接導體之材料。在上述二個部 份之間特別是存在一間隙。 ® 電連接導體之至少另一實施形式之設計方式是，第一和 第二導體層藉由一連接媒體而互相連接。此連接媒體在一 佈置中是良好的導電材料及/或導熱材料。該連接媒體可以 是一種焊劑或可導電之黏合物。 依據電連接導體之至少另一實施形式，在第二導體層之 一部份上設有晶片安裝區。第一導體層在晶片安裝區之此 側上配置在第二導體層之後。該晶片安裝區特別是設置在 該電連接導體之凹口中。 201025537 在電連接導體之至少另一實施形式中，存在至少一內 壁，其主延伸面傾斜於該電連接導體之主延伸面而延伸且 在與該電連接導體之主延伸面比較下朝向該晶片安裝區而 傾斜。這樣所形成的內壁在光電組件中作爲半導體晶片所 發出或所接收之電磁輻射用的反射器。 提供一種半導體組件，其在至少一實施形式中具有電連 接導體。此電連接導體在第一側上設有半導體晶片和包封 A 物質，其中該包封物質圍繞該半導體晶片且形成在該電連 接導體上。換言之，該包封物質以單件方式而形成且包封 著該晶片以及依位置而包封著該電連接導體。 依據一實施形式，該半導體組件是光電半導體組件。半 導體晶片特別適合用來發出及/或接收電磁輻射。 依據半導體組件之至少另一實施形式，電連接導體在一 與第一側相面對的第二側上在橫向中與該包封物質重疊之 區域中至少一部份未具有該包封物質和其它的絕緣材料。 〇 即，電連接導體在該區域中之第二側上至少一部份未具有 該包封物質，該區域中在相面對的第一側上存在該包封物 質。第二側上該電連接導體之裸露之部份特別是作爲該半 導體組件之外部電性連接處。 一些不屬上述的實施形式中，該電連接導體在該包封物 質中完全由該包封物質所圍繞且該電連接導體之另一部份 由該包封物質中突出而在該包封物質的背面上成弧形。 依據半導體組件之另一佈置方式，該電連接導體在第二 201025537 側上之一在橫向中與半導體晶片重疊之區域未具有該包封 物質且亦未具有其它的電性絕緣材料。 半導體晶片特別是一種發光二極體晶片，其中此發光二 極體晶片不限於發出可見光的晶片而是指一般之可發出電 磁輻射之所有半導體晶片。此半導體晶片特別是具有一種 磊晶半導體層序列，其包括活性層，此活性層中產生電磁 輻射。 I 依據另一實施形式，該包封物質的大部份或全部都可使 Ο 輻射透過，其可透過輻射的部份對該半導體晶片所發出之 光譜中的電磁輻射所具有的透射率至少是50%，較佳是 7 0%。 依據該半導體組件之另一實施形式，其所具有的第二電 連接導體同樣具有第一和第二導體層，此二個導體層經由 相面對的主面而互相連接。該第二電連接導體是依據上述 至少一實施形式而形成。 Q 依據該半導體組件之另一實施形式，該電連接導體完全 地或至少80% (較佳是90%)在橫向中與該包封物質重疊。依 據另一實施形式，該包封物質亦可用於該第二電連接導體。 本發明亦提供一種半導體組件用之電連接導體之製造方 法。此方法中製備一第一導體層和一第二導體層。各導體 層分別具有互相遠離之主面。第一和第二導體層經由其主 面而互相連接，使各主面互相面對。第一和第二導體層之 連接特別是在各導體層已製備之後才進行。此外，第一導 -10- 201025537 體層中、第二導體層中或第一和第二導體層中形成至少一 薄化的區域，其中各導體層的層厚度小於其本身最大的層 厚度。 薄化的區域之形成可在第一和第二導體層相連接之後才 進行。薄化的區域的形成特別是亦可在相對應的導體層之 製備期間才進行。該導體層立即以一薄化的區域來形成。 然而，該薄化的區域特別是亦可藉由材料剝蝕或材料變形 來形成。 Ο 本發明之電連接導體、半導體組件及其製造方法之其它 優點、較佳的實施形式以下將參照圖式中的實施例來說明。 【實施方式】 各圖式和實施例中相同或作用相同的各組件分別設有相 同的參考符號。所示的各元件和各元件之間的比例未必依 比例繪出。反之，爲了清楚之故各圖式的一些細節已予放 大地顯示出。 Q 第1圖顯示第一導體層11和第二導體層12。第一和第二 導體層具有多個薄化的區域，其將在第2圖中詳述。第一 導體層11另外具有多個缺口。該些缺口例如能以孔洞來形 成。然而，該些缺口亦可以是空白區’其在至少一側上敞 開或將該第一導體層Π之在第1圖中不同的可見部份互相 隔開。換言之，第一導體層11亦具有多個互相分開的部份。 第一和第二導體層都具有導電材料。各導體層特別是亦 可完全由導電材料所構成。或是’各導體層只有一部份由 -11 - 201025537 導電材料所構成。然而，各導體層的大部份（例如，大於 50%，大於75%或大於80%)較佳是由導電材料所構成。 導體層11、12具有金屬材料或由其所構成。該二個導體 層例如大部份可由銅構成。或是，各導體層例如可以至少 另一金屬（例如，金、銀或錫）來塗佈。 該二個導體層11、12或其中一導體層之最大厚度13例 如是0.1 mm、0.15 mm或0.2 mm。特別是亦可使用具有不 ^ 同的最大厚度23之導體層。例如，第一導體層11具有0.15 mm丨之最大厚度，第二導體層12具有0.4 mm之最大厚度， 或反之亦可。 爲了製成該電連接導體10，則第一和第二導體層11、12 須藉由一連接材料3而互相連接，請參閱第2圖。該連接材 料3例如是焊錫或可導電之黏合物。基本上亦可使用電性 絕緣之連接材料。 在第一導體層11和第二導體層12藉由該連接材料3而 ® 互相連接之後，亦可首先產生第一導體層11之至少一些薄 化的區域和一些缺口 4。 如第2圖所示，電連接導體1〇可藉由使用至少二個導體 層11、12而以技術上簡單的方式設有多個三維之結構，其 能以不同的方式而耗費不高或耗費不是很高地來製成。 第2圖所示之電連接導體1〇中，第一導體層π在第一 邊緣上具有一薄化的區域111，其在橫向中是與第二導體層 12之薄化的區域121相重疊。在第一導體層之薄化的區域 -12- 201025537 111和第二導體層之薄化的區域121之間是一種未具 接導體之材料之區域。第2圖中，多個薄化的區域 整個區域在邊緣111、121上未具有該電連接導體之 然而，該區域之一部份亦可具有該電連接導體之材 連接材料3例如可伸入至該區域中。 電連接導體之一邊緣上之間隙在待製成的組件中 作爲包封物質用之固定元件，使該包封物質和電連 ^ 之去積層（delamination)之危險性大大地下降。當第 〇 層1 1和第二導體層12之各部份之間的各間隙之至少 是以包封物質來塡入時，則第2圖所示之電連接導 它結構亦可作爲包封物質用之固定元件。 第一導體層11之第2圖所示之薄化的區域112、 與缺口 4相鄰接。此外，各區域112、113分別在橫 第二導體層12之薄化的區域122之一部份突出，其 形成間隙。又，在電連接導體1 0中亦形成一凹口。 〇 之橫切面在俯視圖中已放大，其是由第一導體層11 延伸至第二導體層12。 此種凹口例如可用作該電連接導體10之純固定 又，此種凹口之底部亦可用作半導體晶片之安裝面 導體晶片配置在該凹口中。 第2圖中該電連接導體1〇之中央形成另一凹口。 體層之薄化的區域114、115在此凹口中鄰接於一缺 在橫向中突出於第二導體層12之薄化的區域123。 有電連 之間之 材料。 料，該 例如可 接導體 一導體 一部份 體之其 1 1 3是 向中由 間分別 此凹口 之外側 元件。 ，該半 一導 口 4且 第一導 -13- 201025537 體層11之薄化的區域114、115和第二導體層12之薄化的 區域123之間是一種間隙。與先前之凹口不同之處在於， 此凹口具有另一種形式的橫切面。由第一導體層11之外側 開始，該凹口之橫切面在該缺口內部中首先變小，以便在 第二導體層12之區域中又變大。 第一導體層之鄰接於該缺口 4之薄化的區域114、115是 與薄化的區域112、113不同而形成在導體層11之一部份 赢 中，該一部份是面向第二導體層12且形成第一導體層11 © 之主面，藉此使第一導體層11與第二導體層12相連接。 第2圖所示之電連接導體之實施例中，第一導體層11 存在另一薄化的區域116，其在橫向中與第二導體層12之 —部份重疊。於此，薄化的區域116和第二導體層12之被 該區域116所突出之部份之間的區域中只有一部份未具有 電連接導體10之材料。這是藉由”第二導體層12之薄化 的區域124只有一部份是與薄化的區域116相重疊”來達 〇 成。第二導體層12之薄化的區域124在橫向中亦只有一部 份與另一缺口 4相重叠，薄化的區域116鄰接於該缺口 4。 藉由上述在橫向中一部份相重疊，則可在電連接導體10 中有效地形成較各導體層1 1、1 2中還小的結構元件，例如， 突出部份或開口。當薄化的區域和缺口藉由蝕刻而形成在 由金屬構成的導體層中時，則薄化的區域和缺口之橫向範 圍之最小大小是位於未結構化之導體層之最大厚度之數量 級（order)中。 -14- 201025537 在電連接導體10之第二邊緣上，該第一導體層11具有 一未薄化之部份118，其在橫向中是由第二導體層12之~ 部份125突出’其中在導體層π、12之部份118、125之 間形成一間隙。該間隙亦可作爲該包封物質用之固定元件。 第3圖至第9圖分別顯示一種半導體組件之實施例。此 半導體組件例如是光電組件，例如，發光二極體組件，其 具有第一電連接導體10和第二電連接導體20。第一電連接 I 導體1〇具有晶片安裝區5，其上以機械式及可導電方式安 ❹ 裝一個半導體晶片50。 半導體晶片50例如是發光二極體晶片，其具有一圍繞活 性層之磊晶半導體層序列。此活性層特別是可由多個部份 層所組成，各個部份層特別是亦可具有不同之材料成份》 半導體層序列例如具有III-V-化合物-半導體材料。III-V-化合物半導體材料具有至少一種來自第三族的元素（例如， 硼、鋁、鎵、銦）以及一種來自第五族的元素（例如，氮、磷、 〇 砷）。此槪念“ III-V-化合物半導體材料”特別是包括二元、 三元或四元化合物之基團（group)，其含有來自第三族之至 少一元素和來自第五族之至少一元素，例如，氮化物和磷 化物化合物半導體。此種二元、三元或四元化合物可另外 具有一種或多種摻雜物質以及其它成份。 活性層11較佳是包括一 pn-接面、一雙異質結構、一單 —量子井（SQW, single quantum well)或特別是一多量子井結 構（MQW, multi quantum well)以產生輻射。此名稱量子井結 -15- 201025537 構此處未指出量子化的維度。因此，量子井結構可另外包 含量子槽、量子線和量子點以及這些結構的每一種組合。 例如，MQW-結構已爲此行的專家所知悉 在第3圖、第4圖、第5圖、第8圖和第9圖所示的實 施例中，晶片安裝區5分別形成在第一電連接導體10之第 二導體層12之一外表面上。第一導體層11在該晶片安裝 區5之此側上位於第二導體層12之後。因此，半導體晶片 50至少一部份在橫向中由第一電連接導體1〇之材料所圍 繞著。換言之，半導體晶片50配置在第一電連接導體10 之一凹口中。 在晶片安裝區5和半導體晶片50之此側上，第一電連接 導體10和半導體晶片50設有該半導體組件之包封物質9。 此包封物質9包封著該半導體晶片50且形成在電連接導體 10上。在電連接導體10之與晶片安裝區5相面對的此側 上，該電連接導體10未具有該包封物質和其它電性絕緣材 〇 料。第一電連接導體ίο之外表面之區域例如用作該半導體 組件之外部電性接觸面8 1。 在第3圖、第4圖、和第8圖所示之實施例中，晶片安 裝區5形成在第二導體層12之薄化的區域122之一外表面 上。 當晶片安裝區5形成在第二導體層12之薄化的區域122 之外表面上時，可使晶片安裝區5和外部之電性接觸面81 之間的間距特別小。於是’可使半導體晶片50和電性接觸 16 - 201025537 面8 1之間的熱阻特別小，這對於該半導體組件之操作、功 率和持久性有良好的作用。 然而，特別小的熱阻通常總是在該晶片安裝區5形成在 第二導體層之一外表面（即，“下方之”遠離主輻射方向之 導體層）上時才可達成，這與該晶片安裝區是否形成在未薄 化或薄化的區域無關。例如，當第一導體層是由銅構成時， 該導體層的厚度只對該熱阻造成小的影響。反之，當該晶 _ 片安裝區5形成在第一導體層之一外表面（即，“上方之”201025537 SUMMARY OF THE INVENTION [Technical Field] The present invention relates to an electrical connection conductor for a semiconductor component and a method of manufacturing the electrical connection conductor. Moreover, the present invention provides a semiconductor component having an electrical connection conductor. The present patent application claims the priority of the German Patent Application No. 10 2008 05 1 928.6, the entire disclosure of which is hereby incorporated by reference. I [Prior Art] 所谓 When manufacturing semiconductor components, so-called lead frames are usually used. The leadframe has electrical connection conductors for electronic components (e.g., semiconductor components). The electrical connection conductors are connected, for example, by a frame of the lead frame and are fixed in the frame. The lead frame is usually constructed of at least a stamped copper sheet. The lead frame is generally referred to as a metal plate in which an electrical connection conductor is formed by a blank area. In the fabrication of conventional semiconductor components, at least one semiconductor wafer is typically mechanically and electrically connected to a predetermined electrical connection conductor. Then, Φ causes one of the wafer and each of the electrical connection conductors to be Encapsulate the substance to encapsulate. The electrical connection conductors are e.g. protruded from the encapsulating material on mutually facing sides. SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrical connection conductor for a semiconductor component that can be used in more aspects than conventional electrical connection conductors. Furthermore, the present invention provides a particularly advantageous method of fabricating a semiconductor component having an electrical connection conductor and an electrical connection conductor. 201025537 The present invention provides an electrical connection conductor ' for a semiconductor component (particularly an optoelectronic semiconductor component) having a first conductor layer and a second conductor layer which are interconnected via mutually facing main faces. The first conductor layer, the second conductor layer or both have at least one thinned region wherein the layer thickness of the region is less than the maximum layer thickness of the two conductor layers. The electrical connection conductor and each of its conductor layers are special self-loading elements or non-load bearing elements, ie, which are in particular in a state in which the electrical connection conductors are not provided with other materials, are dimensionally stable and can be maintained It moves and transports in the case of a squat. A thin layer of an electrically conductive coating such as a thin metal coating or a transparent conductive oxide is applied to the surface of the material which does not belong to the "first conductor layer" or "second conductor layer". This is particularly suitable when a coating in a form that is "not applied to another material but has no other material" is not suitable for general handling due to lack of dimensional stability. According to a suitable embodiment, the first conductor layer and the second conductor layer have a maximum thickness of at least 50 microns, preferably at least 80 microns or at least 90 microns. That is, the conductor layer must have a thickness at least at one location that is at least as large as one of the above thicknesses, wherein the thickness is the thickness perpendicular to the major extension surface of the conductor layer. According to at least one embodiment, the first conductor layer, the second conductor layer and both are a metal plate or have a metal plate. The conductor layers each have a planar form having major faces facing each other. The major faces are interconnected via sides, each side being smaller than the major faces. 201025537 The first conductor layer has at least one conductor having a plurality of other, for example, including a specific beginning of the crucible region, and thinning, however, the region where the layer is thickened by the thickness of the layer is at least a small thickness of the conductor. First, when the encapsulant is shot, aging, in addition, the sand tree epoxide can be heated to form an electrical connection conductor in at least one of the two portions in the form of a second conductor layer, and this measure The middle layer is provided with a thinned region, and by this measure, a characteristic electrical connection conductor can be formed, which exceeds the conventional characteristic conductivity and the characteristic term "thinned region" which can be used as a carrier for a semiconductor wafer. It is pointed out that the method for forming such a region is formed. Specifically, it is formed by stripping a region of a conductor layer of a fixed thickness, for example, by uranium engraving or molding. 〇 is necessary. For example, the conductor layer is mainly Thin or thicker. "Thined area" is generally defined as: the conductivity in this area is less than the maximum layer thickness, which is independent of the manufacturing method." Thin may have a suitable The thickness is greater than 10%, 25% or 35% of the conductor layer. For example, the "thinned area" is 40% or 50% smaller than the maximum thickness of the conductor layer. According to at least one embodiment of the electrical connecting conductor, an encapsulating material having a resin is formed on the side of the electrical connection φ. In other words, the outer shell material for the two conductor layers is formed. The advantage of enamel resin is that the electromagnetic radiation rate at short wavelengths is much smaller than other encapsulating materials (e.g., photo-resin). The temperature resistance of the fat is much higher, for example, than those of the epoxide. The model can be heated up to approximately 150 °C without damage, but eucalyptus 200 〇C. The encapsulating material is preferably a ruthenium resin having a hardness in the range of Shore A = 20 to D = 90 at a refractive index of 1.41 to 201025537 1.57. Thus, the encapsulating material may be composed of one or more of the enamel resins described herein, wherein a smear which is reflective or absorbing to radiation, such as Ti 〇 2 or carbon black, may additionally be applied to the sand resin. Further, the encapsulating material may be a mixed material such as a mixture of an anthracene resin and an epoxide or a mixture of a fluorene resin and other organic materials (e.g., a material containing a vinyl group or a propylene group). The mixed materials of the above forms have better radiation stability and thermal stability than pure epoxy bismuth compounds and additionally have good mechanical properties (e.g., toughness). According to at least one embodiment of the electrical connecting conductor, the electrical connecting conductor has at least a portion of the second side facing the first side in a region overlapping the encapsulating material in a lateral direction without the encapsulating substance and Electrical insulation material. The electrical connection conductor is preferably a surface mountable person. Advantageously, an external electrical contact can be achieved on the exposed portion (i.e., the second side) of the electrical connection conductor. According to at least one embodiment of the electrical connecting conductor, the first conductor layer is part of the first Φ leadframe and the second conductor layer is part of the second leadframe. The second lead frames are interconnected in a single combined lead frame. As described at the outset, the lead frame is a metal plate in which a plurality of electrical connection conductors for a semiconductor component are connected to each other, and each of the electrical connection conductors is formed in the metal plate by a corresponding blank area in the board. The term "lead frame" is known, in particular to those skilled in the field of optoelectronics. The term "conductor layer" does not necessarily imply a one-piece layer. Conversely, the conductor layer may also have a plurality of partial layers spaced apart and adjacently disposed. 201025537 According to at least one embodiment of the electrical connection conductor, the first and second conductor layers each have at least one thinned region, wherein the thickness of the layer is less than the maximum layer thickness. Therefore, there is still greater variability in the formation of other functions or special forms and structures in the electrical connecting conductor. In this form of arrangement, the thinned region of the first conductor layer overlaps the thinned region of the second conductor layer in the lateral direction. The term "transverse" as used in this application refers to a direction extending parallel to the main extension surface of a corresponding conductor layer or electrical connection conductor. According to at least another embodiment, the first conductor layer has at least one cutout. This gap may for example be a hole in the conductor layer or a blank area which extends via the entire thickness of the conductor layer. The blank area can be open on at least one side, i.e., the blank area is not necessarily laterally surrounded by the material of the conductor layer on all sides. When the first conductor layer has a plurality of spaced apart partial layers, the blank area is a gap between the plurality of partial layers. According to at least one arrangement of this embodiment, the first conductor layer has a thinned region adjacent to the gap. According to at least one arrangement of this embodiment, the second conductor layer has a thinned region which overlaps the notch of the first conductor layer in the lateral direction. This gap and the thinned area can completely overlap. However, it is also possible for only one portion to overlap each other, i.e., the gap may partially offset the thinned region in the lateral direction. According to another arrangement, the area of the opening in the top view of the first conductor layer is smaller than the area of the second conductor layer which is thinned by the gap of the second conductor layer in the plan view from -7 to 201025537. The top view refers to a pattern seen at a viewing angle perpendicular to the main extension surface of one of the conductor layers or the electrical connection conductors. Or, the opening area of the notch is larger in plan view than the area of the second conductor layer overlapping the notch in the plan view. In accordance with at least one embodiment, the first conductor layer has a portion that partially overlaps a portion of the second conductor layer in a lateral direction, wherein the portion of the first conductor layer and the second conductor layer are laterally The portion of the overlap is not © the material having the electrical connection conductor. In particular, there is a gap between the above two parts. In an arrangement, a portion of the first conductor layer is adjacent to the gap. According to at least another arrangement of the electrical connecting conductor, a portion of the first conductor layer is present on an edge and partially overlaps a portion of the second conductor layer, wherein the portion of the first conductor layer Between the portions of the two conductor layers is a region that does not have the material of the electrical connection conductor. In particular, there is a gap between the above two parts. At least another embodiment of the electrical connection conductor is designed in such a way that the first and second conductor layers are connected to each other by a connection medium. This connection medium is a good electrically conductive material and/or thermally conductive material in one arrangement. The connecting medium can be a flux or an electrically conductive adhesive. According to at least another embodiment of the electrical connecting conductor, a wafer mounting area is provided on a portion of the second conductor layer. The first conductor layer is disposed behind the second conductor layer on the side of the wafer mounting region. The wafer mounting area is in particular provided in a recess of the electrical connection conductor. 201025537 In at least another embodiment of the electrical connection conductor, there is at least one inner wall having a main extension surface extending obliquely to the main extension surface of the electrical connection conductor and facing the main extension surface of the electrical connection conductor The wafer mounting area is tilted. The inner wall thus formed serves as a reflector for the electromagnetic radiation emitted or received by the semiconductor wafer in the photovoltaic module. A semiconductor component is provided which, in at least one embodiment, has an electrical connection conductor. The electrical connection conductor is provided on the first side with a semiconductor wafer and an encapsulation material A, wherein the encapsulation material surrounds the semiconductor wafer and is formed on the electrical connection conductor. In other words, the encapsulating material is formed in a single piece and encloses the wafer and encloses the electrical connecting conductor in position. According to an embodiment, the semiconductor component is an optoelectronic semiconductor component. Semiconductor wafers are particularly suitable for emitting and/or receiving electromagnetic radiation. In accordance with at least another embodiment of the semiconductor component, the electrical connection conductor has at least a portion of the region overlapping the encapsulating material in a lateral direction on a second side facing the first side without the encapsulating substance and Other insulating materials. That is, at least a portion of the electrical connection conductor on the second side of the region does not have the encapsulating material in which the encapsulating material is present on the facing first side. The exposed portion of the electrical connection conductor on the second side is particularly an external electrical connection to the semiconductor component. In some embodiments not described above, the electrical connection conductor is completely surrounded by the encapsulation material in the encapsulation material and another portion of the electrical connection conductor is protruded from the encapsulation material in the encapsulation material The back is curved. According to another arrangement of the semiconductor component, the electrical connection conductor does not have the encapsulant in the region of the second 201025537 side that overlaps the semiconductor wafer in the lateral direction and does not have other electrically insulating material. The semiconductor wafer is, in particular, a light-emitting diode wafer, wherein the light-emitting diode wafer is not limited to a wafer emitting visible light but refers to all semiconductor wafers which are generally capable of emitting electromagnetic radiation. The semiconductor wafer in particular has a sequence of epitaxial semiconductor layers comprising an active layer in which electromagnetic radiation is generated. According to another embodiment, most or all of the encapsulating material transmits radiant radiation, and the transmissive portion of the radiant portion has a transmittance of at least electromagnetic radiation in the spectrum emitted by the semiconductor wafer. 50%, preferably 70%. According to a further embodiment of the semiconductor component, the second electrical connecting conductor has a first and a second conductor layer which are connected to each other via the facing main faces. The second electrical connection conductor is formed in accordance with at least one of the above embodiments. According to a further embodiment of the semiconductor component, the electrical connecting conductor overlaps the encapsulating material completely or at least 80% (preferably 90%) in the transverse direction. According to a further embodiment, the encapsulating substance can also be used for the second electrical connecting conductor. The present invention also provides a method of fabricating an electrical connection conductor for a semiconductor component. In this method, a first conductor layer and a second conductor layer are prepared. Each of the conductor layers has a main surface that is apart from each other. The first and second conductor layers are connected to each other via their main faces such that the major faces face each other. The connection of the first and second conductor layers is carried out, in particular, after the individual conductor layers have been prepared. Furthermore, at least a thinned region is formed in the bulk layer, in the second conductor layer or in the first and second conductor layers, wherein the layer thickness of each conductor layer is less than its largest layer thickness. The formation of the thinned regions can be performed after the first and second conductor layers are connected. The formation of the thinned regions can in particular also take place during the preparation of the corresponding conductor layers. The conductor layer is immediately formed in a thinned region. However, the thinned region can be formed in particular by material ablation or material deformation. Other advantages and preferred embodiments of the electrical connecting conductor, semiconductor component and method of manufacturing the same according to the present invention will be described below with reference to the embodiments in the drawings. [Embodiment] Each of the components in the drawings and the embodiments having the same or the same functions is provided with the same reference numerals. The components shown and the ratios between the components are not necessarily drawn to scale. Conversely, some details of the various figures have been shown for clarity. Q FIG. 1 shows the first conductor layer 11 and the second conductor layer 12. The first and second conductor layers have a plurality of thinned regions, which will be detailed in Figure 2. The first conductor layer 11 additionally has a plurality of notches. These notches can be formed, for example, by holes. However, the indentations may also be blank areas which are open on at least one side or separate the different visible portions of the first conductor layer which are different in Figure 1 from each other. In other words, the first conductor layer 11 also has a plurality of mutually separated portions. Both the first and second conductor layers have a conductive material. In particular, the individual conductor layers can also consist entirely of electrically conductive materials. Or only part of each conductor layer consists of -11 - 201025537 conductive material. However, a substantial portion (e.g., greater than 50%, greater than 75% or greater than 80%) of each conductor layer is preferably comprised of a conductive material. The conductor layers 11, 12 have or consist of a metallic material. The two conductor layers, for example, may be mostly composed of copper. Alternatively, each conductor layer may be coated, for example, with at least another metal (e.g., gold, silver or tin). The maximum thickness 13 of the two conductor layers 11, 12 or one of the conductor layers is, for example, 0.1 mm, 0.15 mm or 0.2 mm. In particular, it is also possible to use a conductor layer having a maximum thickness 23 which is not the same. For example, the first conductor layer 11 has a maximum thickness of 0.15 mm, and the second conductor layer 12 has a maximum thickness of 0.4 mm, or vice versa. In order to form the electrical connecting conductor 10, the first and second conductor layers 11, 12 are to be connected to each other by a connecting material 3, see Fig. 2. The joining material 3 is, for example, a solder or an electrically conductive adhesive. Basically, electrically insulating connecting materials can also be used. After the first conductor layer 11 and the second conductor layer 12 are interconnected by the connecting material 3, at least some of the thinned regions of the first conductor layer 11 and some of the notches 4 may also be produced first. As shown in FIG. 2, the electrical connection conductor 1 can be provided in a technically simple manner by using at least two conductor layers 11, 12, which can be inexpensive in different ways or The cost is not very high to make. In the electrical connecting conductor 1 shown in Fig. 2, the first conductor layer π has a thinned region 111 on the first edge which overlaps with the thinned region 121 of the second conductor layer 12 in the lateral direction. . Between the thinned region -12-201025537 111 of the first conductor layer and the thinned region 121 of the second conductor layer is a region of material that is not provided with a conductor. In Fig. 2, the entire area of the plurality of thinned regions does not have the electrical connecting conductor on the edges 111, 121. However, a portion of the region may also have the material connecting material 3 of the electrical connecting conductor, for example, To the area. The gap on the edge of one of the electrical connection conductors acts as a fixing element for the encapsulating material in the assembly to be fabricated, greatly reducing the risk of delamination of the encapsulating material and electrical connection. When the gaps between the portions of the second layer 11 and the second conductor layer 12 are at least entrapped by the encapsulating material, the electrical connection structure shown in FIG. 2 can also be used as an envelope. a fixed component for a substance. The thinned region 112 shown in Fig. 2 of the first conductor layer 11 is adjacent to the notch 4. Further, each of the regions 112, 113 protrudes in a portion of the thinned region 122 of the lateral second conductor layer 12, respectively, which forms a gap. Further, a notch is also formed in the electrical connection conductor 10. The cross section of the crucible is enlarged in plan view and extends from the first conductor layer 11 to the second conductor layer 12. Such a recess can be used, for example, as a pure fixing of the electrical connecting conductor 10. The bottom of such a recess can also be used as a mounting surface of a semiconductor wafer in which the conductor wafer is disposed. In Fig. 2, the center of the electrical connecting conductor 1 has another recess. The thinned regions 114, 115 of the bulk layer are adjacent in this recess to a thinned region 123 which protrudes from the second conductor layer 12 in the lateral direction. There is material between the electrical connections. For example, the conductor may be connected to a conductor, and a portion of the body is 1 1 3 which is an outer member of the recess. There is a gap between the thinned regions 114, 115 of the bulk layer 11 and the thinned regions 123 of the second conductor layer 12 of the first guide port 4 and the first lead -13 - 201025537. The difference from the previous notch is that this notch has another form of cross section. Starting from the outer side of the first conductor layer 11, the cross-section of the recess first becomes smaller in the interior of the recess so as to become larger again in the region of the second conductor layer 12. The thinned regions 114, 115 of the first conductor layer adjacent to the gap 4 are formed in a portion of the conductor layer 11 that is different from the thinned regions 112, 113, the portion being facing the second conductor The layer 12 is formed as a main surface of the first conductor layer 11 © , whereby the first conductor layer 11 and the second conductor layer 12 are connected. In the embodiment of the electrical connection conductor shown in Fig. 2, the first conductor layer 11 has a further thinned region 116 which partially overlaps the second conductor layer 12 in the lateral direction. Here, only a portion of the area between the thinned region 116 and the portion of the second conductor layer 12 that is protruded by the region 116 does not have the material of the electrical connection conductor 10. This is achieved by "the thinned region 124 of the second conductor layer 12 is only partially overlapped with the thinned region 116". The thinned region 124 of the second conductor layer 12 also has only one portion in the lateral direction overlapping the other notch 4, and the thinned region 116 is adjacent to the notch 4. By overlapping a portion in the lateral direction as described above, structural elements smaller than the respective conductor layers 11 and 12, such as protruding portions or openings, can be effectively formed in the electrical connecting conductor 10. When the thinned regions and the notches are formed by etching in a conductor layer composed of a metal, the minimum extent of the thinned region and the lateral extent of the notch is on the order of the maximum thickness of the unstructured conductor layer (order )in. -14- 201025537 On the second edge of the electrical connection conductor 10, the first conductor layer 11 has an unthinned portion 118 which is protruded from the second portion 12 of the second conductor layer 12 in the lateral direction. A gap is formed between the portions 118, 125 of the conductor layers π, 12. This gap can also serve as a fixing element for the encapsulating material. Figures 3 through 9 show an embodiment of a semiconductor component, respectively. The semiconductor component is, for example, a photovoltaic component, for example, a light emitting diode assembly having a first electrical connection conductor 10 and a second electrical connection conductor 20. The first electrical connection I conductor 1 has a wafer mounting area 5 on which a semiconductor wafer 50 is mechanically and electrically conductively mounted. The semiconductor wafer 50 is, for example, a light-emitting diode wafer having a sequence of epitaxial semiconductor layers surrounding the active layer. In particular, the active layer can consist of a plurality of partial layers, which can in particular also have different material compositions. The semiconductor layer sequence has, for example, a III-V compound-semiconductor material. The III-V-compound semiconductor material has at least one element from the third group (e.g., boron, aluminum, gallium, indium) and an element from the fifth group (e.g., nitrogen, phosphorus, antimony). The commemorative "III-V-compound semiconductor material" particularly includes a group of a binary, ternary or quaternary compound containing at least one element from the third group and at least one element from the fifth group. For example, nitride and phosphide compound semiconductors. Such binary, ternary or quaternary compounds may additionally have one or more dopant species as well as other components. The active layer 11 preferably includes a pn junction, a double heterostructure, a single quantum well (SQW) or, in particular, a multi quantum well (MQW) to generate radiation. This name quantum well junction -15- 201025537 The structure does not indicate the dimension of quantization. Thus, quantum well structures can additionally contain sub-lots, quantum wires, and quantum dots, as well as each combination of these structures. For example, the MQW-structure has been known to those skilled in the art. In the embodiments shown in Figures 3, 4, 5, 8, and 9, the wafer mounting regions 5 are formed in the first The outer surface of one of the second conductor layers 12 of the connecting conductor 10 is connected. The first conductor layer 11 is located behind the second conductor layer 12 on the side of the wafer mounting region 5. Therefore, at least a portion of the semiconductor wafer 50 is surrounded by the material of the first electrical connecting conductor 1 in the lateral direction. In other words, the semiconductor wafer 50 is disposed in one of the recesses of the first electrical connection conductor 10. On the wafer mounting region 5 and this side of the semiconductor wafer 50, the first electrical connection conductor 10 and the semiconductor wafer 50 are provided with an encapsulating material 9 of the semiconductor component. This encapsulating material 9 encloses the semiconductor wafer 50 and is formed on the electrical connection conductor 10. On the side of the electrical connection conductor 10 that faces the wafer mounting area 5, the electrical connection conductor 10 does not have the encapsulating material and other electrically insulating material. The area of the outer surface of the first electrical connection conductor ίο serves, for example, as an external electrical contact surface 81 of the semiconductor component. In the embodiments shown in Figs. 3, 4, and 8, the wafer mounting region 5 is formed on one of the outer surfaces of the thinned regions 122 of the second conductor layer 12. When the wafer mounting region 5 is formed on the outer surface of the thinned region 122 of the second conductor layer 12, the spacing between the wafer mounting region 5 and the external electrical contact surface 81 can be made particularly small. Thus, the thermal resistance between the semiconductor wafer 50 and the electrical contact 16 - 201025537 face 81 can be made particularly small, which has a good effect on the operation, power and durability of the semiconductor component. However, a particularly small thermal resistance is usually achieved when the wafer mounting region 5 is formed on one of the outer surfaces of the second conductor layer (ie, the "lower conductor layer" away from the main radiation direction). Whether the wafer mounting area is formed in an area that is not thinned or thinned. For example, when the first conductor layer is composed of copper, the thickness of the conductor layer only has a small effect on the thermal resistance. On the contrary, when the wafer mounting region 5 is formed on the outer surface of one of the first conductor layers (i.e., "above"

G 在主輻射方向中配置在第二導體層之後的導體層）上時則 可依據第二層和第一層之間的佈置而造成一種蓄熱現象。 這對於熱阻而言會造成不良作用。因此，基本上亦可在第 二導體層之外表面上形成該晶片安裝區5，請參閱第6圖 和第7圖。 在第5圖和第9圖所示之半導體組件之實施例中，晶片 安裝區5分別形成在第二導體層12之一部份之一外表面 φ 上，該一部份之厚度等於第二導體層之最大厚度。 在第5圖所示之實施例中，第二導體層12在邊緣上分別 具有薄化的區域121、122。 反之，第9圖之半導體組件例如具有第一電連接導體10 之第二導體層12，其未具有薄化的區域。在此種情況下， 第二導體層12例如由厚度爲定値之金屬板所形成。 在第3圖、第5圖、第8圖、和第9圖所示之實施例中， 配置有半導體晶片50之凹口形成爲一種固定元件，其中第 -17- 201025537 一導體層11之一些部份和第二導體層12之由第一導 突出之部份之間存在著由包封物質9來塡充之間隙。 與上述實施例不同之處是，第4圖所示之半導體組 有一有邊緣之凹口，該凹口可作爲反射器。第4圖之 例中，晶片安裝區5由該凹口之至少二個內壁所包圍 片安裝區5之主延伸面51是傾斜於電連接導體10之 伸面而延伸且與電連接導體10之主延伸面比較時是 _ 晶片安裝區5而傾斜。 第4圖中顯示多個內壁，其由多個矩形之階梯來形 然而，實際上其不是矩形之階梯而是有一部份成弧形 形化的面。當藉由蝕刻而在厚度固定之金屬板中形成 口 4、第一導體層之薄化的區域112、113和第二導體Λ 之薄化的區域1 22時，則形成凹形之弧形。內壁之階 此種凹形的弧形顯示在第12圖所示之區段中。 內壁亦能以其它方式來形成。又，亦可採用其它措 〇 以使內壁平滑。第12圖中藉由虛線來表示：平滑化之 之延伸和形式。邊緣之平滑化或去除例如可藉由電力 或類似方法來達成。內壁廣泛地形成，使半導體晶片 電磁輻射可在內壁上轉向至半導體組件之發射方向中 當該電連接導體10之內壁形成爲反射器時，如第4 第12圖所示，有利的方式是使形成有晶片安裝區50 口之底部儘可能深，因此使”反射器”儘可能高地超 片5。例如，第二導體層12之薄化的區域122較第二 體層 件具 實施 ，晶 主延 朝向 成。 之圓 該缺 f 121 梯之 施， 內壁 拋光 50之 〇 圖和 之凹 過晶 導體 -18- 201025537 層之最大厚度薄了至少60%、至少70%或至少80%。此外， 整個電連接導體10例如具有至少4毫米、至少5毫米或至 少6毫米之總厚度。 第6圖和第7圖所示的實施例中，晶片安裝區5形成在 第一導體層11之外表面上。第二導體層12配置在第一導 體層11之遠離該晶片安裝區5之一側上。 第6圖所示之實施例中，第一導體層11例如不具有缺口。 I 與上述實施例不同之處是，第7圖所示之實施例中第一 ❹ 電連接導體10之第一導體層11具有一缺口 4,其與薄化的 區域112、113相鄰接，以形成一固定元件。然而，此固定 元件之凹口未具有半導體晶片50。 該包封物質9例如具有矽樹脂或至少一大部份是由矽樹 脂所構成。該包封物質9之一部份例如形成一透鏡91。該 包封物質9例如在橫向中分別完全圍繞第一電連接導體10 和第二電連接導體20且在一側上完全覆蓋各個電連接導 ❹ 體10 、 20 。 與所示的圖式不同，該包封物質9例如同樣可覆蓋電連 接導體之遠離半導體晶片之一側的一部份。在此種情況 下’電連接導體1〇、20之其它部份亦未具備該包封物質9 和其它電性絕緣材料且在第一電連接導體1〇時形成電性 接觸面81’在第二電連接導體20時形成電性接觸面82。 第二電連接導體20類似於第一電連接導體而具有至少 一第一導體層21和一第二導體層22。第一電連接導體10 -19- 201025537 及/或第二電連接導體20亦可具有其它導體層，但其未顯 示在實施例中。 半導體晶片50例如藉由連接線6而可導電地與第二電連 接導體20之內部電性連接面7相連接。在與該內部電性連 接面7相面對的一側上，第二電連接導體具有外部電性連 接面82，其未具有絕緣材料。亦可不使用該連接線6,此 時使用其它的電性連接媒體使半導體晶片50可與第二電 連接導體20形成可導電的連接。 ❹ 電連接導體10、20中之至少一個亦能以單件方式或單一 部份來形成。 第3圖、第4圖、第5圖、第7圖、第8圖和第9圖之 實施例中，第二電連接導體都以相同形式來形成，其在第 一導體層21中分別具有第一薄化的區域211，此區域211 在橫向中由第二導體層22之第一薄化的區域221突出。第 一薄化的區域211、221之間存在一間隙。又，第一導體層 Q 21具有第二薄化的區域212，其在橫向中由第二導體層22 之第二薄化的區域222突出。在各薄化的區域212、222之 間存在一間隙。 第6圖所示的實施例中，第二電連接導體20之第一導體 層具有薄化的區域211、212，其與第一導體層21之缺口 4 相鄰接。第二電連接導體20之第二導體層22例如未具有 薄化的區域。內部接觸面7是由第二導體層22之外表面來 形成。 -20- 201025537 第10圖顯示第3圖、第4圖、第5圖、第8圖或第9圖 之半導體組件之俯視圖之第一實施例。此實施例中該半導 體晶片50在橫向中完全由第一連接層11和可能存在之第 二連接層12之一些部份所包圍。換言之，電連接導體10 存在一缺口，其中配置著該半導體晶片50，其在全部的側 面上都具有內壁* 與上述形式不同之處是，第11圖所示之俯視圖中，配置 ^ 有半導體晶片50之該凹口是一種在二個相對側敞開的溝 Ο 渠。此實施例中，第3圖、第4圖'第5圖、第8圖和第9 圖之切面圖亦可以是半導體組件之側視的俯視圖，此乃因 該凹口在二側上是側面敞開者。 本發明當然不限於依據各實施例中所作的描述。反之， 本發明包含每一新的特徵和各特徵的每一種組合，特別是 包含各申請專利範圍或不同實施例之各別特徵之每一種組 合，當相關的特徵或相關的組合本身未明顯地顯示在各申 Q 請專利範圍中或各實施例中時亦屬本發明。 【圖式簡單說明】 第1圖是本發明第一實施例中電連接導體或半導體組 件之製造期間第一和第二導體層之切面圖。 第2圖是第一實施例之電連接導體之切面圖，其具有 第1圖所示的導體層。 第3圖是第一實施例之半導體組件之切面圖。 第4圖是第二實施例之半導體組件之切面圖。 -21- 201025537 第5圖是第三實施例之半導體組件之切面圖。 第6圖是第四實施例之半導體組件之切面圖。 第7圖是第五實施例之半導體組件之切面圖。 第8圖是第六實施例之半導體組件之切面圖。 第9圖是第七實施例之半導體組件之切面圖。 第10圖是第3圖、第5圖、第8圖或第9圖所示之半 導體組件之第一例的俯視圖。When G is disposed on the conductor layer behind the second conductor layer in the main radiation direction, a heat storage phenomenon can be caused depending on the arrangement between the second layer and the first layer. This can have an adverse effect on the thermal resistance. Therefore, the wafer mounting region 5 can be formed substantially on the outer surface of the second conductor layer, see Figs. 6 and 7. In the embodiment of the semiconductor device shown in FIGS. 5 and 9, the wafer mounting regions 5 are respectively formed on the outer surface φ of one of the portions of the second conductor layer 12, the thickness of the portion being equal to the second The maximum thickness of the conductor layer. In the embodiment shown in Fig. 5, the second conductor layer 12 has thinned regions 121, 122 on the edges, respectively. On the other hand, the semiconductor component of Fig. 9 has, for example, a second conductor layer 12 having a first electrical connection conductor 10 which does not have a thinned region. In this case, the second conductor layer 12 is formed, for example, of a metal plate having a predetermined thickness. In the embodiments shown in FIGS. 3, 5, 8, and 9, the recess in which the semiconductor wafer 50 is disposed is formed as a fixing member, wherein some of the conductor layers 11 of -17-201025537 are formed. There is a gap between the portion and the portion of the second conductor layer 12 that is covered by the first guiding protrusion. The difference from the above embodiment is that the semiconductor group shown in Fig. 4 has an edge recess which serves as a reflector. In the example of Fig. 4, the wafer mounting region 5 is surrounded by at least two inner walls of the recess, and the main extension surface 51 of the sheet mounting region 5 extends obliquely to the extension surface of the electrical connection conductor 10 and is electrically connected to the conductor 10. The main extension surface is tilted when compared to the wafer mounting area 5. Fig. 4 shows a plurality of inner walls which are formed by a plurality of rectangular steps. However, in reality, they are not rectangular steps but have a portion which is curved. When the opening 4, the thinned regions 112, 113 of the first conductor layer, and the thinned region 1 22 of the second conductor 形成 are formed in the metal plate having a fixed thickness by etching, a concave arc shape is formed. The step of the inner wall The curved shape of this concave shape is shown in the section shown in Fig. 12. The inner wall can also be formed in other ways. Further, other measures may be employed to smooth the inner wall. In Fig. 12, it is represented by a broken line: the extension and form of smoothing. Smoothing or removal of the edges can be achieved, for example, by electricity or the like. The inner wall is widely formed so that the semiconductor wafer electromagnetic radiation can be deflected on the inner wall into the emission direction of the semiconductor component. When the inner wall of the electrical connection conductor 10 is formed as a reflector, as shown in FIG. 4, it is advantageous. This is done by making the bottom of the wafer mounting area 50 as deep as possible, thus causing the "reflector" to superseat 5 as high as possible. For example, the thinned region 122 of the second conductor layer 12 is implemented as compared to the second bulk layer. The round of the lack of f 121 ladder, the inner wall is polished 50 〇 and the concave crystal conductor -18- 201025537 The maximum thickness of the layer is at least 60%, at least 70% or at least 80%. Furthermore, the entire electrical connecting conductor 10 has, for example, a total thickness of at least 4 mm, at least 5 mm or at least 6 mm. In the embodiment shown in Figs. 6 and 7, the wafer mounting region 5 is formed on the outer surface of the first conductor layer 11. The second conductor layer 12 is disposed on a side of the first conductor layer 11 away from the wafer mounting region 5. In the embodiment shown in Fig. 6, the first conductor layer 11 does not have a notch, for example. I differs from the above embodiment in that the first conductor layer 11 of the first ❹ electrically connecting conductor 10 in the embodiment shown in Fig. 7 has a notch 4 which is adjacent to the thinned regions 112, 113. To form a fixed component. However, the recess of this fixing member does not have the semiconductor wafer 50. The encapsulating material 9 has, for example, a resin or at least a large portion of the resin. A portion of the encapsulating material 9 forms, for example, a lens 91. The encapsulating substance 9 completely surrounds the first electrical connecting conductor 10 and the second electrical connecting conductor 20, respectively, in the transverse direction and completely covers the respective electrical connecting conductors 10, 20 on one side. In contrast to the illustrated embodiment, the encapsulating material 9 can, for example, also cover a portion of the electrical connection conductor that is remote from one side of the semiconductor wafer. In this case, the other portions of the electrical connecting conductors 1 and 20 are not provided with the encapsulating material 9 and other electrically insulating materials, and the electrical contact surface 81' is formed at the first electrical connecting conductor 1〇. When the two conductors 20 are electrically connected, an electrical contact surface 82 is formed. The second electrical connection conductor 20 has at least a first conductor layer 21 and a second conductor layer 22 similar to the first electrical connection conductor. The first electrical connection conductor 10 -19-201025537 and/or the second electrical connection conductor 20 may also have other conductor layers, but it is not shown in the embodiment. The semiconductor wafer 50 is electrically conductively connected to the internal electrical connection surface 7 of the second electrical connection conductor 20, for example by means of a connecting line 6. On the side facing the internal electrical connection face 7, the second electrical connection conductor has an external electrical connection face 82 which is not provided with an insulating material. The connection line 6 may also be omitted, and other electrically conductive media may be used to form the electrically conductive connection of the semiconductor wafer 50 with the second electrical connection conductor 20. At least one of the electrical connection conductors 10, 20 can also be formed in a single piece or in a single piece. In the embodiments of FIGS. 3, 4, 5, 7, 8, and 9, the second electrical connection conductors are all formed in the same form, respectively having the first conductor layer 21 The first thinned region 211, which is protruded in the lateral direction by the first thinned region 221 of the second conductor layer 22. There is a gap between the first thinned regions 211, 221. Further, the first conductor layer Q 21 has a second thinned region 212 which is protruded in the lateral direction by the second thinned region 222 of the second conductor layer 22. There is a gap between each of the thinned regions 212, 222. In the embodiment shown in Fig. 6, the first conductor layer of the second electrical connection conductor 20 has thinned regions 211, 212 adjacent to the gap 4 of the first conductor layer 21. The second conductor layer 22 of the second electrical connection conductor 20, for example, does not have a thinned region. The inner contact surface 7 is formed by the outer surface of the second conductor layer 22. -20- 201025537 Fig. 10 shows a first embodiment of a plan view of the semiconductor component of Fig. 3, Fig. 4, Fig. 5, Fig. 8, or Fig. 9. In this embodiment, the semiconductor wafer 50 is completely surrounded by the first connecting layer 11 and portions of the second connecting layer 12 which may be present in the lateral direction. In other words, the electrical connection conductor 10 has a notch in which the semiconductor wafer 50 is disposed, which has an inner wall on all sides*. The difference from the above-described form is that in the plan view shown in Fig. 11, the semiconductor is disposed. The recess of wafer 50 is a trench that is open on two opposite sides. In this embodiment, the cut-away view of FIG. 3, FIG. 4', FIG. 5, FIG. 8, and FIG. 9 may also be a side view of the semiconductor component, since the recess is lateral on both sides. Opener. The invention is of course not limited to the description made in accordance with the various embodiments. Conversely, the invention encompasses each novel feature and each combination of features, and in particular, each of the various features of the various claims or the various embodiments. The invention is also shown in the scope of the patent application or in the respective embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing first and second conductor layers during manufacture of an electrical connecting conductor or a semiconductor component in a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the electrical connecting conductor of the first embodiment, which has the conductor layer shown in Fig. 1. Fig. 3 is a cross-sectional view showing the semiconductor device of the first embodiment. Fig. 4 is a cross-sectional view showing the semiconductor device of the second embodiment. -21- 201025537 Fig. 5 is a cross-sectional view showing the semiconductor component of the third embodiment. Fig. 6 is a cross-sectional view showing the semiconductor device of the fourth embodiment. Figure 7 is a cross-sectional view showing the semiconductor device of the fifth embodiment. Figure 8 is a cross-sectional view showing the semiconductor device of the sixth embodiment. Figure 9 is a cross-sectional view showing the semiconductor device of the seventh embodiment. Fig. 10 is a plan view showing a first example of the semiconductor component shown in Fig. 3, Fig. 5, Fig. 8, or Fig. 9.

第11圖是第3圖、第5圖、第8圖或第9圖所示之半 導體組件之第二例的俯視圖。 第12圖是第4圖所示之組件之一部份的切面圖。 【主要元件符號說明】 3 連接媒體 4 缺口 5 晶片安裝區 6 連接線 7 第二電連接導體之內部連接面 9 包封物質 10 第一電連接導體 11 第一導體層 12 第二導體 13 第一導體層之最大厚度 14 第一導體層之薄化的區域之薄化後的厚度 20 第二電連接導體 -22- 201025537 21 第一導體層 22 第二導體層 23 第二導體層之最大厚度 24 第二導體層之薄化的區域之厚度 50 半導體晶片 51 內壁之傾斜之主延伸面 81 第一電連接導體之外部連接面 _ 82 第二電連接導體之外部連接面 ❹ 9 1 透鏡 111、 112、 113、 114、 115、 116、 117 第一電連接 導體之第一導體層之薄化的區域 118、119 第一電連接導體之第一導體層之未薄化的區域 121、122、123、124、125 第一電連接導體之第二導 體層之薄化的區域 128、129 第一電連接導體之第二導體層之未薄化的區域 〇 211、212 第二電連接導體之第一導體層之薄化的區域 221、222 第二電連接導體之第二導體層之薄化的區域 -23-Fig. 11 is a plan view showing a second example of the semiconductor component shown in Fig. 3, Fig. 5, Fig. 8, or Fig. 9. Figure 12 is a cross-sectional view of a portion of the assembly shown in Figure 4. [Main component symbol description] 3 Connection medium 4 Notch 5 Wafer mounting area 6 Connection line 7 Internal connection surface of second electrical connection conductor 9 Encapsulation material 10 First electrical connection conductor 11 First conductor layer 12 Second conductor 13 First Maximum thickness of the conductor layer 14 Thinned thickness of the thinned region of the first conductor layer 20 Second electrical connection conductor-22- 201025537 21 First conductor layer 22 Second conductor layer 23 Maximum thickness of the second conductor layer 24 The thickness 50 of the thinned region of the second conductor layer is the main extension surface 81 of the inner wall of the semiconductor wafer 51. The external connection surface of the first electrical connection conductor _ 82 the external connection surface of the second electrical connection conductor ❹ 9 1 lens 111, 112, 113, 114, 115, 116, 117 thinned regions 118, 119 of the first conductor layer of the first electrical connection conductor, unthinned regions 121, 122, 123 of the first conductor layer of the first electrical connection conductor , 124, 125 thinned regions 128, 129 of the second conductor layer of the first electrical connection conductor, unthinned regions 211, 212 of the second conductor layer of the first electrical connection conductor, first of the second electrical connection conductor guide Thinned region of the bulk layer 221, 222 Thinned region of the second conductor layer of the second electrical connection conductor -23-

Claims (1)

201025537 七、申請專利範圍： 1. 一種用於半導體組件之電連接導體，包括第一和第二導 體層，其經由互相面對之主面而互相連接，其特徵爲： 該第一、第二導體層、或該第一和第二導體層具有至少一 薄化的區域，其中該薄化的區域之層厚度小於其最大的層 厚度。 2. 如申請專利範圍第1項之電連接導體，其中在該電連接 ^ 導體之第一側上形成一種包封物質，其具有矽樹脂》 3·如申請專利範圍第2項之電連接導體，其中該電連接導 體在與該第一側相面對的第二側上，在橫向中與該包封物 質相重疊之區域中，未具有該包封物質和電性絕緣材料。 4.如申請專利範圍第1至3項中任一項之電連接導體，其 中該第一導體層是第一導線架之一部份且第二導體層是 第二導線架之一部份，其中該第二導線架在唯一之組合式 導線架中互相連接。 〇 5.如申請專利範圍第1至4項中任一項之電連接導體，其 中該第一和該第二導體層分別具有至少一薄化的區域，其 中該薄化的區域之層厚度小於其最大的層厚度，且特別$ 該第一導體層之該薄化的區域在橫向中是與該第二導鵝 層之該薄化的區域相重疊。 6.如申請專利範圍第1至5項中任一項之電連接導體，其 中該第一導體層具有至少一凹口，且特別是該第一導體墙 具有一薄化的區域，其鄰接於該第一導體層之缺口。 -24- 201025537 7. 如申請專利範圍第6項之電連接導體，其中該第二導體 層具有一薄化的區域，且該第一導體層之缺口在橫向中與 該第二導體層之薄化的區域相重疊。 8. 如申請專利範圍第6或7項之電連接導體，其中該第一 導體層之與該缺口相鄰接的部份在橫向中由該第二導體 層之一部份中突出，且介於此二個部份之間的區域未具有 該電連接導體之材料。 9. 如申請專利範圍第1至8項中任一項之電連接導體，其 ❹ 中在一邊緣上存在著該第一導體層之一部份，其在橫向中 由該第二導體層之一部份突出，且介於此二個部份之間的 區域未具有該電連接導體之材料。 10. 如申請專利範圍第1至9項中任一項之電連接導體，其 中該第一和該第二導體層藉由一連接媒體而互相連接。 11. 如申請專利範圍第1至10項中任一項之電連接導體， 其中晶片安裝區設置在該第二導體層之一部份上，且該第 〇 —導體層在該晶片安裝區之此側上配置在該第二導體層 之後。 12. 如申請專利範圍第11項之電連接導體，其中存在著至 少一內壁，其主延伸面傾斜於該電連接導體之主延伸面而 延伸，且在與該電連接導體之主延伸面比較下，朝向該晶 片安裝區而傾斜。 13. —種半導體組件，具有如申請專利範圍第丨至12項中 任一項之電連接導體，其中該電連接導體在第一側上設有 -25- 201025537 半導體晶片和包封材料，該包封材料包圍該半導體晶片且 形成在該電連接導Hi。 1 4.如申請專利範阖第丨3項之半導體組件，其中該電連接 導體在與該第一側相面對的第二側上，在橫向中與該包封 物質及/或該半導體晶片相重疊之區域中，未具有該包封 物質和電性絕緣材料 15.—種電連接導體之製造方法，包括以下各步驟： 製備第一和第二導體層都具有二個互相遠離的主面； 經由該二個主面而將該第一和該第二導體層相連接，使該 些主面互相面對； 在該第一、第二導體層中、該第一和該第二導體層中都形 成至少一薄化的區域，其中各導體層之層厚度小於其最大 的層厚度。 -26 -201025537 VII. Patent Application Range: 1. An electrical connection conductor for a semiconductor component, comprising first and second conductor layers interconnected by mutually facing main faces, characterized by: first and second The conductor layer, or the first and second conductor layers, has at least one thinned region, wherein the thinned region has a layer thickness less than its largest layer thickness. 2. The electrical connecting conductor of claim 1, wherein an encapsulating substance is formed on the first side of the electrical connecting conductor, which has an encapsulating resin. 3. The electrical connecting conductor of claim 2 Wherein the electrical connection conductor does not have the encapsulating material and the electrically insulating material in a region overlapping the encapsulating substance in a lateral direction on a second side facing the first side. 4. The electrical connection conductor of any one of clauses 1 to 3, wherein the first conductor layer is a portion of the first leadframe and the second conductor layer is a portion of the second leadframe, The second lead frame is interconnected in a single combined lead frame. The electrical connection conductor of any one of claims 1 to 4, wherein the first and second conductor layers respectively have at least one thinned region, wherein the thinned region has a layer thickness less than The largest layer thickness thereof, and particularly the thinned region of the first conductor layer, overlaps the thinned region of the second goose layer in the lateral direction. 6. The electrical connection conductor of any one of clauses 1 to 5, wherein the first conductor layer has at least one recess, and in particular the first conductor wall has a thinned region adjacent to a gap of the first conductor layer. The electrical connection conductor of claim 6, wherein the second conductor layer has a thinned region, and the notch of the first conductor layer is thinner in the lateral direction than the second conductor layer The areas of the overlap overlap. 8. The electrical connection conductor of claim 6 or 7, wherein a portion of the first conductor layer adjacent to the notch protrudes from a portion of the second conductor layer in a lateral direction, and The area between the two portions does not have the material of the electrical connection conductor. 9. The electrical connection conductor of any one of clauses 1 to 8, wherein a portion of the first conductor layer is present on an edge of the crucible, the second conductor layer being laterally A portion is prominent, and the area between the two portions does not have the material of the electrical connection conductor. 10. The electrical connection conductor of any one of clauses 1 to 9, wherein the first and second conductor layers are connected to each other by a connection medium. 11. The electrical connection conductor of any one of clauses 1 to 10, wherein the wafer mounting region is disposed on a portion of the second conductor layer, and the second conductor layer is in the wafer mounting region This side is disposed behind the second conductor layer. 12. The electrical connection conductor of claim 11, wherein there is at least one inner wall, the main extension surface of which extends obliquely to the main extension surface of the electrical connection conductor, and the main extension surface of the electrical connection conductor In comparison, it is tilted toward the wafer mounting area. 13. A semiconductor component having an electrical connection conductor according to any one of claims 12 to 12, wherein the electrical connection conductor is provided with a -25-201025537 semiconductor wafer and an encapsulation material on the first side, An encapsulation material surrounds the semiconductor wafer and is formed at the electrical connection. 1 . The semiconductor component of claim 3, wherein the electrical connection conductor is on a second side facing the first side, in the lateral direction, and the encapsulating material and/or the semiconductor wafer In the overlapping regions, there is no such encapsulating material and electrical insulating material. The manufacturing method of the electrical connecting conductor comprises the following steps: preparing the first and second conductor layers each having two main faces away from each other. Connecting the first and the second conductor layers via the two main faces such that the main faces face each other; in the first and second conductor layers, the first and second conductor layers At least one thinned region is formed in which the thickness of each conductor layer is less than its maximum layer thickness. -26 -
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