EP2225785B1 - Chipanordnung, anschlussanordnung, led sowie verfahren zur herstellung einer chipanordnung - Google Patents

Chipanordnung, anschlussanordnung, led sowie verfahren zur herstellung einer chipanordnung Download PDF

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Publication number
EP2225785B1
EP2225785B1 EP08854876.3A EP08854876A EP2225785B1 EP 2225785 B1 EP2225785 B1 EP 2225785B1 EP 08854876 A EP08854876 A EP 08854876A EP 2225785 B1 EP2225785 B1 EP 2225785B1
Authority
EP
European Patent Office
Prior art keywords
chip
leadframe
plane
connection
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP08854876.3A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2225785A2 (de
Inventor
Herbert Brunner
Steffen Köhler
Raimund Schwarz
Stefan GRÖTSCH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2225785A2 publication Critical patent/EP2225785A2/de
Application granted granted Critical
Publication of EP2225785B1 publication Critical patent/EP2225785B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers

Definitions

  • the invention relates to a chip arrangement for an optoelectronic component having at least one semiconductor chip emitting an electromagnetic radiation and to a method for producing such a chip arrangement.
  • a light-emitting diode also referred to as a light-emitting diode, is a very cost-effective and effective light source.
  • the starting point for the production of LED chips is a monocrystalline base material. Examples include silicon and germanium. Silicon has IV-valent silicon atoms, where IV-valent elements have four outer electrons for atomic bonds.
  • this base material donor or acceptor atoms are inserted into the crystal lattice of the base material.
  • specific properties, such as the conductivity of this base material are changed.
  • V-valent elements called donors
  • a V-valent element has five outer electrons available for atomic bonds, so that upon integration into the silicon crystal, an outer electron of the donor is freely available. This electron can do work when applying a voltage.
  • At the site of the donor atom creates a stationary positive bond that faces a negative charge of the free-floating electron.
  • phosphorus, arsenic or antimony is used for the n-doping of a base material.
  • III-valent elements in p-type doping, where p is the free-floating positive hole (hole), III-valent elements, called acceptors, are introduced into the silicon lattice and replace the IV-valent silicon atom. Similarly, III-valent elements have three outer electrons for atomic bonds. When a voltage is applied, this hole behaves like a freely movable positive charge carrier and can perform work analogously to the negatively charged electron. At the site of the acceptor atom, a stationary negative charge is created, which faces a positive charge of the free-moving hole.
  • a semiconductor device p for example, boron, indium, aluminum or gallium is used.
  • III-IV semiconductor gallium arsenide could be doped with the IV-valent elements carbon, silicon or gold.
  • LED chips require a so-called pn structure for emitting electromagnetic radiation, that is, a p-doped material is connected to an n-doped material.
  • a p-doped material is connected to an n-doped material.
  • an electrical voltage which is higher than the threshold voltage of the structure, light of a specific wavelength is emitted by this pn structure.
  • the wavelength, the intensity of the light and the level of the electrical voltage to be applied are dependent on the type of doping and the structure of the respective pn structure.
  • an LED chip (light-emitting semiconductor chip) is now not necessarily the same.
  • the p-doped layer may be arranged on an upper side of an LED chip, on the other hand on an underside of the LED chip.
  • These types of LED chips are referred to in the art as p-up n-down LED chips. It does not matter if there is a p-junction or an n-junction on the top.
  • the corresponding other connection point of an LED chip is located on the corresponding opposite side of the LED chip.
  • a substrate between the connection points is preferably not electrically insulating, that is to say electrically conductive, to be designed.
  • both the n-junction and the p-junction are arranged on an upper side of the LED chip.
  • the substrate should ideally be designed to be electrically insulating in such a case.
  • LED chips light-emitting semiconductor chips
  • the publication US 2007/0253209 A1 describes a package having a package body and having two radiation-emitting semiconductor chips in an opening therein.
  • the housing body has a conductor and a support on a heat sink made of copper, wherein the two carriers are electrically insulated from each other by the housing body.
  • the chips are each electrically contacted via the conductor and the carrier.
  • Object of the present invention is to arrange a plurality of differently structured semiconductor chips within a chip array, without having to design cost-intensive Verschaltungssche and beyond to realize optimal heat connection for each individual semiconductor chip.
  • a chip arrangement for an optoelectronic component having at least one semiconductor chip emitting an electromagnetic radiation and a connection arrangement, the connection arrangement having electrically insulated planes from each other and at least two electrically insulated conductors are arranged in at least two planes, in at least one Level has a cavity, the semiconductor chip is disposed within the cavity and the chip arrangement has at least two connection points, each of the connection points is electrically conductively connected to one of the conductors and at least one of the planes is a heat dissipation plane.
  • a second semiconductor chip which is not necessarily constructed like the first semiconductor chip, is introduced within the cavity.
  • the second semiconductor chip also has at least two connection points and each of the connection points is electrically conductively connected to one conductor each.
  • one of the two planes has at least one third conductor which is electrically insulated from the other conductors. If two different built-LED chips are now arranged within the chip arrangement, it is possible by means of this chip arrangement to interconnect both LED chips in series.
  • the second level is to be formed as electrically conductive in an advantageous manner.
  • the second connection point of the at least second semiconductor chip is connected to a further, electrically insulated conductor of the first level, whereby a separate driving of the LED chips can be realized.
  • the heat dissipation plane can be electrically non-conductive.
  • the giveawayableit Mrs is divided and the parts of the heat dissipation plane are spatially separated.
  • the second plane is formed as a common electrically insulated conductor.
  • the individual semiconductor chips can be connected to each other in series and / or in parallel. Due to the connection arrangement, it is possible in a simple manner to conceive of the at least two levels as simple as possible interconnection. As a result, different wavelengths, for example an RGB arrangement, can be controlled individually, flexibly and optimally. Furthermore, this can increase the light intensity of the chip arrangement.
  • the chip arrangement is provided with an optical element.
  • this optical element it is possible to deflect, to reflect or to focus the emitted electromagnetic radiation. As a result, an optimal illumination is achieved.
  • connection arrangement is equipped with a third plane, the holding plane, which is designed as a holding plane for the optical element.
  • the individual layers are electrically insulated and, moreover, inexpensive to produce.
  • the chip arrangement has electrical connections, which are designed in the form of plug contacts, solder pins or insulation displacement connection, which are electrically conductively connected to the individual conductors. In this way, for example, by means of ISO or IEC-standardized plug contacts, an electrical control to the chip arrangement can be produced.
  • the semiconductor chips are realized with an insulating platinum substrate.
  • both connection points of the LED chip are arranged on a first upper side of the LED chip.
  • the heat dissipation plane is in a further advantageous embodiment, a heat sink and directly connected to an electrically conductive heat sink heat sink.
  • the heat dissipation plane is preferably to be designed to be electrically conductive.
  • the inside of the chip arrangement Heat generated by the semiconductor chips is optimally dissipated.
  • an electrically conductive connection is simply realized.
  • connection arrangement for an optoelectronic component and an LED with a housing, a cover, electrical connections and a multi-chip arrangement.
  • connection arrangement for an optoelectronic component is preferably constructed from a plurality of mutually electrically isolated planes, at least two electrically insulated conductors being arranged in at least two planes, the individual planes being encapsulated by plastic, a first plane of the connection arrangement being a connection plane, and a second plane the connection arrangement is a heat dissipation plane.
  • connection arrangement preferably has a third plane, which is designed as a holding plane for an optical element.
  • the LED with a housing preferably has a cover, electrical connections and a connection arrangement, wherein the electrical connections are electrically conductively connected to the conductors and at least one second semiconductor chip is introduced into the cavity.
  • the heat dissipating plane is divided and the parts are spatially separated from each other such that for each semiconductor chip individually optimally heat can be dissipated to the housing.
  • the electrical connections plug contacts, solder pins and / or insulation displacement connections.
  • the semiconductor chips preferably have an electrically insulating platinum substrate.
  • the housing is directly heat-coupled with an electrically conductive heat sink.
  • a leadframe also referred to as conductor track frame
  • This intermediate material is preferably a stamped sheet or another stamped electrically conductive material. Punching makes the adjustments needed in each layer.
  • the heat dissipation plane is preferably a Division of the material for better heat dissipation completed. Again, the parts of the heat dissipating plane during manufacture by a frame surrounding the surface (frame) are still mechanically connected.
  • a third frame, the holding leadframe, is likewise inserted, the holding leadframe holding an optical element or the cover of the chip arrangement.
  • the semiconductor chips have a non-insulating substrate and are connected in series.
  • the heat dissipation layer is connected directly to an electrically conductive heat sink, which dissipates the heat generated by the semiconductor chips.
  • leadframes are introduced into the arrangement and encapsulated in a further process step by means of plastic, an insulation is first produced between the individual leadframes.
  • the still mechanically connecting frame are separated in a further process step, whereby only the punched areas remain and ideally no mechanical or electrical connection between the individual punches prevails.
  • the leadframes correspond to the connection arrangement as of this method step.
  • FIG. 1 shows an example of a chip arrangement.
  • a connection arrangement 2 with a first level 3 and a second level 4 is shown.
  • a semiconductor chip 1 is introduced.
  • a potting compound 13 is furthermore providable.
  • the individual levels 3 and 4 of the terminal assembly 2 are electrically insulated from each other.
  • the individual layers 3 and 4 are encapsulated with a plastic material 15.
  • a cover 11 closes off the cavity 6 and protects the semiconductor chips from external influences.
  • the first level 3 has a first conductor 9.
  • the semiconductor chip 1 is electrically conductively connected to the first conductor 9 by means of a first connection point 7.
  • the connection is preferably to be realized by means of bonding methods.
  • the second level 4 here has a second conductor 10.
  • the second connection point 8 of the semiconductor chip 1 is electrically conductively connected to the second conductor 10.
  • the two connection points 7 and 8 are often referred to in the art as anode and cathode, in which case it remains open which connection point 7 or 8 is specifically anode or cathode.
  • One function of the semiconductor chip, that is to say the illumination of the LED, is to be aimed at in each circuit concept, whereby the second level 4 is to be formed in an electrically conductive manner.
  • the conductors 9, 10 are located in a first and a second leadframe, respectively, and after the assembly is overmolded, the frame that mechanically connects the conductors during manufacture is removed.
  • These lead frames correspond to the respective level 3 or 4.
  • FIG. 2 a development of the invention shown in Figure 1 chip assembly is shown. The following is merely to the differences between FIG. 1 and Figure 2 received.
  • at least one second semiconductor chip 1 is introduced in the cavity 6. Its first connection point 7 is connected, ideally by means of a bonding connection, to a third connection contact 16 of the first level 3.
  • the second connection point 8 of the second semiconductor chip 1 is likewise connected in an electrically conductive manner to the second conductor 10 of the second plane 4.
  • the at least two semiconductor chips 1 can now be, for example, differently constructed semiconductor chips 1.
  • FIG. 8 directed.
  • the second level 4 is the common reference point. Either the anode or the cathode of the semiconductor chip 1 can be switched to the common reference point. Operation of the individual semiconductor chips 1 is now achieved via an individual voltage control via the first level 3.
  • FIGS. 3A and 3B each show a plan view of a chip arrangement FIG. 2 ,
  • four semiconductor chips 1 are incorporated in a chip arrangement.
  • the second connection points 8 of the semiconductor chip 1 are all connected by means of the second level 4, which is designed to be electrically conductive.
  • further electrical conductors are provided in the first plane for the third and fourth semiconductor chip 1.
  • the cover 11 is fitted in the plastic material 15.
  • the respective semiconductor chips 1 are constructed differently. Again, let's get back to clarification FIG. 8 directed.
  • the chips 1 are interconnected in series.
  • the voltage to be applied must be higher than the threshold voltage of all series-connected semiconductor chips 1 in order to ensure that the semiconductor chips 1 shine.
  • the second level 4 is thus provided only as a heat dissipation level. It does not necessarily have to be designed to be electrically conductive in this case.
  • the second level 4 is formed electrically insulating. Since both connection points 7, 8 are arranged on an upper side of the semiconductor chips, an insulating substrate is inside the Semiconductor chips 1 vorsehbar. Thus, each semiconductor chip 1 is driven separately.
  • FIG. 4 is a further education of in FIG. 3A shown chip arrangement shown. In contrast to FIG. 3A is in FIG. 4 spatially split the second level.
  • the division of the second level 4 By the division of the second level 4 an optimal heat dissipation is obtained.
  • the division of the second level 4 does not necessarily have to be symmetrical, but rather is to be adapted to the heat dissipation requirements of the differently constructed semiconductor chips 1.
  • the control and the introduction of the individual semiconductor chips 1 is similar to the in FIG. 3A described scenario.
  • the electrical conductivity of the entire layer 4 is given.
  • Not shown is a breakdown of the heat dissipation level for in FIG. 3B illustrated embodiment. Since each chip is individually controllable herein, the heat dissipation plane and also the heat sink can be made electrically insulating.
  • FIG. 5 an LED with one of the previously described chip arrangement is shown.
  • a lens is provided as the optical element 14 instead of the cover 11.
  • this optical element 14 it is possible in a simplified manner to focus, diffuse or deflect the light beams.
  • connection arrangement 2 here has three levels, wherein the third level 5 serves as a holding plane for the optical element 14.
  • the lens is preferably made of silicone or another thermoplastic. Epoxies are preferably introduced by injection molding between the individual layers 3, 4 and 5 of the connection arrangement 2 and thereby generate the electrical insulation of the individual planes.
  • the third level 5 can also be produced by means of a leadframe in a production method.
  • three surfaces are thus to be punched out to produce such a chip arrangement. These surfaces have the necessary properties for the respective level in terms of electrical and thermal conductivity.
  • different materials can be used per leadframe.
  • the leadframes are encapsulated after their production and arrangement by means of plastic. For this purpose, an injection molding method is preferred. As a result, on the one hand electrical isolation of the individual leadframes is achieved, on the other hand a simplified interconnection of differently constructed semiconductor chips 1 is made possible by this multi-layer leadframe fabrication. After the encapsulation, the frames are removed around the individual conductors 9, 10, 16 or the heat dissipating plane 4 and the holding plane 5.
  • the electrical connections 12 serve as SMT contacts. In another case, the electrical connections 12 may be formed as plug contacts, solder pins and / or insulation displacement connections. These electrical connections 12 are preferably IEC or DIN standardized. In the FIGS. 7A and 7C the semiconductor chips 1 additionally on Stromleitschienen, which counteract a poor current conductivity of the respective doped material. These power rails can be configured star-shaped, round, square or adapted to the particular circumstances.
  • FIG. 8 are shown at the outset principally different constructed semiconductor chips 1.
  • a non-insulating substrate 17a is provided on a bottom surface having an n-type pad 19.
  • a p-junction 18 is provided on the opposite side of the underside of a p-junction 18 .
  • FIG. 8B both connection points 18, 19 reversed.
  • FIG. 8C an insulating substrate 17b is provided with connection points 18, 19 provided on an upper side.
  • an injection molding process serves to introduce epoxies between the individual layers of the terminal assembly, thereby achieving the electrical isolation of the individual layers.
  • the interconnection level 3 is separated from the heat dissipation level 4, whereby the interconnection and connection level are equipped with more functionality.
  • current conducting paths can still be arranged on the semiconductor chip 1 in order to counteract the poor conductivity of the doped base material.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
EP08854876.3A 2007-11-28 2008-11-21 Chipanordnung, anschlussanordnung, led sowie verfahren zur herstellung einer chipanordnung Not-in-force EP2225785B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007057242 2007-11-28
DE102008021618A DE102008021618A1 (de) 2007-11-28 2008-04-30 Chipanordnung, Anschlussanordnung, LED sowie Verfahren zur Herstellung einer Chipanordnung
PCT/DE2008/001931 WO2009067996A2 (de) 2007-11-28 2008-11-21 Chipanordnung, anschlussanordnung, led sowie verfahren zur herstellung einer chipanordnung

Publications (2)

Publication Number Publication Date
EP2225785A2 EP2225785A2 (de) 2010-09-08
EP2225785B1 true EP2225785B1 (de) 2017-03-15

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EP08854876.3A Not-in-force EP2225785B1 (de) 2007-11-28 2008-11-21 Chipanordnung, anschlussanordnung, led sowie verfahren zur herstellung einer chipanordnung

Country Status (8)

Country Link
US (1) US20100314635A1 (ko)
EP (1) EP2225785B1 (ko)
JP (1) JP2011505072A (ko)
KR (1) KR20100105632A (ko)
CN (1) CN101878544A (ko)
DE (1) DE102008021618A1 (ko)
TW (1) TWI484656B (ko)
WO (1) WO2009067996A2 (ko)

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US20100314635A1 (en) 2010-12-16
KR20100105632A (ko) 2010-09-29
EP2225785A2 (de) 2010-09-08
JP2011505072A (ja) 2011-02-17
WO2009067996A3 (de) 2009-10-08
WO2009067996A2 (de) 2009-06-04
DE102008021618A1 (de) 2009-06-04
TWI484656B (zh) 2015-05-11
TW200929627A (en) 2009-07-01
CN101878544A (zh) 2010-11-03

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