EP2139028A1 - Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film - Google Patents

Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film Download PDF

Info

Publication number
EP2139028A1
EP2139028A1 EP08739474A EP08739474A EP2139028A1 EP 2139028 A1 EP2139028 A1 EP 2139028A1 EP 08739474 A EP08739474 A EP 08739474A EP 08739474 A EP08739474 A EP 08739474A EP 2139028 A1 EP2139028 A1 EP 2139028A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
adhesive film
semiconductor wafer
dicing tape
elongation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08739474A
Other languages
German (de)
English (en)
French (fr)
Inventor
Yuuki Nakamura
Tsutomu Kitakatsu
Youji Katayama
Keiichi Hatakeyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of EP2139028A1 publication Critical patent/EP2139028A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/40—Removing material taking account of the properties of the material involved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0082—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material for supporting, holding, feeding, conveying or discharging work
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/16—Composite materials, e.g. fibre reinforced
    • B23K2103/166—Multilayered materials
    • B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer

Definitions

  • the present invention relates to a method for manufacturing a semiconductor chip, and to an adhesive film for a semiconductor and a composite sheet using the film.
  • silver paste is conventionally used, for the most part, as the die bonding material to bond the semiconductor chip with the supporting member.
  • methods that employ silver pastes are presenting problems including paste bleed-out and wire bonding troubles due to sloping of the semiconductor chip.
  • adhesive films adhesive films for semiconductors
  • Systems used to obtain semiconductor devices using adhesive films include short bar attachment systems and wafer back-side attachment systems.
  • short bars are cut out by cutting or punching from a reel-shaped adhesive film and the short bars of the adhesive film are bonded to a supporting member.
  • Individuated semiconductor chips are joined to the supporting member by a separate dicing step, via the adhesive film bonded to the supporting member.
  • a semiconductor device is then obtained, if necessary by a wire bond step, sealing step, or the like.
  • a special assembly apparatus is necessary to cut out the adhesive film into short bars and bond them to the supporting member, and therefore production cost has been higher than methods using silver paste.
  • a wafer back-side attachment system first an adhesive film and dicing tape are attached in that order to the back side of a semiconductor wafer.
  • the semiconductor wafer is diced for partitioning into a plurality of semiconductor chips, and the adhesive film is cut for each semiconductor chip.
  • the semiconductor chips are picked up together with the adhesive films laminated on their back sides, and the semiconductor chips are bonded to supporting members through the adhesive films.
  • a semiconductor device is then obtained by further steps such as heating, curing and wire bonding.
  • a wafer back-side attachment system does not require an assembly apparatus for individuation of the adhesive film, and a conventional assembly apparatus used for silver paste may be used either in its original form or with part of the apparatus modified by addition of a heating plate or the like.
  • this method has been of interest with the aim of helping to limit production cost.
  • Methods proposed for dicing semiconductor wafers include stealth dicing, in which a semiconductor wafer is irradiated with laser light to selectively create reformed sections inside the semiconductor wafer, and the semiconductor wafer is cut along the reformed sections (Patent documents 1 and 2).
  • stealth dicing in which a semiconductor wafer is irradiated with laser light to selectively create reformed sections inside the semiconductor wafer, and the semiconductor wafer is cut along the reformed sections.
  • dicing tape is stretched to apply stress to the semiconductor wafer, and the semiconductor wafer is partitioned into multiple semiconductor chips along the reformed sections.
  • Wafer back-side attachment systems require the adhesive film to be cut simultaneously during semiconductor wafer dicing.
  • the semiconductor wafer and adhesive film are simultaneously cut by ordinary dicing methods employing a diamond blade, cracking occurs on the side surfaces of the cut semiconductor chips (chip cracks), and the adhesive film becomes raised on the cut surfaces, producing numerous burrs.
  • chip cracks occurs on the side surfaces of the cut semiconductor chips
  • burrs The presence of such chip cracks and burrs tends to result in cracking of the semiconductor chips during their pickup, thus lowering the yield.
  • the stealth dicing method mentioned above can potentially inhibit the extent of chip cracks and burrs produced with dicing.
  • the invention relates to a method for manufacturing a semiconductor chip.
  • the manufacturing method of the invention comprises a step of preparing a laminated body having a semiconductor wafer, an adhesive film for a semiconductor and dicing tape laminated in that order, the adhesive film for a semiconductor having a tensile breaking elongation of less than 5%, the tensile breaking elongation being less than 110% of the elongation at maximum load, the semiconductor wafer being partitioned into multiple semiconductor chips, and notches being formed from the semiconductor wafer side so that at least a portion of the adhesive film for a semiconductor remains uncut in its thickness direction, and a step of stretching out the dicing tape in a direction so that the multiple semiconductor chips are separated apart, to separate the adhesive film for a semiconductor along the notches.
  • a laminated body is prepared with the adhesive film for a semiconductor connected instead of being completely cut. Stretching out of the dicing tape also causes the adhesive film for a semiconductor to be partitioned.
  • the adhesive film for a semiconductor having the aforementioned specified tensile breaking elongation is employed to allow semiconductor chips to be obtained from a semiconductor wafer at high yield while sufficiently inhibiting generation of chip cracks and burrs.
  • the method for manufacturing a semiconductor chip according to the invention may also comprise a step of preparing a laminated body having a semiconductor wafer, an adhesive film for a semiconductor and dicing tape laminated in that order, the adhesive film for a semiconductor having a tensile breaking elongation of less than 5% and the tensile breaking elongation being less than 110% of the elongation at maximum load, with reformed sections formed in the semiconductor wafer by laser working along lines for division of the semiconductor wafer into multiple semiconductor chips, and a step of stretching out the dicing tape in a direction so that the multiple semiconductor chips are separated apart, to partition the semiconductor wafer into multiple semiconductor chips while partitioning the adhesive film for a semiconductor along the reformed sections.
  • the semiconductor wafer is partitioned after forming reformed sections in the semiconductor wafer by laser working, and therefore generation of chip cracks and burrs is satisfactorily prevented compared to conventional methods that employ dicing blades or the like. Furthermore, since the method employs an adhesive film for a semiconductor having the aforementioned specified tensile characteristics, the adhesive film for a semiconductor is efficiently and reliably partitioned by stretching out of the dicing tape, allowing semiconductor chips to be obtained at high yield as a result.
  • the adhesive film for a semiconductor preferably comprises a thermoplastic resin, a thermosetting component and a filler, and has a filler content of less than 30 % by mass with respect to the mass of the adhesive film for a semiconductor. Reducing the filler content somewhat while imparting the specified tensile characteristic to the adhesive film for a semiconductor will inhibit reflow cracks after mounting.
  • the step of preparing the laminated body preferably includes a step of attaching the adhesive film for a semiconductor onto the semiconductor wafer at a temperature of not higher than 100°C. Attachment of the adhesive film for a semiconductor to the semiconductor wafer while maintaining a relatively low temperature of the adhesive film for a semiconductor will satisfactorily prevent warping of the semiconductor wafer and damage resulting from the thermal history of the dicing tape or backgrind tape.
  • the invention relates to an adhesive film for a semiconductor.
  • the adhesive film for a semiconductor according to the invention has a tensile breaking elongation of less than 5% and the tensile breaking elongation of less than 110% of the elongation at maximum load.
  • Such an adhesive film for a semiconductor according to the invention is preferably attachable to a semiconductor wafer at 100°C or below.
  • the adhesive film for a semiconductor according to the invention preferably comprises a thermoplastic resin, a thermosetting component and a filler, where a filler content is less than 30 % by mass with respect to the mass of the adhesive film for a semiconductor. Reducing the filler content somewhat while imparting the specified tensile characteristics to the adhesive film for a semiconductor will further inhibit reflow cracks.
  • the invention relates to a composite sheet comprising an adhesive film for a semiconductor according to the invention as described above, and dicing tape laminated on one side of the adhesive film for a semiconductor.
  • 1 Semiconductor wafer, 1a: reformed section, 2: adhesive film for a semiconductor, 3: dicing tape, 4: dicing blade, 5: division line, 7: wiring-attached base, 8: bonding wire, 9: sealing resin layer, 10, 10a, 10b: semiconductor chips, 20: laminated body, 40: notch, 100: semiconductor device.
  • Figs. 1 , 2 , 3 , 4 and 5 are end views showing a method for manufacturing a semiconductor chip according to a first embodiment.
  • the method for manufacturing a semiconductor chip according to this embodiment comprises a step of preparing a laminated body 20 obtained by laminating a semiconductor wafer 1, an adhesive film for a semiconductor 2 and dicing tape 3 in that order ( Fig. 1 ), a step of forming notches 40 in the laminated body 20 from one side of the semiconductor wafer 1 ( Figs. 2 and 3 ), a step of partitioning the adhesive film for a semiconductor 2 along the notches 40 ( Fig. 4 ), and a step of pickup of semiconductor chips 10 together with the adhesive film for a semiconductor 2 ( Fig. 5 ).
  • the laminated body 20 in Fig. 1 is prepared by a method in which an adhesive film for a semiconductor 2 and dicing tape 3 are attached in that order on the back side of a semiconductor wafer 1, or a composite sheet obtained by laminating the adhesive film for a semiconductor 2 and dicing tape 3 is attached to the back side of the semiconductor wafer 1 with the adhesive film for a semiconductor 2 facing the semiconductor wafer 1 side.
  • the semiconductor wafer 1 used is a wafer comprising single-crystal silicon, or polycrystalline silicon, a ceramic, or a compound semiconductor composed of gallium-arsenic.
  • the dicing tape 3 is not particularly restricted so long as it has a sufficient adhesive property to allow anchoring onto an anchoring ring, and can be stretched out so that the adhesive film for a semiconductor 2 is partitioned. Vinyl chloride-based tape, for example, may be used as the dicing tape.
  • the adhesive film for a semiconductor 2 will be described in detail below.
  • the temperature of the adhesive film for a semiconductor is preferably kept at 0-100°C. Attachment of the adhesive film for a semiconductor 2 at such a relatively low temperature will satisfactorily prevent warping of the semiconductor wafer 1 and damage resulting from the thermal history of the dicing tape or backgrind tape. From the same viewpoint, the temperature is more preferably 15°C-95°C and even more preferably 20°C-90°C.
  • a dicing blade 4 is used to form notches 40 in the laminated body 20 from the semiconductor wafer 1 side, in such a manner that the semiconductor wafer 1 is partitioned into multiple semiconductor chips 10 while leaving a portion uncut in the direction of thickness of the adhesive film for a semiconductor 2 ( Fig. 2 ). In other words, the semiconductor wafer 1 is completely cut while the adhesive film for a semiconductor 2 is half-cut along the lines on which the semiconductor wafer 1 is cut.
  • Fig. 3 is a magnified end view showing the area near a notch 40 formed in the laminated body 20.
  • "Half-cut" means that the thickness T1 of the adhesive film for a semiconductor 2 and the depth T2 to which the adhesive film for a semiconductor 2 is notched satisfy the relationship T2/T1 ⁇ 1.
  • T2/T1 is preferably 1/5-4/5, more preferably 1/4-3/4 and even more preferably 1/3-2/3.
  • a smaller T2 will tend to prevent generation of burrs when the adhesive film for a semiconductor 2 is partitioned along the notches 40, but will also tend to interfere with complete partitioning of the adhesive film for a semiconductor 2 even by stretching of the dicing tape 3 and increasing the thrusting height during pickup of the semiconductor chip 10.
  • T2 A larger T2 will tend to facilitate complete segmentation of the die bond film even with a low amount of stretching of the dicing tape (also referred to hereunder as "expanding volume"), and even with a low thrusting height during pickup of the semiconductor chip 10.
  • an excessively large T2 will tend to reduce the effect against burrs and lower the yield for production of semiconductor devices.
  • the dicing tape 3 is stretched out in a direction such that the multiple semiconductor chips 10 are separated apart, i.e. in the direction along the main side of the dicing tape 3 (the direction of the arrow in Fig. 2 ), to partition the adhesive film for a semiconductor 2 ( Fig. 4 ).
  • the semiconductor chips 10 and the adhesive film-attached semiconductor chips having the adhesive film for a semiconductor 2 attached thereover become arranged on the dicing tape 3.
  • the expanding volume is the difference between the width (maximum width) of the dicing tape 3 after stretching R 1 and the initial width (maximum width) of the dicing tape 3 R 0 (see Fig. 2 ).
  • the expanding volume is preferably 2 mm-10 mm, more preferably 2 mm-8 mm and even more preferably 2 mm-7 mm. Since the notches formed in the adhesive film for a semiconductor 2 as in this embodiment serve as starting points for cutting, the expanding volume may be reduced compared to a situation where the adhesive film for a semiconductor 2 is completely uncut, as in the second embodiment described hereunder.
  • the semiconductor chips 10 are picked up together with the adhesive film for a semiconductor 2 attached onto the back side thereof ( Fig. 5 ).
  • the dicing tape 3 may be pushed up to a prescribed height from the side opposite the semiconductor chips 10, at the locations where the semiconductor chips 10 are to be picked up.
  • the picked-up semiconductor chips 10 are mounted onto supporting members or the like using the adhesive film for a semiconductor 2 attached on their back sides as die bonding materials. The steps after pickup will be described below.
  • the adhesive film for a semiconductor 2 has, as a feature, a relatively short tensile breaking elongation.
  • the adhesive film for a semiconductor 2 does not yield in a tensile test, or breaks immediately after yielding at maximum load. With such tensile characteristics, the adhesive film for a semiconductor 2 will be resistant to raising of the ruptured surface when rupture occurs due to tensile stress, so that generation of burrs can be satisfactorily prevented.
  • the tensile breaking elongation of the adhesive film for a semiconductor 2 is preferably less than 5%.
  • the tensile breaking elongation of the adhesive film for a semiconductor 2 is preferably less than 110% with respect to the elongation at maximum load in a tensile test.
  • the adhesive film for a semiconductor 2 with such tensile characteristics can be efficiently and reliably separated with low expanding volume.
  • the tensile breaking elongation is more preferably less than 4% and even more preferably less than 3.5%.
  • the ratio of the tensile breaking elongation to the elongation under maximum load is more preferably less than 108% and even more preferably less than 105%. This ratio is a minimum of 100%, when the tensile breaking elongation and the elongation under maximum load are equal.
  • the maximum stress, maximum load elongation and tensile breaking elongation are determined by using a test strip with a width of 5 mm, a length of 50 mm and a thickness of 25 ⁇ m, cut out from the adhesive film for a semiconductor in the B-stage state, for a tensile test under the following conditions, in an environment at 25°C.
  • Tensile tester 100N autograph "AGS-100NH” by Shimadzu Length between chucks (at start of test): 30 mm Pull rate: 5 mm/min
  • the maximum load, length between chucks at maximum load and length between chucks at the time of rupture are read from a stress-strain curve obtained by the tensile test, and these values and the measured value for the cross-sectional area of the sample are used to calculate the maximum stress, maximum load elongation and tensile breaking elongation by the following formula.
  • Maximum stress Pa maximum load N / cross - sectional area of sample m 2
  • Elongation at maximum load % length between chucks at maximum load mm ⁇ 30 / 30 ⁇ 100
  • Tensile breaking elongation % length between chucks at the time of rupture mm ⁇ 30 / 30 ⁇ 100
  • the tensile test is preferably carried out under the conditions described above, but the conditions may be altered to other conditions that give substantially the same test results.
  • the adhesive film for a semiconductor 2 preferably comprises a thermoplastic resin, a thermosetting component and a filler.
  • the thermoplastic resin in the adhesive films for a semiconductor preferably has a glass transition temperature (Tg) of not higher than 60°C.
  • Tg glass transition temperature
  • a thermoplastic resin with heat resistance of 300°C or above is also preferred.
  • preferred thermoplastic resins there may be mentioned polyimide resins, polyamideimide resins, phenoxy resins, acrylic resins, polyamide resins and urethane resins. These may be used alone or in combinations of two or more. Polyimide resins are particularly preferred among those mentioned above. By using a polyimide resin it is possible to easily impart the tensile characteristic described above to the adhesive film for a semiconductor 2 while maintaining a reasonably small filler content.
  • thermosetting component is a component that can be hardened when it undergoes crosslinking under heating, and for example, it may be composed of a thermosetting resin and its curing agent.
  • the thermosetting resin may be any known one and is not particularly restricted, but preferred are epoxy resins and imide compounds with at least two thermosetting imide groups in the molecule, from the viewpoint of convenience as a semiconductor peripheral material (availability of high purity product, variety and easily controllable reactivity).
  • An epoxy resin will normally be used together with an epoxy resin curing agent.
  • An epoxy resin is preferably a compound having two or more epoxy groups. From the viewpoint of curability and cured properties, it is preferably a phenol glycidyl ether-type epoxy resin.
  • phenol glycidyl ether-type epoxy resins there may be mentioned condensation products of bisphenol A, bisphenol AD, bisphenol S, bisphenol F or halogenated bisphenol A with epichlorohydrin, as well as phenol-novolac resin glycidyl ether, cresol-novolac resin glycidyl ether and bisphenol A-novolac resin glycidyl ether.
  • Novolac-type epoxy resins are preferred among those mentioned above because they have high cured crosslink density and can increase the adhesive strength of the hot film. They may be used alone or in combinations of two or more.
  • epoxy resin curing agents there may be mentioned phenol-based compounds, aliphatic amines, alicyclic amines, aromatic polyamines, polyamides, aliphatic acid anhydrides, alicyclic acid anhydrides, aromatic acid anhydrides, dicyandiamides, organic acid dihydrazides, boron trifluoride amine complexes, imidazoles and tertiary amines.
  • Phenol-based compounds are preferred among these, with phenol-based compounds having two or more phenolic hydroxyl groups being especially preferred. More specifically, naphthol-novolac resins and trisphenol-novolac resins are preferred.
  • Using these phenol-based compounds as epoxy resin curing agents can effectively reduce contamination of the chip surfaces and devices during heating for package assembly, as well as generation of outgas that is a cause of odor.
  • the filler content may also be adjusted to control the tensile characteristic of the adhesive film for a semiconductor.
  • a high filler content will tend to lower the tensile breaking elongation, while also tending to reduce the ratio of the tensile breaking elongation to the elongation at maximum load.
  • Appropriate use of a filler can produce effects such as improved handleability, increased thermal conductivity, modified melt viscosity and thixotropic properties.
  • the filler is preferably an inorganic filler.
  • preferred inorganic fillers contain one or more inorganic materials selected from the group consisting of aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, aluminum nitride, aluminum borate whiskers, boron nitride, crystalline silica, amorphous silica and antimony oxide.
  • Alumina, aluminum nitride, boron nitride, crystalline silica and amorphous silica are preferred for increased thermal conductivity.
  • aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, crystalline silica and amorphous silica are preferred.
  • Alumina, silica, aluminum hydroxide and antimony oxide are preferred for increased humidity resistance.
  • Different types of fillers may also be used in combination.
  • a high filler content will tend to lower the tensile breaking elongation while raising the elastic modulus and increasing the breaking strength, but will also tend to lower the adhesion, resulting in reduced reflow crack resistance. In particular, it will be more prone to tearing during reflow between semiconductor chips and an adherend with irregularities formed in the surface, such as an organic board.
  • a high filler content will also tend to lower the resistance in reliability testing under high-temperature, high-humidity environments, such as HAST testing.
  • increasing the filler content will tend to increase the temperature at which the adhesive film for a semiconductor can attach to semiconductor wafers.
  • the filler content is preferably less than 30 % by mass and more preferably less than 25 % by mass with respect to the total mass of the adhesive film for a semiconductor. It is more preferably less than 20 % by mass.
  • the adhesive film for a semiconductor 2 is preferably attachable to a semiconductor wafer as the adherend, at 100°C or below.
  • the adhesive film for a semiconductor is considered to be attachable to a semiconductor wafer if the peel strength at the interface between the adhesive film for a semiconductor and the semiconductor wafer is at least 20 N/m when the adhesive film for a semiconductor kept at the prescribed temperature is attached to the semiconductor wafer.
  • the adhesive film for a semiconductor may be attached to the semiconductor wafer, for example, using a hot roll laminator set to a temperature of 100°C or below.
  • the peel strength is measured in an atmosphere at 25°C, with a pull angle of 90° and a pull speed of 50 mm/min.
  • the adhesive film for a semiconductor 2 is preferably attachable to the semiconductor wafer at a temperature of not higher than 95°C and more preferably not higher than 90°C.
  • the adhesive film for a semiconductor 2 preferably has the heat resistance and humidity resistance required for mounting of a semiconductor chip onto a semiconductor chip mounting supporting member. It should therefore pass a reflow crack resistance test.
  • the reflow crack resistance of the adhesive film for a semiconductor can be evaluated based on the adhesive strength.
  • the peel strength is preferably at least 1.0 kg/cm initially, and at least 0.5 kg/cm after standing for 48 hours in an atmosphere at 85°C/85%, when the adhesive film for a semiconductor is attached to a semiconductor wafer with a 4 ⁇ 2 mm square bonding area.
  • the initial peel strength is more preferably at least 1.3 kg/cm and even more preferably 1.5 kg/cm.
  • the peel strength after standing for 48 hours in an atmosphere at 85°C/85% is more preferably at least 0.7 kg/cm and even more preferably at least 0.8 kg/cm.
  • the adhesive film for a semiconductor 2 may be obtained by a method in which, for example, a coating solution comprising a thermoplastic resin, a thermosetting component, a filler and an organic solvent which dissolves or disperses the foregoing is coated onto a base film, and the organic solvent is removed from the coating solution on the base film by heating.
  • the organic solvent is not particularly restricted so long as it allows uniform dissolution and dispersion of the materials, and as examples there may be mentioned dimethylformamide, dimethylacetamide, N-methylpyrrolidone, dimethyl sulfoxide, diethyleneglycol dimethyl ether, toluene, benzene, xylene, methyl ethyl ketone, tetrahydrofuran, ethylcellosolve, ethylcellosolve acetate, butylcellosolve, dioxane, cyclohexanone and ethyl acetate. These may be used alone or in combinations of two or more.
  • the base film is not particularly restricted so long as it can withstand the heating used for removal of the organic solvent.
  • base films there may be mentioned polyester films, polypropylene films, polyethylene terephthalate films, polyimide films, polyetherimide films, polyether naphthalate films and methylpentene films.
  • a multilayer film comprising two or more of these films may also be used as the base film.
  • the surface of the base film may be treated with a release agent which is silicone-based, silica-based or the like. After removal of the organic solvent, the base film may be used by itself as the support of the adhesive film for a semiconductor without removal.
  • the adhesive film for a semiconductor may be stored and used as a composite sheet attached to dicing tape. Using such a composite sheet can simplify the semiconductor device production process.
  • Figs. 6 , 7 , 8 and 9 are end views showing a method for manufacturing a semiconductor chip according to a second embodiment.
  • the method according to this embodiment comprises a step of preparing a laminated body 20 obtained by laminating a semiconductor wafer 1, an adhesive film for a semiconductor 2 and dicing tape 3 in that order ( Figs. 6-8 ), a step of stretching out the dicing tape 3 in a direction such that the plurality of semiconductor chips 10 separate from each other, to partition the adhesive film for a semiconductor 2 as the semiconductor wafer 1 is partitioned into a plurality of semiconductor chips 10 ( Fig. 9 ), and a step of pickup of the semiconductor chips 10 together with the adhesive film for a semiconductor 2.
  • the step of preparing the laminated body 20 comprises a step of laser working to form reformed sections 1a inside the semiconductor wafer 1 along lines 50 that demarcate the semiconductor wafer 1 into multiple semiconductor chips 10 (hereinafter referred to as "division lines") ( Fig. 6 ), a step of attaching an adhesive film for a semiconductor 2 onto the semiconductor wafer 1 in which the reformed sections 1a have been formed ( Fig. 7 ), and a step of attaching dicing tape 3 onto the adhesive film for a semiconductor 2 ( Fig. 8 ).
  • a laser 90 is irradiated along division lines 50 ( Fig. 6(b) ).
  • the laser working may be carried out under conditions commonly employed for known "stealth dicing" methods.
  • the laser working forms reformed sections 1a inside the semiconductor wafer 1.
  • the adhesive film for a semiconductor 2 and dicing tape 3 are attached in that order onto the semiconductor wafer 1 as shown in Figs. 7 and 8 , to obtain a laminated body 20.
  • the steps for obtaining the laminated body 20 are not limited to the order of this embodiment.
  • the reformed sections may be formed by laser working after the adhesive film for a semiconductor has been attached onto the semiconductor wafer.
  • the dicing tape 3 is stretched out in a direction such that the plurality of semiconductor chips 10 separate apart (direction of the arrow in Fig. 8(b) ), to partition the semiconductor wafer 1 into multiple semiconductor chips 10 while also partitioning the adhesive film for a semiconductor 2 along the reformed sections 1a ( Fig. 9 ).
  • the semiconductor wafer 1 and adhesive film for a semiconductor 2 are partitioned by stretching the dicing tape, without cutting with a dicing blade.
  • This method does not require simultaneous cutting of the semiconductor wafer 1 and adhesive film for a semiconductor 2 with a dicing blade and can therefore increase the speed of individuation of the semiconductor wafer while inhibiting generation of burrs.
  • the expanding volume of the dicing tape 3 is preferably 5-30 mm, more preferably 10-30 mm and even more preferably 10-20 mm. If the expanding volume is less than 5 mm it will tend to be difficult to completely separate the semiconductor wafer 1 and adhesive film for a semiconductor 2, while if it is greater than 30 mm, tearing will tend to occur at sections other than the sections along the division lines.
  • the speed at which the dicing tape 3 is stretched out is preferably 10-1000 mm/sec, more preferably 10-100 mm/sec and even more preferably 10-50 mm/sec. If the expanding speed is less than 10 mm/sec it will tend to be difficult to completely separate the semiconductor wafer 1 and adhesive film for a semiconductor 2, while if it is greater than 1000 mm/sec, tearing will tend to occur at sections other than the sections along the division lines.
  • the semiconductor chips 10 are bonded onto supporting members via the adhesive film for a semiconductor 2 attached on their back sides.
  • the supporting members there may be mentioned lead frames such as 42 alloy lead frames and copper lead frames, boards obtained by impregnating a resin film, nonwoven glass fabric or glass woven fabric formed from an epoxy resin, polyimide-based resin, maleimide-based resin or the like with a thermosetting resin such as an epoxy resin, polyimide-based resin or maleimide-based resin and curing the resin, as well as glass boards and ceramic boards of alumina and the like.
  • the semiconductor chips may also be bonded together via the adhesive film for a semiconductor.
  • Fig. 10 is a cross-sectional view showing an embodiment of a semiconductor device obtained by such a method.
  • the semiconductor device 100 shown in Fig. 10 comprises a wiring-attached base (supporting member) 7, a semiconductor chip 10a bonded to the wiring-attached base 7 via the adhesive film for a semiconductor 2, and a semiconductor chip 10b bonded to the semiconductor chip 10a via the adhesive film for a semiconductor 2.
  • the semiconductor chips 10a and 10b are connected to the wiring of the wiring-attached base 7 by bonding wire 8.
  • the semiconductor chips 10a and 10b are sealed by a sealing resin layer 9 in which they are embedded.
  • Bonding between the semiconductor chip and supporting member and between the semiconductor chips is accomplished, for example, by heating at 60-300°C for 0.1-300 seconds with the adhesive film for a semiconductor sandwiched between the semiconductor chip and supporting member or between the semiconductor chips.
  • the bonded semiconductor chips are preferably heated to promote adhesion and curing of the adhesive film for a semiconductor onto the adherend, for increased joint strength.
  • the heating may be appropriately adjusted according to the composition of the adhesive film, and it will normally be 60-220°C for 0.1-600 minutes.
  • resin sealing is carried out, the heating in the curing step for the sealing resin may be utilized.
  • NMP solution of a polyimide resin was obtained in the same manner as Example 1, except that 1,3-bis(3-aminopropyl)tetramethyldisiloxane (0.06 mol) and 4,9-dioxadecane-1,12-diamine (0.04 mol) were used as diamine components.
  • the obtained NMP solution of the polyimide resin was used to form an adhesive film in the same manner as Example 1.
  • An adhesive film was formed in the same manner as Example 1, except that the boron nitride filler was used at 57 wt%.
  • DF-402 as the adhesive film for Comparative Example 1
  • DF-470 as the adhesive film for Comparative Example 2
  • DF-443 as the adhesive film for Comparative Example 3 (all die bond films by Hitachi Chemical Co., Ltd.).
  • the NMP solution of the polyimide resin obtained by removal of the water was used to form an adhesive film.
  • An adhesive film was formed in the same manner as Example 1, except that the obtained solution was used and the boron nitride filler content was 25 wt% with respect to the total solid weight.
  • An adhesive film was formed in the same manner as Comparative Example 4, except that the boron nitride filler was used at 47 wt%.
  • a test strip (width: 5 mm, length: 50 mm) cut out from the adhesive film in the B-stage state was used for a tensile test.
  • the maximum stress, maximum load elongation and tensile breaking elongation were determined from the obtained stress-strain curve, based on the following formulas.
  • the tensile test was conducted using a tensile tester (100N autograph, AGS-100NH by Shimadzu) under conditions with an atmosphere at 25°C, a length between chucks of 30 mm at the start of the test and a pull rate of 5 mm/min.
  • Fig. 11 is a view showing the stress-strain curve for the adhesive film of Example 1
  • Fig. 12 is the same for Example 2
  • Fig. 13 is the same for Comparative Example 1.
  • elongation (mm) length between chucks - 30.
  • the maximum load elongation is calculated from the elongation corresponding to the maximum load Pmax
  • the tensile breaking elongation is calculated from the elongation E at the moment at which the load has fallen to 0, after the test piece has ruptured.
  • a peel test was conducted in which a hot roll laminator (0.3 m/min, 0.3 MPa) heated to a prescribed temperature was used to attach an adhesive film with a width of 10 mm to a semiconductor wafer and then the adhesive film was pulled off in a 25°C atmosphere at a pull angle of 90° and a pull speed of 50 mm/min, to determine the peel strength.
  • the peel test was conducted using a UTM-4-100 TENSILON by Toyo Baldwin. The preset temperature of the hot roll laminator was raised from 40°C, 10°C at a time, and the lowest temperature among the hot roll laminator temperatures at which peel strength of 20 N/m or greater was obtained was recorded as the wafer attachment temperature.
  • a silicon wafer with a thickness of 400 ⁇ m was half-cut from the surface side to a depth of 250 ⁇ m and split by force applied in the back-side direction, to prepare 4 mm ⁇ 2 mm silicon chips having 150 ⁇ m-wide raised edges on the perimeter.
  • An adhesive film cut out to a size of 4 mm ⁇ 2 mm was sandwiched between the silicon chips and 42 alloy lead frame.
  • a load of 200 gf was applied to the entire section and contact bonded therewith at 160°C for 5 seconds, and then heated at 180°C for 60 minutes for postcuring of the adhesive film.
  • the chip pull-off strength during heating at 260°C for 20 seconds was then measured using the measuring apparatus 15 shown in Fig. 14 with a modified push-pull gauge.
  • the measuring apparatus 15 comprised a heating plate 14, a die pad 13 mounted on the heating plate 14, and a push-pull gauge 12.
  • the sample was placed on the die pad 13 of the measuring apparatus 15, and the push-pull gauge 12 was hooked onto the raised edge of the silicon chip to measure the chip peel strength.
  • the peel strength of each sample was measured initially, and after high-temperature, high-humidity treatment for 48 hours in an environment of 85°C, 85% RH. This measurement allows the surface adhesive strength of the adhesive film to be measured. A higher numerical value corresponds to greater resistance to reflow crack formation.
  • An adhesive film-attached silicon chip comprising a silicon chip cut to a 5 mm square and an adhesive film attached thereto was bonded to a circuit board having wiring formed on the surface of a polyimide film (25 ⁇ m thickness) as the base. A separate 5 mm-square adhesive film-attached silicon chip was then bonded to this silicon chip.
  • Treatment of ten obtained samples was carried out twice, the treatment comprising passing each sample through an IR reflow furnace set so that the surface temperature reached 260°C and the temperature was held for 20 seconds, and then allowing it to stand at room temperature (25°C) for cooling. Cracks in the treated samples were observed visually and with an acoustic microscope, to confirm the presence of any board/chip or chip/chip cracks. The reflow crack resistance was evaluated on the following scale, based on the observation results. A: No cracks found in any of the samples. C: Cracks occurred in one or more samples.
  • a hot roll laminator (DM-300H by JCM, 0.3 m/min, 0.3 MPa) was used to attach each adhesive film to a 50 ⁇ m-thick semiconductor wafer at the wafer attachment temperature listed in Table 1.
  • dicing tape was laminated onto the adhesive film under conditions with a hot plate temperature of 80°C, to prepare a dicing sample.
  • a stainless steel ring was attached around the perimeter of the dicing tape, and a DFD-6361 by DISCO was used to cut the dicing sample.
  • the cutting was performed with a single-cut system in which working is completed with a single blade, under conditions with an NBC-ZH104F-SE 27HDBB blade, a blade rotation rate of 45,000 rpm and a cutting speed of 50 mm/s.
  • the blade height (cutting depth) during cutting was 80 ⁇ m, as a height allowing complete cutting of the adhesive film.
  • the dicing tape was stretched out with an expanding apparatus, with the ring in an anchored state.
  • the expanding speed was 10 mm/s and the expanding volume was 3 mm.
  • the semiconductor wafer (50 ⁇ m thickness) was subjected to laser irradiation to form reformed sections therein along the lines demarcating the semiconductor chips.
  • Adhesive film and dicing tape were then attached in that order, by the same procedure as for full-cutting, and a stainless steel ring was attached around the outer periphery of the dicing tape.
  • the dicing tape was stretched out with an expanding apparatus, with the ring in an anchored state.
  • the expanding speed was 30 mm/s and the expanding volume was 15 mm.
  • the adhesive films of the examples which had tensile breaking elongations of less than 5% and tensile breaking elongation/elongation at maximum load ratios of less than 110%, exhibited satisfactory tear resistance with both half-cutting and laser dicing, while the generation of chip cracks and burrs was also sufficiently minimized.
  • the adhesive films of Examples 1 and 2 which had filler contents of less than 30 % by mass were attachable to semiconductor wafers at 100°C or below, and were highly superior in terms of reflow crack resistance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)
EP08739474A 2007-04-05 2008-03-31 Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film Withdrawn EP2139028A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007099344 2007-04-05
JP2007204338 2007-08-06
PCT/JP2008/056361 WO2008126718A1 (ja) 2007-04-05 2008-03-31 半導体チップの製造方法、並びに半導体用接着フィルム及びこれを用いた複合シート

Publications (1)

Publication Number Publication Date
EP2139028A1 true EP2139028A1 (en) 2009-12-30

Family

ID=39863823

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08739474A Withdrawn EP2139028A1 (en) 2007-04-05 2008-03-31 Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film

Country Status (7)

Country Link
US (2) US8232185B2 (ko)
EP (1) EP2139028A1 (ko)
JP (1) JP5045745B2 (ko)
KR (1) KR101162819B1 (ko)
CN (1) CN101647096B (ko)
TW (1) TWI419215B (ko)
WO (1) WO2008126718A1 (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY151354A (en) * 2007-10-09 2014-05-15 Hitachi Chemical Co Ltd Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device
US8198176B2 (en) * 2007-10-09 2012-06-12 Hitachi Chemical Company, Ltd. Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device
JP2013520009A (ja) * 2010-02-12 2013-05-30 ダウ コーニング コーポレーション 半導体加工のための一時的ウェハー接着方法
JP5554118B2 (ja) * 2010-03-31 2014-07-23 古河電気工業株式会社 ウエハ加工用テープ
JP2012069919A (ja) * 2010-08-25 2012-04-05 Toshiba Corp 半導体装置の製造方法
JP2012195388A (ja) * 2011-03-15 2012-10-11 Toshiba Corp 半導体装置の製造方法及び半導体装置
US9559004B2 (en) 2011-05-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of singulating thin semiconductor wafer on carrier along modified region within non-active region formed by irradiating energy
JP2013008915A (ja) * 2011-06-27 2013-01-10 Toshiba Corp 基板加工方法及び基板加工装置
CN103013365A (zh) * 2011-09-23 2013-04-03 古河电气工业株式会社 晶片加工用带
CN103178007A (zh) * 2011-12-20 2013-06-26 杭州士兰集成电路有限公司 划片方法、芯片制作方法及凸点玻璃封装二极管
US8936969B2 (en) 2012-03-21 2015-01-20 Stats Chippac, Ltd. Semiconductor device and method of singulating semiconductor wafer along modified region within non-active region formed by irradiating energy through mounting tape
JP6028460B2 (ja) * 2012-08-24 2016-11-16 日立化成株式会社 半導体装置の製造方法及び半導体装置
CN104647615A (zh) * 2013-11-15 2015-05-27 台湾暹劲股份有限公司 晶圆切割装置及其切割方法
JP6310748B2 (ja) * 2014-03-31 2018-04-11 日東電工株式会社 ダイボンドフィルム、ダイシングシート付きダイボンドフィルム、半導体装置、及び、半導体装置の製造方法
WO2016080570A1 (ko) * 2014-11-20 2016-05-26 주식회사 이녹스 유기전자장치용 봉지재 및 이를 포함하는 발광장치
JP7041476B2 (ja) * 2017-07-04 2022-03-24 日東電工株式会社 ダイシングテープおよびダイシングダイボンドフィルム
CN107353841A (zh) * 2017-08-14 2017-11-17 东莞市哲华电子有限公司 一种Mylar片的低成本生产工艺
JP6977588B2 (ja) * 2018-01-30 2021-12-08 昭和電工マテリアルズ株式会社 半導体装置の製造方法及び接着フィルム
JP7019254B2 (ja) * 2018-04-10 2022-02-15 株式会社ディスコ 被加工物の切削方法
JP7305268B2 (ja) * 2019-08-07 2023-07-10 株式会社ディスコ ウェーハの加工方法
JP7471880B2 (ja) 2020-03-18 2024-04-22 リンテック株式会社 フィルム状接着剤及びダイシングダイボンディングシート
JP7471879B2 (ja) 2020-03-18 2024-04-22 リンテック株式会社 フィルム状接着剤及びダイシングダイボンディングシート
CN113299594B (zh) * 2021-05-25 2022-12-30 江西信芯半导体有限公司 Tvs芯片贴蓝膜后加工方法
CN116062536B (zh) * 2023-02-07 2024-08-02 珠海芯烨电子科技有限公司 双面胶贴装组件、设备及方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69914418T2 (de) * 1998-08-10 2004-12-02 Lintec Corp. Dicing tape und Verfahren zum Zerteilen einer Halbleiterscheibe
JP3408805B2 (ja) 2000-09-13 2003-05-19 浜松ホトニクス株式会社 切断起点領域形成方法及び加工対象物切断方法
JP2003257896A (ja) * 2002-02-28 2003-09-12 Disco Abrasive Syst Ltd 半導体ウェーハの分割方法
JP4358502B2 (ja) 2002-03-12 2009-11-04 浜松ホトニクス株式会社 半導体基板の切断方法
JP4107417B2 (ja) * 2002-10-15 2008-06-25 日東電工株式会社 チップ状ワークの固定方法
CN101392159B (zh) * 2003-06-06 2012-10-03 日立化成工业株式会社 粘合片、与切割胶带一体化的粘合片以及半导体的制造方法
WO2004109786A1 (ja) 2003-06-06 2004-12-16 Hitachi Chemical Co., Ltd. 接着シート、ダイシングテープ一体型接着シート、及び半導体装置の製造方法
JP2006203133A (ja) * 2005-01-24 2006-08-03 Lintec Corp チップ体の製造方法、デバイスの製造方法およびチップ体固着用粘接着シート
KR100673685B1 (ko) 2005-04-29 2007-01-24 엘에스전선 주식회사 반도체용 접착 필름
JP4979063B2 (ja) 2006-06-15 2012-07-18 日東電工株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP5045745B2 (ja) 2012-10-10
TWI419215B (zh) 2013-12-11
TW200903609A (en) 2009-01-16
US20100120229A1 (en) 2010-05-13
KR20090126249A (ko) 2009-12-08
CN101647096A (zh) 2010-02-10
KR101162819B1 (ko) 2012-07-05
WO2008126718A1 (ja) 2008-10-23
US8232185B2 (en) 2012-07-31
JPWO2008126718A1 (ja) 2010-07-22
CN101647096B (zh) 2012-01-04
US20120244347A1 (en) 2012-09-27

Similar Documents

Publication Publication Date Title
US8232185B2 (en) Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film
EP2200074A1 (en) Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device
US8071465B2 (en) Method for producing semiconductor chip with adhesive film, adhesive film for semiconductor used in the method, and method for producing semiconductor device
US8404564B2 (en) Adhesive film for semiconductor, composite sheet, and method for producing semiconductor chip using them
JP5206769B2 (ja) 接着シート
JP2005019962A (ja) 接着シート
TWI733931B (zh) 片、膠帶及半導體裝置的製造方法
JP2010001453A (ja) 接着フィルム、接着シート、半導体装置及び半導体装置の製造方法
WO2022054718A1 (ja) フィルム状接着剤、接着シート、並びに半導体装置及びその製造方法
WO2022186285A1 (ja) フィルム状接着剤、ダイシング・ダイボンディング一体型フィルム、並びに半導体装置及びその製造方法
WO2023157846A1 (ja) フィルム状接着剤及びその製造方法、ダイシング・ダイボンディング一体型フィルム、並びに半導体装置及びその製造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20091030

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20130129