EP2118927A2 - Procédé pour appliquer une structure sur un élément à semi-conducteurs - Google Patents

Procédé pour appliquer une structure sur un élément à semi-conducteurs

Info

Publication number
EP2118927A2
EP2118927A2 EP07856974A EP07856974A EP2118927A2 EP 2118927 A2 EP2118927 A2 EP 2118927A2 EP 07856974 A EP07856974 A EP 07856974A EP 07856974 A EP07856974 A EP 07856974A EP 2118927 A2 EP2118927 A2 EP 2118927A2
Authority
EP
European Patent Office
Prior art keywords
film
structural material
masking layer
semiconductor device
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07856974A
Other languages
German (de)
English (en)
Inventor
Oliver Schultz-Wittmann
Filip Granek
Andreas Grohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP2118927A2 publication Critical patent/EP2118927A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the invention relates to a method for applying a structure from a structural material to a semiconductor component according to claim 1, and to a semiconductor layer structure according to claim 15.
  • Methods according to the preamble of claim 1 are typically used in semiconductor technology to apply thin metallization structures to a semiconductor device.
  • a metal structure to a silicon wafer in which a photosensitive coating is first applied to the silicon wafer.
  • the photosensitive resist is then exposed through an exposure mask so that the areas of the photosensitive resist are exposed to the silicon wafer, which is later to have metal on the surface.
  • the paint is developed so that the exposed areas of the paint are removed.
  • a metal film is now applied over the entire surface so that the metal film rests on the remaining lacquer on the one hand and the metal film on the silicon wafer on the other hand in the areas in which the lacquer was removed again.
  • the remaining paint is removed by means of solvents, so that in this step, the metal film in the areas where it rests on the paint, is removed with.
  • a predetermined metal structure remains on the silicon wafer.
  • the method described above is also known as the "lift-off method". It is essential in this process that the solvent must pass through the metal film to the paint lying below the metal film in order to detach it. For this, either long process times for the detachment process are necessary, so that the solvent can penetrate through small pores through the metal film or laterally detach the paint in some areas, so that the detachment process eventually continues on the entire paint-covered areas.
  • the invention is therefore based on the object to improve the known method for applying a predetermined structure of a structural material to a semiconductor device, so that in particular the process times can be reduced and also costs are saved. Furthermore, the method according to the invention is intended to impose a lower requirement on the solvent to be used for detaching the paint and to the means from which the masking layer is formed, so that costs can be saved on the one hand and a reduction of the environmental impact by the process waste products on the other hand is.
  • inventive method according to claim 1, and by a semiconductor layer structure according to claim 15.
  • Advantageous embodiments of the method can be found in claims 2 to 14.
  • the inventive method is thus suitable for applying a structure of a structural material to a semiconductor device. This includes the previously described application of a metal structure to a semiconductor component, however, any other structures of any further structural materials can be applied to the semiconductor component by means of the method according to the invention.
  • a surface of the semiconductor component is partially covered by means of a masking layer, so that the areas are left out at which the structural material is to be on the surface of the semiconductor component after completion of the method.
  • a film of the structural material is applied so that the structural material covers the masking layer on the one hand and covers the surface of the semiconductor component in the areas recessed by the masking layer on the other hand.
  • a "lift-off” is performed, that is, the masking layer is peeled off, so that the structure material on the masking layer is also peeled off, as a result of which structural material remains in the predetermined recessed areas of the masking layer on the surface of the semiconductor device.
  • Step B2 of the film of structural material is partially removed.
  • openings are formed in the film of structural material prior to peeling the masking layer.
  • the solvent, which in step C removes the masking layer it is possible for the solvent, which in step C removes the masking layer, to pass through the film of structural material through the openings produced in method step B2 to the masking layer, so that the detachment process is initiated.
  • step C a significant acceleration of the process step C can be achieved, since by the achieved in step B2 openings immediately the detachment process is initiated. Likewise, it is possible to dispense with expensive and cost-intensive methods which-as described in the introductory part-modify the masking layer in such a way that no closed metal film is formed.
  • the structural material is partially removed in the areas in which the film has been applied to the masking layer.
  • the solvent can pass directly through the resulting free areas to the masking layer and initiate the detachment process.
  • the film is perforated from structural material, that is perforated at a plurality of approximately regularly arranged perforation points. It is particularly advantageous if the perforation is selected such that the individual perforations are arranged such that a predetermined
  • the perforations are spaced apart by a maximum of 5000 ⁇ m, in particular by at most 1000 ⁇ m, most particularly by at most 500 ⁇ m.
  • the film of structural material is at least perforated in step B2 along at least one predetermined line.
  • the lines are advantageously set to follow the recessed areas, i. have approximately the shape and the course of the edges of the recessed areas.
  • At least two sides of the predetermined structure is given a line as described above, along which the film of structural material is perforated, or is completely removed.
  • a complete removal can e.g. by means of a pulsed
  • the predetermined line to the predetermined structure ie to the edges of the recessed areas on a substantially constant distance.
  • the structural material remains on the surface of the semiconductor device. At the edges of the recessed areas, the film of structural material thus tears off when the masking layer is removed, because, on the one hand, structural material remains in the recessed areas on the surface of the semiconductor component, and on the other hand
  • Structure material which is located on the masking layer, with detached.
  • the predetermined lines lie approximately at the edges of the recessed areas, i. the distance of the predetermined line to the edges of the recessed areas is approximately zero.
  • the force acting on the film at the edges of the recessed areas also depends on the size of the means of the The larger the released area, the greater the force acting on the film at the edges of the recessed areas. At small distances of the predetermined line to the edges of the recessed areas, it is possible that the film is not torn off due to low acting forces and thus a portion of the film of structural material outside the recessed areas is not peeled off.
  • the distance is in the range 10 microns to 20 microns, so that even with alignment inaccuracies no structural material is removed in the recessed areas.
  • the detachment process in method step C can be accelerated once more by virtue of the predetermined lines being at a greater distance, i.e. a greater distance. have at least a predetermined distance to the edges of the recessed areas, since in this case the detachment process is initiated starting from the predetermined lines both in the direction of the edges of the recessed areas, as well as in the opposite direction.
  • a further advantage of such a predetermined minimum distance is that this results in sufficiently large forces on the film of structural material at the edges of the recessed areas, so that a tearing takes place and undesirable remaining on the semiconductor device film remains due to low acting forces as described previously avoided.
  • the entire film of structural material is provided in step B2 with a grid-like perforation.
  • the regions not covered by the masking layer are advantageously cut out, so that the film of structural material is not perforated in the regions in which the structure is to be produced on the semiconductor component.
  • Raster-like perforation leads to a variety of points of attack for the solvent on the masking layer, so that an optimal acceleration of the detachment process in step C is achieved.
  • the partial removal of the film of structural material in method step B2 can advantageously be carried out mechanically. This is conceivable for example by scribing with pointed or knife-like devices, as well as a milling or cutting by means of a rotating blade is possible.
  • the film of structural material is partially removed by local action of radiation.
  • a partial removal of the film by means of a laser is advantageous.
  • devices are known which allow an exact positioning of the laser beam relative to the semiconductor device and also a rapid change between several points on the surface of the semiconductor device, for example by the use of rotary mirrors in the beam path of the laser beam.
  • the film of structural material can be perforated in a very short time at a large number of points, in particular by evaporation of the structural material by means of the laser beam.
  • Method step B2 is to select this removal process such that the semiconductor component is not impaired, in particular that the electrical properties of the semiconductor component are not changed and impaired, for example, by introduction of impurities in the semiconductor structure.
  • the energy of the irradiation for removing the film of structural material and the thickness of the masking layer has a predetermined minimum thickness, so that the laser beam may indeed have a change in the masking layer, but not
  • 1 .mu.m in particular at least 5 .mu.m, most preferably 10 .mu.m, further in particular in the range of 20 microns to 40 microns when using a laser for opening the metal film is advantageous.
  • Masking layer in method step A can be carried out by a photolithography method known per se:
  • the surface of the semiconductor component is first covered with a photosensitive resist in a method step A1.
  • the photosensitive resist is exposed in a method step A2 in the areas in which the surface of the semiconductor device is to be covered with the structural material. Thereafter, in a method step A3, the photosensitive resist is developed so that only the exposed regions of the photosensitive resist are removed from the surface of the semiconductor component.
  • the masking layer is applied to the semiconductor component in method step A by means of screen printing methods known per se or by means of ink jet methods known per se, ie in this case on the solar cell wafer becomes.
  • alkaline solvents such as weakly concentrated potassium hydroxide solution (e.g., KOH diluted to 3%) is advantageous.
  • a dibasic ester may advantageously be used, e.g. by LEMRO, Chemie effort, Michael Mrozyk KG, D-41515 Grevenbroich, under the designation "DBE.” This has the additional advantage that a metal film is not attacked by the dibasic ester.
  • a typical masking varnish can be used for the masking layer applied by means of screen printing or inkjet processes, in particular the masking varnish offered by Lackwerke Peters GmbH + Co KG, D-47906 under the name "SD 2154E" of the previously described "DBE".
  • the metal is applied by evaporation or sputtering.
  • Figure 1 is a schematic representation of the inventive method for producing a metallization on a solar cell
  • Figure 2 is a plan view of a solar cell having a metallization structure, wherein indicated by dots, at which points a perforation by means of the method according to the invention takes place.
  • the method according to the invention is particularly suitable for applying a metallization structure to a solar cell.
  • a semiconductor component is shown in partial image a), which is designed as a solar cell 1, which consists in this example of a silicon wafer with corresponding dopants for generating a pn junction.
  • the representation in sub-image a) represents a process stage in which a dielectric layer 2 has already been structured by means of a masking layer 3:
  • a dielectric layer 2 was applied to the entire surface of the solar cell 1 and printed thereon by means of screen printing a masking layer 3 which eliminates the areas in which metallization of the solar cell is desired.
  • the masking layer 3 consists of the above-mentioned resist "SD 2154 E", that is, the masking layer is an etching resist and is not attacked by corrosive substances Thus, by an etching step, the dielectric layer 2 can be etched away in the areas of the masking layer 3.
  • the masking layer 3 has a thickness in the range of 20 ⁇ m to 40 ⁇ m.
  • a film of structural material is then applied over the whole area, which in this case is realized as a metal film 4.
  • the metal film 4 was applied in a known manner by means of vapor deposition and consists of several layers: First, an aluminum layer with about 300 nm thickness is evaporated, then an about 30 nm thick layer of titanium and about 100 nm thick layer of silver. On the one hand, this ensures a good electrical and mechanical contact between the metal structure and semiconductor and, on the one hand, a low ohmic transverse line resistance of the metal structure. As can be seen in panel b), the metal film 4 thus covers, on the one hand, the masking layer 3 and, on the other hand, the solar cell 1 in the areas recessed by the masking layer 3.
  • the metallization layer 4 was locally evaporated at individual points 8, 8 '.
  • the pulse energy of the laser beam was chosen to be less than 5 .mu.J in order to avoid damage to the solar cell by the laser beams. In particular, a pulse energy of 2 ⁇ J is advantageous according to investigations by the applicant.
  • the perforation was carried out by means of a frequency-tripled Nd: YAG laser with a wavelength of 355 nm.
  • the laser uses pulsed laser radiation, with pulse lengths ranging from 20 ns to 30 ns.
  • FIG. 2 shows a plan view of a solar cell with a comb-like metallization structure 10 shown in greatly simplified form:
  • the solar cell 1 has a comb-like metallization structure 10, via which charge carriers can pass from the silicon wafer via the metallization structure to a contact point (not shown).
  • the dots in Figure 2 indicate the perforations along predetermined lines, two of which are exemplified by the reference numerals 11, 11 '.
  • the perforations shown follow lines which are arranged approximately at a constant distance of 500 ⁇ m from the areas recessed by the masking layer, that is to the metallization structure 10, so that a defined break of the metal film is present at the edges of the metallization structure 10.
  • a typical comb-like metallization structure typically has a plurality of (over 80) upwardly extending "fingers" in FIG. 2, the fingers being approximately at a distance of Have 1200 microns to each other and have a width of about 150 microns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photovoltaic Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé permettant d'appliquer une structure prédéfinie à base de matériau structural sur un composant à semi-conducteurs, selon lequel il est prévu les étapes suivantes: A) recouvrir partiellement une surface du composant à semi-conducteurs avec une couche de masquage, B) appliquer un film à base de matériau structural sur la couche de masquage et dans les zones réservées par la couche de masquage, sur la surface du composant à semi-conducteurs et C) éliminer la couche de masquage avec le matériau structural se trouvant sur ladite couche de masquage. A cet égard, il est essentiel que le film à base de matériau structural situé soit partiellement éliminé à l'étape B2, entre l'étape B et l'étape C.
EP07856974A 2007-02-06 2007-12-20 Procédé pour appliquer une structure sur un élément à semi-conducteurs Withdrawn EP2118927A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007006640A DE102007006640A1 (de) 2007-02-06 2007-02-06 Verfahren zum Aufbringen einer Struktur auf ein Halbleiterbauelement
PCT/EP2007/011251 WO2008095526A2 (fr) 2007-02-06 2007-12-20 Procédé pour appliquer une structure sur un élément à semi-conducteurs

Publications (1)

Publication Number Publication Date
EP2118927A2 true EP2118927A2 (fr) 2009-11-18

Family

ID=39587390

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07856974A Withdrawn EP2118927A2 (fr) 2007-02-06 2007-12-20 Procédé pour appliquer une structure sur un élément à semi-conducteurs

Country Status (6)

Country Link
US (1) US8236689B2 (fr)
EP (1) EP2118927A2 (fr)
JP (1) JP2010518610A (fr)
CN (1) CN101569004B (fr)
DE (1) DE102007006640A1 (fr)
WO (1) WO2008095526A2 (fr)

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DE202008012829U1 (de) * 2008-09-26 2008-12-04 Nb Technologies Gmbh Siebdruckform
WO2012030407A1 (fr) * 2010-09-03 2012-03-08 Tetrasun, Inc. Métallisation en lignes fines de dispositifs photovoltaïques par enlèvement partiel de revêtements optiques
DE102020118019A1 (de) 2020-07-08 2022-01-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Verfahren und Vorrichtung zur Strukturierung einer Strukturschicht mittels Laserstrahlung
JP7453874B2 (ja) 2020-07-30 2024-03-21 芝浦メカトロニクス株式会社 基板処理方法、および基板処理装置

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Also Published As

Publication number Publication date
WO2008095526A3 (fr) 2008-12-18
WO2008095526A2 (fr) 2008-08-14
CN101569004B (zh) 2011-04-20
US20100301456A1 (en) 2010-12-02
CN101569004A (zh) 2009-10-28
DE102007006640A1 (de) 2008-08-07
JP2010518610A (ja) 2010-05-27
US8236689B2 (en) 2012-08-07

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