EP1971959A2 - Procédé et appareil de traitement de sous-blocs de données multimédia dans des systèmes de traitement en parallèle - Google Patents

Procédé et appareil de traitement de sous-blocs de données multimédia dans des systèmes de traitement en parallèle

Info

Publication number
EP1971959A2
EP1971959A2 EP07716561A EP07716561A EP1971959A2 EP 1971959 A2 EP1971959 A2 EP 1971959A2 EP 07716561 A EP07716561 A EP 07716561A EP 07716561 A EP07716561 A EP 07716561A EP 1971959 A2 EP1971959 A2 EP 1971959A2
Authority
EP
European Patent Office
Prior art keywords
blocks
data
image data
sub
rows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07716561A
Other languages
German (de)
English (en)
Inventor
Lazar Bivolarski
Bogdan Mitu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Brightscale Inc
Original Assignee
Brightscale Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brightscale Inc filed Critical Brightscale Inc
Publication of EP1971959A2 publication Critical patent/EP1971959A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

Definitions

  • the invention relates generally to parallel processing. More specifically, the invention relates to methods and apparatuses for processing of multimedia data in parallel processing systems.
  • a method includes generating blocks of image data, wherein each of the blocks of image data are divided into sub-blocks, and a first data point of each sub-block flags a beginning position of the sub-block, and generating a block of type data
  • 354726-990400 1 Atty Dckt No.: 354726-5405 PATENT for each of the blocks of image data, wherein each of the blocks of type data contains the first data point for all of the sub-blocks in the block of image data.
  • a computer readable medium having computer executable instructions thereon for a method of processing in a parallel processing array having computing elements configured to process blocks of data of an image, the method including generating blocks of image data, wherein each of the blocks of image data are divided into sub-blocks, and a first data point of each sub-block flags a beginning position of the sub- block, and generating a block of type data for each of the blocks of image data, wherein each of the blocks of type data contains the first data point for all of the sub-blocks in the block of image data.
  • FIG. 1 conceptually illustrates macroblocks of a 1080i high definition (HD) frame.
  • FIGS. 2A-2B further illustrate the arrangement of blocks such as macroblocks within an image frame.
  • FIGS. 3A-3C illustrate the mapping of macroblocks from their arrangement within an image to individual parallel processors.
  • FIGS. 4A-4E illustrate the mapping of images to individual parallel processors, for various image formats.
  • FIGS. 5A-5B illustrate 16x8 mapping for mapping subdivisions of images to individual parallel processors.
  • FIGS. 6A-6B illustrate 16*4 mapping for mapping subdivisions of images to individual parallel processors.
  • FIGS. 7A-7C illustrate an alternative approach to mapping image blocks to parallel processors, in accordance with an embodiment of the present invention.
  • FIGS. 8A-8C illustrate further details of the data structure of an image format, including luma and chroma information.
  • FIGS. 9A-9C illustrate various alternative approaches to mapping multiple image blocks to parallel processors, in accordance with an embodiment of the present invention.
  • FIGS. lOA-lOC illustrate data block data locations, sub-block locations, sub-block flag data positions, and a block of type data, in accordance with an embodiment of the present invention.
  • FIGS. 1 IA-I IB illustrate algorithm processing steps and selection codes for identifying which processing steps are applied to which data variables.
  • FIG. 12 illustrates a parallel processor.
  • Like reference numerals refer to corresponding parts throughout the drawings.
  • this innovation relates to a more efficient method for the parallel processing of multimedia data. It is known that, in various image formats, the images are subdivided into blocks, with the "later" blocks, or those blocks that fall generally below and to the right of other blocks in the image as it is typically viewed in matrix form, dependent upon information from the "earlier" blocks, i.e. those images above and to the left of the later blocks.
  • the earlier blocks must be processed before the later ones, as the later ones require information, often called dependency data, from the earlier blocks. Accordingly, blocks (or portions thereof) are transmitted to various parallel processors, in the order of their dependency data. Earlier blocks are sent to the parallel processors first, with later blocks sent later.
  • the blocks are stored in the parallel processors in specific locations, and shifted around as necessary, so that every block, when it is processed, has its dependency data located in a specific set of earlier blocks with specified positions. In this manner, its dependency data can be retrieved with the same commands. That is, earlier blocks are shifted around so that later blocks can be processed with a single set of commands that instructs each processor to retrieve its dependency data from specific locations.
  • FIG. 1 conceptually illustrates an exemplary frame of an image, in its matrix form as it is typically viewed and/or stored in memory.
  • a 1080i HD image matrix 10 is subdivided into 68 lines of 120 macroblocks 12 each.
  • images such as this 108Oi frame are processed by individual macroblock 12.
  • one or more macroblocks 12 are processed by each computing element (or processor) of a parallel processing array.
  • the invention is often discussed in the context of the processing of macroblocks 12, it should be recognized that the invention includes the division of images and other data into any portions, often referred to as blocks, that can be processed in parallel.
  • the macroblocks of images such as the 1080i HD frame of FIG. 1 include dependency data, as further illustrated in FIGS. 2A-2B.
  • dependency data e.g., data required for interpolation, etc.
  • the processing of each block of an image requires dependency data from the block immediately to the left, as well as the block diagonally to the immediate upper left, the block immediately above, and the block diagonally to .the immediate upper right.
  • Block a therefore also depends upon information from blocks d and b, block b depends upon information from block d, and so forth, while block d does not depend on information from any other blocks. It can therefore be seen that parallel processing of these blocks requires processing in diagonals, with block d processed first, followed by blocks a and b as they depend upon information from block d, then blocks R and c as they depend upon information from blocks a, d, and b, and so forth.
  • FIG. 3 A illustrates the macroblock structure of an exemplary image, as the image appears to a viewer. As above, the blocks of FIG. 3 A are processed in an order that retains their dependency data for later blocks.
  • FIG. 3B illustrates the diagonals that must be processed, in the order they must be processed to preserve their dependency data for later blocks. Each row illustrates a separate diagonal, with each
  • block ( )o is processed first, as it is located in the uppermost left corner of the image, and thus has no dependency data.
  • Block Oo is processed next, and thus appears in the next row, as it requires dependency data only from block ( )o.
  • Blocks 11 and Io are processed next, and therefore appear in the following row, as block 1 1 requires dependency data from blocks ( )o and OQ, and block Io requires dependency data from block Oo. It can therefore be seen that each diagonal of blocks in FIG. 3A 5 highlighted by the dashed lines, can be mapped into rows of a parallel processing array as shown in FIG. 3B.
  • mapping blocks into rows of computing elements as shown in FIG. 3B preserves all required dependency data above each row, difficulties still exist. More specifically, the dependency data for each block is still often located in different positions relative to that block.
  • block 4i has dependency data located in the following blocks, in clockwise order: 3i, lo > 2o, and 3o-
  • these processors are located as shown by the arrows, with processors 3i, lo, 2 0 , and 3o arranged in an "L" shape above block 4
  • the dependency data for block 9 3 is located in blocks 83, 82, 1 2 , and 6 2 , which are arranged as shown by the arrows.
  • each computing element will require its own commands directing it to retrieve dependency data.
  • dependency data for each block is arranged differently for each block (as shown by blocks 4i and 9 3 )
  • separate data retrieval commands must be pushed to each processor, slowing down the speed at which images can be processed.
  • this problem is overcome by shifting the dependency data for each block prior to the processing of that block.
  • the dependency data can be shifted in any fashion.
  • FIG. 3C one convenient approach to shifting dependency data is illustrated in FIG. 3C, in which the blocks containing dependency data are shifted into the "L" shape described above. That is, when block X is processed, it requires dependency data from blocks A-D. Within the image, these blocks are located directly above X, to the immediate upper left, directly to the left, and to the immediate upper right, respectively. Within the parallel processing array, these blocks can then be shifted to two processor positions above X, three processor positions above, one processor position above, and the processor position to the immediate
  • FIGS. 4A-4E illustrate this point, showing how diagonals of various types of frames can be mapped into varying numbers of processor rows.
  • the diagonals of an HD frame can be mapped into consecutive rows of processors as shown, creating a trapezoidal (or alternately a rhomboid, or possibly even a combination of both) layout where 257 rows of processors are employed, with a maximum of 61 processors being used in a single row.
  • Smaller frames utilize fewer rows, and fewer processors.
  • a GIF frame utilizes 59 rows of processors, with a maximum of 19 processors employed in any row.
  • a 625 SD frame would occupy 117 rows, and a maximum of 36 processors per row, when mapped into a parallel processing array.
  • an SIF frame would occupy 51 rows, and 16 processors maximum per row, when mapped into the same array.
  • a 525 SD frame would occupy 107 rows, and 30 processors maximum per row.
  • the invention can be employed to
  • 354726-990400 6 Attv Dckt No.: 354726-5405 PATENT map any image to a parallel processing array, where data can be shifted within rows as described above, allowing for processing of blocks with a single command or command set.
  • FIGS. 5A-5B illustrate one such embodiment, in which blocks of an image are divided in two. Each of these divisions is then processed as above, except that each division is mapped into, and processed by, one half of a processor.
  • blocks are divided into a top half and a bottom half as shown. That is, the upper left hand block is divided into two sub-blocks, 0 and 2. Similarly, the block next to it is divided into sub-blocks 1 and 3, and so forth.
  • each sub-block behaves the same as a full block for dependency purposes, i.e., sub-block 1 requires dependency data only from block 0, the leftmost sub-block 2 requires dependency data from blocks 0 and 1 , etc.
  • these sub-blocks are then mapped into halves of processors as shown, with sub-blocks 0 and 1 mapped into the first row, sub-blocks 2 and sub-blocks 3 mapped into the second row, and so on.
  • the processes of the invention can then be employed in the same manner as above, with sub-blocks shifted along rows of processors as necessary.
  • FIG. 5B illustrates that its embodiment increases the number of processors utilized by one for every row: the first row utilizes one processor, the second row two, and so forth. The embodiment of FIGS. 5A-5B thus utilize more processors at a time, resulting in even faster processing.
  • FIGS. 6A-6B illustrate another such embodiment, in which blocks of an image are divided into four subdivisions.
  • the upper left block of an image is divided into sub-blocks 0, 2, 4, and 6.
  • These sub-blocks are then mapped into portions of a processor in the order required by their dependency data. That is, each processor can be divided into four "sub-rows" each capable of processing a row of sub-blocks.
  • the various sub-blocks are described below.
  • 354726-990400 7 Attv Dckt No.: 354726-5405 PATENT can then be mapped into the sub-rows of the processors as shown.
  • the 0, 1, 2, and 3 sub-blocks can all be mapped into two processors in the first row (with the first processor processing sub-blocks 0, 1, one 2 sub-block, and one 3 sub-block, and the second processor processing the other 2 and 3 sub-blocks), and processed accordingly.
  • this embodiment employs two processors in the first row instead of one, and that the number of processors grows by two per row, thus allowing even more processors to be utilized per row.
  • the invention also encompasses the division of blocks and processors into 16 subdivisions.
  • the invention includes the processing of multiple blocks "side by side,” i.e., the processing of multiple blocks per row.
  • FIGS. 7A-7C illustrate both these concepts.
  • FIG. 7 A illustrates the division of a block into 16 sub-blocks ( )o — 8o, as shown.
  • FIG. 7B illustrates the fact that unrelated blocks, i.e. blocks that do not require dependency data from each other, can be processed in parallel. Each block is divided as in FIG. 7A, with sub-blocks shown without subscripts for simplicity.
  • the first block is divided into 16 sub-blocks labeled 0 through 9, with like numbers processed simultaneously as above. So long as the blocks in each row do not require dependency data from each other, they can be processed together, in the same row. Accordingly, one group of processors can process multiple unrelated blocks simultaneously. For example, the top row of four blocks in FIG. 7B (with sub-blocks labeled 0-9, 10-19, 20-29, and 30-39, respectively) can be processed in a single set of processors.
  • FIG. 7C a chart of processors (numbered along the left hand side) and the corresponding sub-blocks loaded into them, illustrates this point.
  • sub-blocks 0-9 can be loaded into subdivisions of processors 0-9 (where processors are labeled along the left hand side) to form the diamond-like pattern shown. Further blocks can then be loaded into overlapping sets of processors, with sub-blocks 10-19 loaded into processors 4-13, etc. In this manner, both further subdivisions of blocks, as well as the "chaining" of multiple blocks into overlapping sets of processors, allows mote processors to be utilized more quickly, yielding faster processing.
  • Figs. 7A-7C illustrate four by four processing. It should be understood that this same technique can be implemented in a eight by eight processing as well.
  • the invention encompasses the separate processing of intensity information, luma information, and chroma information from the same block. That is, intensity information from one block can be processed separately from the luma information from that block, which can be processed separately from the chroma information from that block.
  • intensity information from one block can be processed separately from the luma information from that block, which can be processed separately from the chroma information from that block.
  • luma and chroma information can be mapped to processors and processed as above (i.e., shifted as necessary, etc.), and can also be subdivided, with subdivisions mapped to different processors, for increased efficiency in processing.
  • FIGS. 8A-8C illustrate this. In FIG.
  • one block of luma data can be mapped to one processor, with the corresponding "half-block" of chroma data mapped to the same processor or a different one.
  • the intensity, luma, and chroma data can be mapped to adjacent sets of processors, perhaps in at least partially overlapping sets of rows, similar to FIG. 7B.
  • the luma and chroma information can also be divided into sub-blocks, for processing in subdivisions of individual computing elements, as described in connection with FIGS. 5A-5B, and 6A-6B.
  • FIGS, 8B-8C illustrate the division of one frame's luma and chroma data into two and four sub-blocks, respectively. The two sub-blocks of FIG.
  • FIG. 8B can then be processed in different halves of processors, as described in connection with FIGS. 5A-5B.
  • the four sub-blocks of FIG. 8C can be processed in different quarters of processors, like that described in FIGS. 6A-6B.
  • FIGS. 9A-9C which conceptually illustrate processors occupied by various blocks, describe embodiments of the latter concept.
  • rows of processors extend along the vertical axis, while columns extend along the horizontal axis.
  • regions 100-104 regions 100-104.
  • the region(s) 104 do not occupy many processors, thus reducing the overall utilization of the processing array. This can be at least partially remedied by processing another block of data right below the block that occupies
  • 354726-990400 9 Any Dckt No.: 354726-540.5 PATENT regions 100-104.
  • This block can occupy regions 106-112, allowing more processors to be utilized, particularly in the "transition" regions 104-106 between subsequent blocks. In this manner, processing can be accomplished quicker and with more array utilization than if users were to process the block of regions 106-112 only after processing of the block in regions 100-104 was completed.
  • FIGS. 9B-9C illustrate further extensions of this concept.
  • this vertical "chaining" of mapped blocks can be continued over two or more blocks, resulting in significantly higher array utilization.
  • blocks can be mapped into adjacent columns one after another, with regions 116-120 occupied by one block, regions 122-126 occupied by another block, etc.
  • rhomboid shapes can be used instead of or in conjunction with the trapezoidal shapes.
  • any combination of mappings of different formats could be achieved by different sizes or combinations of rhomboids and/or trapezoids to facilitate the processing of multiple streams simultaneously.
  • the invention contemplates use by any parallel processor having multiple computing elements capable of each processing a block of image data, and shifting such data to preserve dependencies. While many such parallel processors are contemplated, one suitable example is described in U.S. Patent Application No. 11/584,480 entitled "Integrated Processor Array, Instruction Sequencer And I/O Controller," filed on October 19, 2006, the disclosure of which is hereby incorporated by reference in its entirety and for all purposes.
  • FIGS. 10A- 1OC illustrate the innovations relating to sub-block parallel processing.
  • each macroblock 12 is a matrix of 16 rows by 16 columns (16x16) of data bits (i.e. pixels), broken up into 4 or more sub-blocks 20. Specifically, each matrix is broken into at least four equal quadrant sub-blocks 20 that are 8x8 in size. Each quadrant sub-block 20 can be further broken up into sub-blocks 20 having sizes that are 8x4, 4x8 and 4x4. Thus, any given block 12 can be broken up into sub-blocks 20 having sizes that are 8x8, 4x8, 8x4 and 4x4.
  • FIG. 1OA illustrates a block 12 with one 8x8 sub-block 20a, two 4x8 sub-blocks 20b, two 8x4 sub-blocks 20c, and four 4x4 sub-blocks 2Od.
  • the numbers of each sized sub- block 20, if any, can vary, as well as their locations within the block 12. Further, the numbers and locations of the various sized sub-blocks 20 can vary from block 12 to block 12.
  • FIG. 1OB illustrates the block 12, and shows the sixteen data locations 22 that could possibly form the first data location for any given sub-block 20 (first meaning the most upper left entry of the sub-block 20). For each block 12, these sixteen positions 22 will contain the data necessary to flag whether this data position constitutes the first entry of a new sub-block 20.
  • this position is considered the starting point of a data-block 20, and the position to its immediate left (if any) is considered the last column of the sub-block 20 immediately to the left, and the position immediately above (if any) is considered the last row of the sub-block 20 immediately above. If it is not flagged, then this entry signifies a continuation of a same sub-block 20. Thus, it can be seen that these sixteen flag data locations 22 contain all the data necessary to determine the locations and sizes of the sub- blocks 20.
  • FIG. 1OC illustrates the type data block according to this innovation, where a block of type data 24, which has a 16x4 size, is associated with each block 12.
  • the four rows of block 24 correspond to the four rows in the block 12 that contain the flag data positions 22.
  • 354726-990400 1 1 Attv Dckt No.: 354726-5405 PATENT analysis of the block 12 is needed for this purpose.
  • remaining data positions in the block 20 can be used to store other data, such as sub-block type (I-locally predicted, P- predicted with motion vectors, and B-bidirectionally predicted), block vectors, etc.
  • sub-block type I-locally predicted, P- predicted with motion vectors, and B-bidirectionally predicted
  • block vectors etc.
  • Another source of parallel processing optimization involves simultaneously processing algorithms having certain similarities (e.g. similar calculations).
  • Computer processing involves two basic calculations: numerical computations and data movements. These calculations are achieved by processing algorithms that either compute the numerical computations or move (or copy) the desired data to a new location.
  • Such algorithms are traditionally processing using a series of "IF" statements, where if a certain criteria is met, then a one calculation is made, whereas if not then either that calculation is not made or a different calculation is made. By navigating through a plurality of IF statements, the desired total calculation is performed in each data.
  • IF IF
  • the same code (algorithm) is generally applied to all data, and only the selection codes need to be tailored for each data to determine how each calculation is made.
  • the advantage here is that if plural data are being processed in which many of the processing steps are the same, then applying one algorithm code with both the calculations in common and those that are not in common simplifies the system. In order to apply this
  • Figs. 1 IA and 1 IB illustrate an example of the above described concept.
  • This example involves bilinear filters used to generate intermediate values between pixels, in which certain number computations are made (although this technique can be used for any data algorithms).
  • the algorithms need to compute the various values use the same basic set of numerical additions and data shifting steps, but the order and numbering of these steps differ based upon the computation being made.
  • the first computation for the 1/2 and 3/4 Bi-Cubic equation is the number 53, which requires 7 computation steps to make.
  • the second computation is the number 18, which requires 6 computation steps, four of which are in common with, and in the same order as, the same four steps as they occur in the previous computation.
  • the last two computations for the first equation again have overlapping computation steps with the first two calculations.
  • Additional computations for 1/2 Bi-Cubic equation, as well as the three Bi-Linear equations of Fig. 1 IB all involve various combinations of the same calculation steps, and all have four computations to make.
  • a selection code of "0011" dictates that the step will only be applied to the third and fourth variables, but not the first and second variables.
  • the second step is applied only to the second variable, as dictated by the selection code "0100".
  • the same methodology is applied for all the steps and variables of all the equations using the selection codes shown.
  • the advantage of using selection codes is that instead of generating twenty algorithm codes to make the twenty various computations illustrated in Figs. 1 IA and 1 IB (or at the very least eight different algorithm codes to make the eight distinct numerical
  • FIGs. 1 IA and 1 IB illustrate the use of selection codes for a data computation application
  • selection codes used for selectively dictating which algorithm steps to apply to data is equally applicable for algorithms used to move data.
  • the invention can be employed to process any subdivisions of any image format. That is, the invention can process in parallel images of any format, whether they be 1080i HD images, CIF images, SIF images, or any other. These images can also be broken into any subdivisions, whether they be macroblocks of an image, or any other.
  • any image data can be so processed, whether it be intensity information, luma information, chroma information, or any other.
  • the embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
  • the present invention can be embodied in the form of methods and apparatus for practicing those methods.
  • the present invention can also be embodied in the form of program code embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, firmware, or any other machine-readable storage medium, wherein, when the
  • PATENT program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
  • the present invention can also be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
  • the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits.

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Abstract

L'invention concerne un procédé et un dispositif efficaces dans le traitement en parallèle de sous-blocs de données. Un réseau de traitement parallèle comprend des éléments de calcul configurés pour traiter des blocs de données d'une image en parallèle. Des blocs de données d'image sont produites, chacun desdits blocs de données d'image est divisé en sous-blocs, un premier point de données de chaque sous-bloc marquant une position de commencement du sous-bloc. Un bloc de données types est créé pour chacun des blocs de données d'image. Chacun des blocs des données types renferme le premier point de données pour tous les sous-blocs dans le bloc de données d'image, de telle manière que les numéros et les emplacements de tous les sous-blocs dans chaque bloc de données d'image peuvent être déterminés sans avoir, d'abord, à traiter le bloc de données d'image.
EP07716561A 2006-01-10 2007-01-10 Procédé et appareil de traitement de sous-blocs de données multimédia dans des systèmes de traitement en parallèle Withdrawn EP1971959A2 (fr)

Applications Claiming Priority (2)

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US75806506P 2006-01-10 2006-01-10
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