TW200737983A - Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems - Google Patents

Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems

Info

Publication number
TW200737983A
TW200737983A TW096101018A TW96101018A TW200737983A TW 200737983 A TW200737983 A TW 200737983A TW 096101018 A TW096101018 A TW 096101018A TW 96101018 A TW96101018 A TW 96101018A TW 200737983 A TW200737983 A TW 200737983A
Authority
TW
Taiwan
Prior art keywords
blocks
sub
data
block
image data
Prior art date
Application number
TW096101018A
Other languages
English (en)
Inventor
Lazar Bivolarski
Bogdan Mitu
Original Assignee
Brightscale Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brightscale Inc filed Critical Brightscale Inc
Publication of TW200737983A publication Critical patent/TW200737983A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Computing Systems (AREA)
  • Signal Processing (AREA)
  • Image Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
TW096101018A 2006-01-10 2007-01-10 Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems TW200737983A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75806506P 2006-01-10 2006-01-10

Publications (1)

Publication Number Publication Date
TW200737983A true TW200737983A (en) 2007-10-01

Family

ID=38257031

Family Applications (3)

Application Number Title Priority Date Filing Date
TW096101018A TW200737983A (en) 2006-01-10 2007-01-10 Method and apparatus for processing sub-blocks of multimedia data in parallel processing systems
TW096101019A TW200806039A (en) 2006-01-10 2007-01-10 Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems
TW096101017A TW200803464A (en) 2006-01-10 2007-01-10 Method and apparatus for scheduling the processing of multimedia data in parallel processing systems

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW096101019A TW200806039A (en) 2006-01-10 2007-01-10 Method and apparatus for processing algorithm steps of multimedia data in parallel processing systems
TW096101017A TW200803464A (en) 2006-01-10 2007-01-10 Method and apparatus for scheduling the processing of multimedia data in parallel processing systems

Country Status (7)

Country Link
US (4) US20070189618A1 (zh)
EP (3) EP1971958A2 (zh)
JP (3) JP2009523291A (zh)
KR (3) KR20080085189A (zh)
CN (3) CN101371262A (zh)
TW (3) TW200737983A (zh)
WO (3) WO2007082042A2 (zh)

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