EP1971032B1 - Schaltungsstruktur für einen Hochleistungs-Zeit-Digital-Wandler - Google Patents

Schaltungsstruktur für einen Hochleistungs-Zeit-Digital-Wandler Download PDF

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EP1971032B1
EP1971032B1 EP08102491.1A EP08102491A EP1971032B1 EP 1971032 B1 EP1971032 B1 EP 1971032B1 EP 08102491 A EP08102491 A EP 08102491A EP 1971032 B1 EP1971032 B1 EP 1971032B1
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output
current
signal
voltage
transistor
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French (fr)
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EP1971032A3 (de
EP1971032A2 (de
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Ke Wu
Jiantao Cheng
Hongjun Sun
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Chiphomer Technology Ltd
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Chiphomer Technology Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the present invention relates to a circuit structure and in particular to a circuit structure of a high performance time-to-digital converter for converting a time interval into a digital signal.
  • a Time-to-Digital converter refers to a timer for converting a time interval into a digital signal.
  • a basic time-to-digital converter uses a counter to count a series of digital pulses within a time range to be tested. Although stable high speed pulses can be realized by an existing oscillator counting method, the resultant power consumption and noise may be unacceptable.
  • An actually effective method is to measure a large time at a relatively low measuring frequency and to perform a special process on the time remainder shorter than one cycle of the measured period for the purpose of precise measurement.
  • a capacitor voltage method within the range of a part to be tested, a capacitor is charged with a current and then is discharged after it becomes fully charged. The time used for one charge and discharge is referred to as one cycle. During a period shorter than one cycle, the voltage of the capacitor varies with the charging time, and the magnitude of the voltage is converted into a digital magnitude using an Analog-to-Digital converter (ADC), thereby realizing precise measurement for the period shorter than one cycle.
  • ADC Analog-to-Digital converter
  • This method may be disadvantageous in that a high precision Analog-to-Digital ADC converter is required and a design thereof has to take a series of complex factors into account; it is difficult to guarantee linearity of the capacitor voltage; and the charging current is liable to interference from external conditions.
  • a time extension method it is analogous to the above method except that at the end of the period to be tested, the capacitor is discharged with a rated current far smaller than the charging current until the voltage of the capacitor drops to a voltage at initial charging; and during discharging, this much multiplied period is measured using a timer.
  • the charging current has to be larger than the discharging current by a plurality of times for the purpose of a high precision, and thus the discharging current have to be very small and the charging current has to be large in order to attain a sufficiently large ratio of charging current to discharging current
  • An excessively small discharging current is liable to interference and it is infeasible to realize an excessively large charging current.
  • an additional period dedicated for processing is required for discharging the capacitor slowly at the end of the measured period, thus failing to implement continuous time-to-digital conversion.
  • a vernier caliper method the basic principle is that three sets of pulse waveforms, i.e. a set of reference pulses and two sets of trigger pulses, are generated, where the two sets of trigger pulses each have a cycle identical to that of the other but slightly different from that of the set of reference pulses, and the three sets of pulses are counted respectively by three counters; at the start of start pulses, the start counter counts the start pulses and stops counting when the start pulses overlap with the reference pulses; likewise, the end counter counts end pulses until they overlap with the reference pulses; and the reference counter counts the reference pulses between the start pulses and the start of the end pulses.
  • This method has a resolution determined by the difference between the cycles of the two kinds of pulses.
  • WATANABE T et al. in "A CMOS TIME-TO-DIGITAL CONVERTER LSI WITH HALF-NANOSECOND RESOLUTION USING A RING GATE DELAY LINE” discloses a time to digital converter using a ring gate delay line, wherein the ring gate delay system takes two pulses PA and PB as inputs.
  • US-B-6 348 839A discloses a delay circuit for a ring oscillator, which includes a first electric potential line, a pair of output lines, a pair of two first transistors arranged between the first electric potential line and the pair of output lines, respectively, a second electric potential line, and a pair of two second transistors arranged between the second electric potential line and the pair of output lines, respectively. Respective gates of the first transistors are connected to the pair of output lines, respectively, the first transistors, and the second transistors are connected to each other center-symmetrically, and the output lines are connected to a third electric potential line.
  • Such a circuit can easily realize a differential gain of more than or equal to 1 and an in-phase gain of less than or equal to 1.
  • US-A-5 905 412 discloses a current controlled oscillator circuit comprising a variable-ratio current mirror for providing a variable output current to a multi-stage ring oscillator that has a plurality of series connected current controlled inverters stages.
  • US-A-5 331 295 discloses a voltage controlled oscillator (VCO), where process spread, temperature and supply voltage variations have minimal effect on output frequency.
  • VCO voltage controlled oscillator
  • the present invention provide a circuit structure of a high performance time-to-digital converter as defined in claim 1.
  • the dependent claims relate to individual embodiments of the invention.
  • Embodiments of the invention provide a circuit structure of a high performance time-to-digital converter which employs a fully digital method, uses a CMOS gate level delay as a minimum measurement unit, and can achieve a high measurement precision.
  • the delay link loop includes a delay unit loop, comparators, latches, a coder and an initialization unit.
  • a start signal STA turns on the delay unit loop via the initialization unit.
  • a signal output from the delay unit loop is converted into a digital signal via the comparators.
  • the digital signal is output via the latches and is particularly output via the last latch as a carry signal.
  • An end signal END enables the latches to latch data at this time and to send the latched data to the coder
  • the coder converts and outputs the data as low bits of the time-to-digital converter.
  • the delay unit loop includes a plurality of connected full differential buffers The last buffer is connected with the first buffer in antiphase, and each of the remaining buffers is connected with the next buffer in phase.
  • Each of the buffers includes a P channel field effect transistor, a signal switch EN and MOS transistors MP1, MP2, MN1, MN2, MN3 and MN4.
  • Sources of the MOS transistors MN1, MN2, MN3 and MN4 are connected with each other and then are grounded.
  • Gates of the MOS transistors MN and MN3 are connected with each other and then are connected sequentially with drains of the MOS transistors MN2 and MN3 and an output terminal OUT-.
  • Gates of the MOS transistors MN2 and MN4 are connected with each other and then are connected sequentially with drains of the MOS transistors MN4 and MN1 and an output terminal OUT+.
  • the P channel field effect transistor has a source connected with a supply voltage VDD, a gate connected with a voltage signal V BP of the compensated control source and a drain connected via the signal switch EN with sources of the MOS transistors MP1 and MP2 respectively. Drains of the MOS transistors MP1 and MP2 are connected respectively with the output terminals OUT- and OUT+. Gates of the MOS transistors MP1 and MP2 are connected respectively with input terminals IN+ and IN-, A full differential structure with a dual-terminal input and a dual-terminal output is thus formed, which controls a transmission delay through a voltage controlled current sour-ce.
  • the counter is a traveling wave counter including a plurality of D flip-flops and counts the carry signal from the delay link loop as a high bit output of the time-to-digital converter.
  • the compensated control source includes a low drop out regulator LDO, a current source buffer, a PMOS current mirror, an NMOS current mirror, a bias voltage output transistor and a current setting resistor.
  • the low drop out regulator LDO is connected sequentially with the PMOS current mirror, the current source buffer, the NMOS current mirror and the current setting resistor and provides an internal operation voltage AVDD and a series of reference voltages.
  • the current source buffer and the current setting resistor are connected and cooperate with each other to generate an original reference current which is mirrored by the PMOS current mirror and the NMOS current mirror and is output through the bias voltage output transistor as a voltage signal V BP .
  • a current division PMOS compensated transistor with a gate connected with the low drop out regulator LDO and a drain connected with the PMOS current mirror.
  • NMOS current mirror Provided between the NMOS current mirror and the low drop out regulator LDO is a current division NMOS compensated transistor with a gate connected with the low drop out regulator LDO and a drain connected with the NMOS current mirror.
  • a supply voltage of the bias voltage output transistor is connected with a supply voltage VDD.
  • the low drop out regulator LDO includes a reference source BANDGAP, an error amplifier, an output transistor and voltage division resistors.
  • the reference source BANDGAP has one terminal connected with a negative input terminal of the error amplifier and the other terminal connected with the current source buffer.
  • a positive input terminal of the error amplifier is connected between the voltage division resistors.
  • An output terminal of the error amplifier is connected with a gate of the output transistor.
  • a drain of the output transistor is connected sequentially with the voltage division resistors for voltage division and output.
  • the output data of the buffers is latched in the latches.
  • the carry of the low bit counter is output via the data latch of the last buffer to the high bit counter.
  • the high bit counter is incremented by one upon each cycle of operation of the low bit counter, and the latched data of the last buffer is carried. Therefore, it can be ensured that the cycle of the low bit data matches the carry at the moment of stopping measurement
  • the counter counts the signals in the cycle of T delivered from the delay link loop in a way that the counter is incremented by one upon each period of T as a high bit of the Time-to-Digital Converter.
  • the period of T is 2n (n is the number of stages in the delay link loop) times the minimum measurement precision ⁇ t. n is chosen appropriately to ensure that the counter can count properly the signals in the cycle of T.
  • the last bit of the high bit counter is an overflow bit. When the counter counts to the last bit and is inversed, it indicates that the counter overflows.
  • the minimum time resolution is one buffer transmission delay.
  • a fast processing speed data is generated in real time at the end of measurement without any additional processing time.
  • Fig.1 is a block diagram illustrating the principle of an embodiment of the invention
  • Fig.2 is a circuit principle diagram of a delay link loop according to an embodiment of the invention.
  • Fig.3 is a timing waveform diagram of a delay link loop according to an embodiment of the invention.
  • Fig.4 is a circuit principle diagram of a buffer according to an embodiment of the invention.
  • Fig.5 is a circuit principle diagram of a counter according to an embodiment of the invention.
  • Fig.6 is a timing waveform diagram of a counter according to an embodiment of the invention.
  • Fig.7 is a circuit principle diagram of a compensated source circuit according to an embodiment of the invention.
  • the circuit structure of a high performance time-to-digital converter includes a delay link loop 10 configured to generate low bit data, a counter 20 configured to generate high bit data, and a compensated control source 30.
  • the delay link loop 10 includes a delay unit loop 101, a set of comparators 102, a set of latches 10.3, a coder 104 and an initialization unit 105.
  • the delay unit loop 101 includes n (a positive integer) buffers each with two positive and negative differential input terminals and two positive and negative differential output terminals. Each buffer is connected with the next buffer via their in-phase terminals, and the last buffer has a positive output terminal connected with the negative input terminal of the first buffer and a negative output terminal connected with the positive input terminal of the first buffer to thereby realize inversion.
  • a dual-terminal signal output from each buffer is converted by one of the comparators COMP into a uni-terminal signal which is in turn output via one of the latches.
  • the last latch outputs a carry signal entering the high bit counter 20 via a carry terminal.
  • the outputs of the latches are coded by the coder 104 as low bits of the Time-to-Digital Converter.
  • the initialization unit 105 structured simply with a pull-up P transistor and a pull-down N transistor sets the signals output from the first buffer in a way that the positive terminal is set at a low level and the negative terminal is set at a high level. Since the remaining buffers are conducting, the differential signals are passed down. At this time the outputs of all the comparators COMP are low bits (denoted with 0).
  • the initialization unit 105 When a start signal STA is provided, the initialization unit 105 is disabled and the first buffer conducts. Since the signal output of the last buffer is connected with the input of the first buffer in antiphase, the output of the first stage is inverted after a transmission delay of time ⁇ t, and the output of the first comparator COMP is at a high level (denoted with 1); the output of the second stage is inverted after another transmission delay of time ⁇ t; and so on.
  • a transmission delay timing diagram is illustrated in Fig.3 .
  • the outputs of the comparators COMP are passed to the latches, and the outputs of the latches vary with time as depicted in the table below.
  • the buffer includes a P channel field effect transistor, a signal switch EN and MOS transistors MP1, MP2, MN1, MN2, MN3 and MN4.
  • the P channel field effect transistor has a source connected with a supply voltage VDD, a gate connected with a voltage signal V BP of the compensated control source and a drain connected via the signal switch EN with sources of the MOS transistors MP1 and MP2, respectively. Drains of the MOS transistors MP1 and MP2 are connected respectively with output terminals OUT- and OUT+, and gates of the MOS transistors MP1 and MP2 are connected respectively with input terminals IN+ and IN-.
  • the P channel field effect transistor is used for an input due to the possibility of fabricating it into a separate well to reduce interference from external. Since a small transmission delay is necessary for a high precision, the MOS transistors shall be made in as a small size as possible to reduce power consumption and the transmission delay. In this high speed circuit, the time for inversion of an MOS transistor is determined primarily by the time it takes for a gate capacitor to be charged and discharged to a threshold voltage and by an equivalent RC delay over a metal line in a pattern. A smaller MOS transistor results in a small gate capacitor, and a shorter and thinner wire results in a small RC delay, thereby resulting in a small transmission delay.
  • Sources of the MOS transistors MN1, MN2, MN3 and MN4 are connected with each other and then are grounded. Gates of the MOS transistors MN1 and MN3 are connected with each other and then are connected sequentially with drains of the MOS transistors MN2 and MN3 and the output terminal OUT-. Gates of the MOS transistors MN2 and MN4 are connected with each other and then are connected sequentially with drains of the MOS transistors MN4 and MN1 and the output terminal OUT+.
  • a voltage controlled current source converts a bias voltage into a current to control the transmission delay.
  • the differential structure can, on one hand, reduce common mode interference, and on the other hand, select in-phase transmission or in-antiphase transmission.
  • the MOS switch is controlled by a signal switch EN, and before STA is enabled, the switch of the first stage is opened and the switches of the remaining stages are closed.
  • the comparator COMP is a conventional fast hysteresis comparator, and a design thereof shall take a small size and a large current into account.
  • the latch is a part of a master-slave D flip-flop which is in a conducting status during normal operation where its output is equal to its input.
  • a latch signal here the END signal
  • the input signal at this time is latched in an inverter loop, and the output is kept unchanged despite the jumping input.
  • the codes are as depicted in the following table.
  • Time b1b2b3b4 b5b6b7b8 Code output 0 00000000 0000 ⁇ t 10000000 0001 2 ⁇ t 11000000 0010 3 ⁇ t 11100000 0011 4 ⁇ t 11110000 0100 5 ⁇ t 11111000 0101 6 ⁇ t 11111100 0110 7 ⁇ t 11111110 0111 8 ⁇ t 11111111 1000 9 ⁇ t 01111111 1001 10 ⁇ t 00111111 1010 11 ⁇ t 00011111 1011 12 ⁇ t 00001111 1100 13 ⁇ t 00000111 1101 14 ⁇ t 00000011 1110 15 ⁇ t 00000001 1111 16 ⁇ t 00000000 0000 carry
  • the counter 20 is a traveling wave counter including m (a positive integer) D flip-flops triggered with a falling edge.
  • m a positive integer
  • the carry signal gives a falling edge
  • the first stage Qk+1 of the traveling wave counter jumps; when Qk+1 jumps from 1 to 0 after a cycle, the second stage Qk+2 jumps; and so on
  • the cycles of the carry signals are counted, the timing of which is as illustrated in Fig.6 .
  • the (m+1) th D flip-flop acts in a way that the OF output is 1, indicating that the counter overflows.
  • the D flip-flop Dff is a conventional master-slave D flip-flop triggered with a falling edge. In such a way of connection, a current stage jumps by a cycle and the next stage jumps by half a cycle, thus implementing binary counting Description of its structure is omitted here.
  • the low bit timer including the delay unit loop 10 and the high bit timer including the counter 20 may simply function well as a time-to-digital converter, but readings of the Time-to-Digital Converter for a fixed period of time fluctuate in a relatively large range along with an external supply voltage fluctuation, a change of temperature and a process variation.
  • the reading fluctuation is largely due to a delay fluctuation of the delay unit loops 101. Since the voltage controlled current source control is adopted for the delay unit loops 101, we can know from a simulation under the condition of a constant current (the current does not fluctuate along with the temperature, voltage and process fluctuations) that the delay link loop 10 fluctuates mainly along with a MOS transistor model but rarely along with the temperature and supply voltage fluctuations.
  • the readings of the Time-to-Digital Converter obtained in FF (a fast N transistor and a fast P transistor, i.e., an extreme process angle) and SS (a slow N transistor and a slow P transistor, i.e., another extreme process angle) have a deviation of approximately 20% relative to TT (a typical case).
  • the FF readings are 20% more than the TT readings, and the SS readings are 20% less than the TT readings. Therefore such a compensated control source is required that firstly it shall be a constant current source and secondly it can decrease the current in the case of FF and increase the current in the case of SS.
  • the compensated control source 30 includes a low drop out regulator LDO 301, a current source buffer 302, a PMOS compensated transistor 303, an NMOS compensated transistor 304, a PMOS current mirror 305, an NMOS current mirror 306, a bias voltage output transistor 307 and a current setting resistor 308.
  • the low drop out regulator LDO 301 is connected sequentially with the PMOS compensated transistor 303, the PMOS current mirror 305, the current source buffer 302, the NMOS compensated transistor 304, the NMOS current mirror 306 and the current setting resistor 308.
  • the low drop out regulator LDO 301 includes a reference source BANDGAP configured to generate a voltage V BG with a temperature coefficient of zero, an error amplifier, an output transistor and a voltage division resistor-
  • the low drop out regulator LDO 301 generates an internal operation voltage AVDD and a series of reference voltages, and all the voltages are of a temperature coefficient of zero.
  • the current source buffer 302 and the current setting resistor 308 function to generate an original reference current If there is a high requirement on a value of the current, an external resistor is used as the current setting resistor 308, and at this time the reference voltage V REF is a voltage with a temperature coefficient of zero. If the current with a deviation is allowable, an internal resistor is used as the current setting resistor 308, and at this time the reference voltage V REF is a reference voltage with the same temperature coefficient as that of the internal resistor, and a voltage with a specific temperature coefficient can be introduced from inside the reference source BANDGAP. Thus the temperature coefficient of the current can be counteracted, and the inherent deviation of the current will only be a resistor process deviation.
  • the bias voltage transistor 307 converts the current signal into a voltage signal V BP to be connected with the bias voltage V BP of the buffer in Fig.2 .
  • the supply voltage of the bias voltage transistor 307 and the supply voltage of the buffers in the delay link loop are connected to the same potential VDD.
  • the V 1 is set appropriately so that the PMOS compensated transistor 303 is provided with a constant gate supply voltage V 1 -V AVDD .
  • the PMOS transistor operates at a fast process angle, a larger current is drawn therefrom (relative to a typical case), so that the current eventually flowing to the buffer illustrated in Fig.4 becomes smaller, thereby increasing the delay to counteract the immoderately small delay due to the fast PMOS transistor in the buffer. If the PMOS transistor operates at a slow process angle, a smaller current is drawn therefrom (relative to a typical case), so that the current eventually flowing to the buffer illustrated in Fig.4 becomes larger, thereby decreasing the delay to counteract the immoderately large delay due to the slow PMOS transistor in the buffer.
  • NMOS current mirror 306 There is provided at the NMOS current mirror 306 a current division NMOS compensated transistor 304 with a source connected with a reference voltage V 2 generated by the voltage division resistor of the low drop out regulator LDO 301, so that the NMOS compensated transistor 304 is provided with a constant gate supply voltage V 2 . If the NMOS transistor operates at a fast process angle, a larger current is drawn therefrom (relative to a typical case), so that the current eventually flowing to the buffer illustrated in Fig.4 becomes smaller, thereby increasing the delay to counteract the immoderately small delay due to the fast NMOS transistor in the buffer.
  • NMOS transistor operates at a slow process angle, a smaller current is drawn therefrom (relative to a typical case), so that the current eventually flowing to the buffer illustrated in Fig.4 becomes larger, thereby decreasing the delay to counteract the immoderately large delay due to the slow NMOS transistor in the buffer.

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Claims (9)

  1. Schaltungsstruktur für einen Hochleistungs-Zeit-Digital-Wandler, mit:
    - einer Verzögerungs-Link-Schleife (10), die zum Erzeugen von Niedrig-Bit-Daten konfiguriert ist, wobei die Verzögerungs-Link-Schleife (10) PMOS-Transistoren und NMOS-Transistoren aufweist, und
    - einem Zähler (20), der zum Erzeugen von Hoch-Bit-Daten konfiguriert ist,
    - wobei die Verzögerungs-Link-Schleife (10) ferner derart konfiguriert ist, dass sie Niedrig-Bits zählt und ein entsprechend erzeugtes Signal in einem bestimmten Zyklus an den Zähler (20) übermittelt, und
    - wobei der Zähler (20) ferner derart konfiguriert ist, dass er eine Periode des Signals in dem bestimmten Zyklus als Hoch-Bits des Zeit-Digital-Wandlers akkumuliert,
    - eine Kompensations-Steuer-Quelle (30),
    - wobei die Kompensations-Steuer-Quelle (30) zum Kompensieren und Steuern eines Spannungssignals der Verzögerungs-Link-Schleife (10) konfiguriert ist,
    - wobei die Kompensations-Steuer-Quelle (30) einen Niedrig-Drop-Out-Regler (LDO) (301), einen Stromquellen-Puffer (302), einen PMOS-Stromspiegel (305), einen NMOS-Stromspiegel (306), einen Vorspannungs-Ausgangstransistor (307) und einen Stromsetz-Widerstand (308) aufweist,
    - wobei der Niedrig-Drop-Out-Regler (LDO) (301) sequentiell mit dem PMOS-Stromspiegel (305), dem Stromquellen-Puffer (302), dem NMOS-Stromspiegel (306) und dem Stromsetz-Widerstand (308) verbunden ist und zum Ausgeben einer internen Betriebsspannung (AVDD) und einer Serie von Referenzspannungen konfiguriert ist, und
    - wobei der Stromquellen-Puffer (302) und der Stromsetz-Widerstand (308) derart miteinander verbunden sind und zusammenwirken, dass sie einen Original-Referenzstrom erzeugen, der von dem PMOS-Stromspiegel (305) und dem NMOS-Stromspiegel (306) gespiegelt wird und durch den Vorspannungs-Ausgangstransistor (307) als Spannungssignal (VBP) ausgegeben wird.
  2. Schaltungsstruktur nach Anspruch 1, dadurch gekennzeichnet, dass die Verzögerungs-Link-Schleife (10) eine Verzögerungs-Einheits-Schleife (101), Komparatoren (102), Halteschaltungen (103), einen Kodierer (104) und eine Initialisierungseinheit (105) aufweist; wobei ein Start-Signal (STA) die Verzögerungs-Einheits-Schleife (101) über die Initialisierungseinheit (105) einschaltet; ein von der Verzögerungs-Einheits-Schleife (101) ausgegebenes Signal über die Komparatoren (102) in ein Digitalsignal konvertiert wird, das Digitalsignal über die Halteschaltungen (103) ausgegeben wird und insbesondere über die letzte Halteschaltung als Carry-Signal ausgegeben wird, ein End-Signal (END) die Halteschaltungen (103) dahingehend aktiviert, dass sie die Daten an diesem Zeitpunkt halten und die gehaltenen Daten an den Kodierer (104) übermitteln; und der Kodierer (104) derart konfiguriert ist, dass er die Daten als Niedrig-Bits des Zeit-Digital-Wandlers konvertiert und ausgibt.
  3. Schaltungsstruktur nach Anspruch 2, dadurch gekennzeichnet, dass die Verzögerungs-Einheits-Schleife (101) mehrere verbundene Volldifferentialpuffer aufweist, wobei der letzte Puffer mit dem ersten Puffer gegenphasig verbunden ist und jeder der übrigen Puffer mit dem nächsten Puffer phasengleich verbunden ist.
  4. Schaltungsstruktur nach Anspruch 3, dadurch gekennzeichnet, dass jeder der Puffer einen P-Kanal-Feldeffekttransistor, einen Signalschalter (EN) und erste und zweite PMOS-Transistoren (MP1,MP2) und erste bis vierte NMOS-Transistoren (MN1, MN2, MN3 und MN4) aufweist, wobei Quellen der ersten bis vierten NMOS-Transistoren (MN1, MN2, MN3 und MN4) miteinander verbunden sind und dann geerdet sind; Gates der ersten und dritten NMOS-Transistoren (MN1 und MN3) miteinander verbunden sind und dann sequentiell mit Drains der zweiten und dritten NMOS-Transistoren (MN2 und MN3) und einem negativen Ausgangsanschluss (OUT-) verbunden sind; Gates der zweiten und vierten NMOS-Transistoren (MN2 und MN4) miteinander verbunden sind und dann sequentiell mit Drains der vierten und ersten NMOS-Transistoren (MN4 und MN1) und einem positiven Ausgangsanschluss (OUT+) verbunden sind; der P-Kanal-Feldeffekttransistor eine Source, die mit einer Versorgungsspannung (VDD) verbunden ist, ein Gate, das mit einem Spannungssignal (VBP) der Kompensations-Steuer-Quelle verbunden ist, und ein Drain aufweist, das über den Signalschalter (EN) mit Sources der ersten bzw. zweiten PMOS-PMOS-Transistoren (MP1 und MP2) verbunden ist; Drains der ersten und zweiten PMOS-Transistoren (MP1 und MP2) mit den negativen bzw. positiven Ausgangsanschlüssen (OUT- und OUT+) verbunden sind; und Gates der ersten und zweiten PMOS-Transistoren (MP1 und MP2) mit einem positiven bzw. negativen Eingangsanschluss (IN+ und IN-) verbunden sind, wodurch eine Voll-Differentiaistruktur mit einem Doppel-Anschluss-Eingang und einem Doppel-Anschluss-Ausgang gebildet wird, die eine Übertragungsverzögerung durch eine spannungsgesteuerte Stromquelle steuert.
  5. Schaltungsstruktur nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass der Zähler (20) ein Bewegungswellen-Zähler ist, der mehrere D-Flip-Flops aufweist und ferner derart konfiguriert ist, dass er das Carry-Signal aus der Verzögerungs-Link-Schleife (10) als Hoch-Bit-Ausgang des Zeit-Digital-Wandlers zählt.
  6. Schaltungsstruktur nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass zwischen dem PMOS-Stromspiegel (305) und dem Niedrig-Drop-Out-Regler (LDO) (301) ein Stromteilungs-PMOS-Kompensations-Transistor (303) angeordnet ist, der ein mit dem Niedrig-Drop-Out-Regler (LDO) (301) verbundenes Gate und ein mit dem PMOS-Stromspiegel (305) verbundenes Drain aufweist.
  7. Schaltungsstruktur nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass zwischen dem NMOS-Stromspiegel (306) und dem Niedrig-Drop-Out-Regler (LDO) (301) ein Stromteilungs-NMOS-Kompensations-Transistor (304) angeordnet ist, der ein mit dem Niedrig-Drop-Out-Regler (LDO) (301) verbundenes Gate und ein mit dem NMOS-Stromspiegel (306) verbundenes Drain aufweist.
  8. Schaltungsstruktur nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass eine Versorgungsspannung des Vorspannungs-Ausgangstransistors (307) mit einer Versorgungsspannung (VDD) verbunden ist.
  9. Schaltungsstruktur nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass der Niedrig-Drop-Out-Regler (LDO) (301) eine Referenzquelle (BANDGAP), einen Fehler-Verstärker, einen Ausgangstransistor und Spannungsteilungs-Widerstände aufweist; wobei die Referenzquelle (BANDGAP) über einen ihrer Anschlüsse mit einem negativen Eingangsanschluss des Fehler-Verstärkers verbunden ist und über den anderen Anschluss mit dem Stromquellen-Puffer (302) verbunden ist; ein positiver Eingangsanschluss des Fehler-Verstärkers zwischen den Spannungsteilungs-Widerständen angeordnet ist; ein Ausgangsanschluss des Fehlerverstärkers mit einem Gate des Ausgangstransistors verbunden ist; und ein Drain des Ausgangstransistors sequentiell mit den Spannungsteilungs-Widerständen für die Spannungsteilung und dem Ausgang verbunden ist.
EP08102491.1A 2007-03-12 2008-03-11 Schaltungsstruktur für einen Hochleistungs-Zeit-Digital-Wandler Not-in-force EP1971032B1 (de)

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