EP1964129A1 - Procede de lecture de stockage non volatile avec controle efficace de lignes de mots non selectionnees - Google Patents

Procede de lecture de stockage non volatile avec controle efficace de lignes de mots non selectionnees

Info

Publication number
EP1964129A1
EP1964129A1 EP06845066A EP06845066A EP1964129A1 EP 1964129 A1 EP1964129 A1 EP 1964129A1 EP 06845066 A EP06845066 A EP 06845066A EP 06845066 A EP06845066 A EP 06845066A EP 1964129 A1 EP1964129 A1 EP 1964129A1
Authority
EP
European Patent Office
Prior art keywords
voltage
volatile storage
storage element
control gate
unselected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06845066A
Other languages
German (de)
English (en)
Inventor
Teruhiko Kamei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/305,588 external-priority patent/US7545675B2/en
Priority claimed from US11/303,193 external-priority patent/US7369437B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of EP1964129A1 publication Critical patent/EP1964129A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Definitions

  • Non-volatile semiconductor memory has become more popular for use in various electronic devices.
  • non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
  • Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
  • Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate.
  • the floating gate is positioned between the source and drain regions.
  • a control gate is provided over and insulated from the floating gate.
  • the threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
  • the program voltage applied to the control gate is applied as a series of pulses.
  • the magnitude of the pulses is increased with each pulse by a predetermined step size.
  • verify operations are carried out. That is, the programming level of each memory cell being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than a verify level to which it is being programmed.
  • One means of verifying the programming is to test conduction between the memory cell's source and drain at a specific compare point.
  • Conduction represents an "on" state of the device corresponding to the flow of current across the channel of the device.
  • An "off state corresponds to no current flowing across the channel between the source and drain.
  • a flash memory cell will conduct if the voltage being applied to the control gate is greater than the threshold voltage and the memory cell will not conduct if the voltage applied to the control gate is less than the threshold voltage.
  • the threshold voltage of the memory cell By setting the threshold voltage of the memory cell to an appropriate value, the memory cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a memory cell conducts current at a given set of voltages, the state of the memory cell can be determined.
  • Flash memory cells are erased by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block (or other unit) of memory cells.
  • the source and bit lines are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of- cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative.
  • Some flash memory systems use group the memory cells into an array, organized so that a set of bit lines and word lines can be used to address a particular memory cell.
  • the memory cells are grouped into a set of NAND strings.
  • Each NAND string includes multiple transistors in series between two select gates(a drain side select gate SGD and a source side select gate SGS).
  • the select gates (SGD and SGS) are raised to approximately 3 volts and the unselected word lines are raised to a read pass (or enable) voltage (e.g. 5 volts) to make the transistors operate as pass gates.
  • the selected word line is connected to a compare voltage, a level of which is specified for each read or verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level.
  • the source and p-well are at zero volts.
  • the selected bit lines are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the verify or read level applied to the selected word line, the potential level of the concerned bit line maintains the high level because of the non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line decreases to a low level, for example less than 0.5V, because of the conductive memory cell.
  • the state of the memory cell is detected by a sense amplifier that is connected to the bit line.
  • the word lines are at 0 volts.
  • the unselected word lines are raised to the read pass voltage at the same time as the selected word line is raised to the read compare voltage. Because the read pass voltage is generally much larger than the read compare voltage, the word lines are close together and the word lines can be relatively long, coupling noise can appear on the selected word line when it is raised to the read compare voltage while the unselected word lines axe raised to the read pass voltage. This coupling initially raises the voltage of the selected word line; however, the raised voltage will dissipate over time so that the selected word line settles at the intended read compare voltage. To avoid errors, some systems will need to delay the read process in order to wait for the selected word line to settle at the intended read compare voltage. This waiting slows down the reading and/or verification process.
  • Another proposal is to reduce the capacitive coupling of the word lines.
  • To reduce the capacitive coupling of the word lines more expensive materials need to be used or die size needs to be increased in order to increase space in between word lines.
  • Another proposal is to maintain- the word lines at the read pass voltage in between read operations and in between program and verify operations. Therefore, the unselected word lines would not need to be ramped up during a read process.
  • a problem with this approach is that to move the word lines to the read pass voltage from other voltages using during the programming process (or other processes) requires a charge pump or other circuit to sink a large amount of current to bring down the word lines to the read pass voltage. For example, during a program-verify process, the word lines must move from a boosting voltage (e.g. 10 volts) to the read pass voltage (e.g., approximately 5 volts).
  • the technology described herein pertains to a system for reading data (including verifying during programming) from one or more selected nonvolatile storage elements of a group (e.g., NAND string) of non-volatile storage elements.
  • the system maintains an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changes that control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage.
  • the control gate voltage for a selected non-volatile storage element is raised from a standby voltage (which is different than the intermediate voltage) to a read compare voltage.
  • control gate for the selected non-volatile storage element is at the read compare voltage and the control gate for the unselected non-volatile storage element is at the read enable voltage, the state of the selected non-volatile storage element is sensed to determine information about the data stored in the selected non-volatile storage element.
  • One embodiment includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element, changing the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage, maintaining a read voltage as a control gate voltage for a selected non-volatile storage element while the control gate voltage for the unselected non-volatile storage element is at the read enable voltage, and sensing information about data stored in the selected non-volatile storage element in response to the read voltage as the control gate voltage for the selected non- volatile storage element.
  • One embodiment includes raising a control gate voltage for an unselected non-volatile storage element from an intermediate voltage to a read enable voltage, raising a control gate voltage for a selected non-volatile storage element from a standby voltage to a read voltage while raising the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to the read enable voltage, and sensing information about data stored in the selected non- volatile storage element in response to the read voltage.
  • a non-volatile storage system includes a plurality of non-volatile storage elements, word lines in communication with the plurality of non-volatile storage elements, bit lines in communication with the plurality of non-volatile storage elements, and one or more managing circuits in communication with the plurality of non-volatile storage elements.
  • the one or more managing circuits maintain an intermediate voltage on unselected word lines, change the unselected word lines from the intermediate voltage to a read enable voltage, maintain a read voltage on a selected word line while the unselected word lines are at the read enable voltage, and sense information about data stored in a selected non-volatile storage element connected to the selected word line in response to the read voltage on the selected word line.
  • Figure 1 is a top view of a NAND string.
  • Figure 2 is an equivalent circuit diagram of the NAND string.
  • Figure 3 is a cross-sectional view of the NAND string.
  • Figure 4 is a block diagram of one embodiment of a non-volatile memory system.
  • Figure 5 is a block diagram of one embodiment of a non-volatile memory array.
  • Figure 6 is a block diagram depicting one embodiment of a sense amplifier and latches.
  • Figure 7 is a block diagram of one embodiment of charge pump and switching circuits.
  • Figure 8 depicts an example set of threshold voltage distributions.
  • Figure 9 is a flow chart describing one embodiment of a process for programming non-volatile memory.
  • Figure 10 is a signal diagram describing a portion of one embodiment of a programming process.
  • Figure 11 is a flow chart describing one embodiment of a process for reading non-volatile memory.
  • Figure 12 is a signal diagram that depicts one embodiment of a process used when reading non-volatile memory.
  • Non-volatile memory system suitable for implementing the present invention uses the NAND flash memory structure, which includes arranging multiple transistors in series between two select gates.
  • the transistors in series and the select gates are referred to as a NAND string.
  • Figure 1 is a top view showing one NAND string.
  • Figure 2 is an equivalent circuit thereof.
  • the NAND string depicted in Figures 1 and 2 includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122.
  • Select gate 120 connects the NAND string to bit line contact 126.
  • Select gate 122 connects the NAND string to source line contact 128.
  • Select gate 120 is controlled by applying the appropriate voltages to control gate 120CG.
  • Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG.
  • Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate.
  • Transistor 100 has control gate IOOCG and floating gate 100FG.
  • Transistor 102 includes control gate 102CG and floating gate 102FG.
  • Transistor 104 includes control gate 104CG and floating gate 104FG.
  • Transistor 106 includes a control gate 106CG and floating gate 106FG.
  • Control gate IOOCG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WLl, and control gate 106CG is connected to word line WLO.
  • transistors 100, 102, 104 and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may be different than that depicted in Figures 1 and 2.
  • Select gate 120 is connected to select line SGD.
  • Select gate 122 is connected to select line
  • FIG. 3 provides a cross-sectional view of the NAND string described above.
  • the transistors of the NAND string are formed in p-well region 140.
  • Each transistor includes a stacked gate structure that consists of a control gate (IOOCG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG).
  • the floating gates are formed on the surface of the p-well on top of an oxide or other dielectric film.
  • the control gate is above the floating gate, with an inter-polysilicon dielectric layer separating the control gate and floating gate.
  • the control gates of the memory cells (100, 102, 104 and 106) form the word lines.
  • N+ doped layers 130, 132, 134, 136 and 138 are shared between neighboring cells, whereby the cells are connected to one another in series to form a NAND string. These N+ doped layers form the source and drain of each of the cells.
  • N+ doped layer 130 serves as the drain of transistor 122 and the source for transistor 106
  • N+ doped layer 132 serves as the drain for transistor 106 and the source for transistor 104
  • N+ doped layer 134 serves as the drain for transistor 104 and the source for transistor 102
  • N+ doped layer 136 serves as the drain for transistor 102 and the source for transistor 100
  • N+ doped layer 138 serves as the drain for transistor 100 and the source for transistor 120.
  • N+ doped layer 126 connects to the bit line for the NAND string
  • N+ doped layer 128 connects to a common source line for multiple NAND strings.
  • Figures 1-3 show four memory cells in the NAND string, the use of four transistors is provided only as an example.
  • a NAND string used with the technology described herein can have less than four memory cells or more than four memory cells.
  • some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
  • Each memory cell can store data represented in analog or digital form.
  • the range of possible threshold voltages of the memory cell can be divided into two ranges, which are assigned logical data "1" and "0.”
  • the threshold voltage is negative after the memory cell is erased, and defined as logic "1.”
  • the threshold voltage is positive after a program operation, and defined as logic "0.”
  • the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored.
  • the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
  • a memory cell can also store multiple states (known as a multi- state memory cell), thereby storing multiple bits of digital data.
  • the threshold voltage window is divided into the number of states. For example, if four states are used, there will be four threshold voltage ranges assigned to the data values "11,” “10,” “01,” and “00..”
  • the threshold voltage after an erase operation is negative and defined as "11.” Positive threshold voltages are used for the states of "10,” “01,” and "00.”
  • the data values e.g., logical states
  • Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
  • a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
  • Such a cell is described in an article by Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95.
  • a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel.
  • the cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable.
  • the cell is erased by injecting hot holes into the nitride. See also Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
  • Fig. 4 is a block diagram of one embodiment of a flash memory system that can implement the technology described herein.
  • Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c-source control circuit 310 and p-well control circuit 308.
  • Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote or inhibit programming and erasing.
  • Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages and to apply program voltages.
  • C-source control circuit 310 controls a common source line (labeled as "Source” in Fig. 5) connected to the memory cells.
  • P-well control circuit 308 controls the p-well voltage and can provide the erase voltage.
  • the data stored in the memory cells are read out by the column control circuit 304 and are output to external I/O lines via data input/output buffer 312.
  • Program data to be stored in the memory cells are input to the data input/output buffer 312 via the external I/O lines, and transferred to the column control circuit 304.
  • the external I/O lines are connected to controller 318.
  • Command data for controlling the flash memory device is input to controller 318.
  • the command data informs the flash memory device of what operation is requested.
  • the input command is transferred to state machine 316 which is part of control circuitry 315.
  • State machine 316 controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308 and data input/output buffer 312.
  • State machine 316 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.
  • state machine 316 is responsible for managing the programming process, verify process and the read process, including the processes depicted in the flow charts described below.
  • Controller 318 is connected to or connectable with a host system such as a personal computer, a digital camera, or personal digital assistant, etc. It communicates with the host that initiates commands, such as to store or read data to or from the memory array 302, and provides or receives such data. Controller 318 converts such commands into command signals that can be interpreted and executed by command circuits 314 which are part of control circuitry 315. Command circuits 314 are in communication with state machine 316. Controller 318 typically contains buffer memory for the user data being written to or read from the memory array.
  • One exemplary memory system comprises one integrated circuit that includes controller 318, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits.
  • the memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems.
  • a memory card may include the entire memory system (e.g. including the controller) or just the memory array(s) with associated peripheral circuits (with the controller or control function being embedded in the host).
  • the controller can be embedded in the host or included within the removable memory system.
  • one or more of the components of Fig. 4 can be combined.
  • one or more of the components of Fig. 4 (alone or in combination), other than memory cell array 302, can be thought of as a managing circuit.
  • one or more managing circuits may include any one of or a combination of a command circuit, a state machine, a row control circuit (including one or more decoders), a column control circuit (including one or more decoders), a well control circuit, a source control circuit or a data I/O circuit.
  • memory cell array 302 includes NAND flash memory.
  • other types of flash memory and/or other types of non- volatile storage can be used, including those described above as well as others not described above.
  • FIG. 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four memory cells can be used. One terminal of the NAND string is connected to corresponding bit line via a select transistor SGD, and another terminal is connected to c-source via a second select transistor SGS.
  • bit lines are simultaneously selected.
  • the memory cells selected have the same word line and the same kind of bit line (e.g. even bit lines or odd bit lines). Therefore, 532 bytes of data can. be read or programmed simultaneously. These 532 bytes of data that are simultaneously read or programmed form a logical page. Therefore, one block can store at least eight logical pages (four word lines, each with odd and even pages).
  • each memory cell stores two bits of data (e.g., multi-state memory cells), wherein each of these two bits are stored in a different page, one block stores 16 logical pages.
  • Other sized blocks and pages can also be used with the present invention.
  • architectures other than that of Figs. 4 and 5 can also be used to implement the present invention. For example, in one embodiment the bit lines are not divided into odd and even bit lines so that all bit lines are programmed and read concurrently (or not concurrently).
  • Memory cells are erased by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block.
  • the source and bit lines are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells. Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative (in one embodiment).
  • a sense amplifier that is connected to the bit line.
  • Fig. 6 depicts a portion of column control circuit 304 of Fig. 4 that includes a sense amplifier.
  • Each pair of bit lines (e.g. BLe and BLo) is coupled to a sense amplifier 400.
  • the sense amplifier is connected to three data latches: first data latch 402, second data latch 404 and third data latch 406.
  • Each of the three data latches is capable of storing one bit of data.
  • the sense amplifier senses the potential level of the selected bit line during read or verify operations, stores the sensed data in a binary manner, and controls the bit line voltage during the program operation.
  • the sense amplifier is selectively connected to the selected bit line by selecting one of signals of "evenBL” and "oddBL.”
  • Data latches 402, 404 and 406 are coupled to I/O lines 408 to output read data and to store program data. I/O lines 408 are connected to data input/output buffer 312 of Fig 6.
  • Data latches 402, 404 and 406 are also coupled to status line(s) 410 to receive and send status information.
  • a memory system will typically be provided with an external power supply that is commonly referred to as Vcc.
  • Vcc may vary between 2.7 to 3.6volts.
  • a memory system may also receive a ground signal (approximately 0 volts) commonly referred to as Vss.
  • Vdd Some memory systems will create an internal power supply that is referred to as Vdd.
  • Vdd is a regulated and stabilized version of Vcc so that Vdd is regulated to 2.7 volts regardless of whether Vcc varies. In other embodiments, other values for Vdd can be used.
  • the memory system will not have an internal power supply Vdd; therefore, Vcc will be used internally for power by the components of the memory system.
  • FIG. 7 is a block diagram depicting one embodiment of a charge pump and selection circuitry.
  • Charge Pump circuit 460 can be comprised of one or more charge pumps. Technology for implementing charge pumps is well known in the art. Charge Pump circuit 460 is depicted to generate at least four signals Vpgm, Vcgr, Vread and Vpass.
  • the signal Vpgm is the program voltage signal which is applied to the control gates (via the selected word line) of the memory cells selected for programming.
  • the signal Vcgr (sometimes called the read compare voltage or read voltage) is the control gate voltage for the selected memory cells being read.
  • the signal Vread is the read pass (or enable) voltage. When Vread is applied to the control gates of the memory cells in the NAND string, those memory cells receiving Vread will turn on and act as pass gates to enable reading of the selected memory cells.
  • the signal Vpass is used as a boosting signal during the programming process. Vpass is supplied to the control gates of those memory cells on a NAND string that is not selected for programming so that the channel of unselected NAND string will be boosted to a higher voltage to prevent programming of unselected memory cells. This boosting prevents program disturb, which is the unintentional programming of unselected memory cells. Program disturb is well known to the art. More information about program disturb can be found in U.S. Patent 6,859,397, incorporated herein by reference in its
  • FIG 7 shows that two outputs of charge pump circuit 460, Vpgm and Vcgr, are provided to switch 474.
  • Switch 474 also receives Vss. Based on signals received from the state machine, switch 474 will select one of its three input voltages (either Vpgm, Vcgr, or Vss) and provide that selected voltage as the selected word voltage to Row Decoder 480.
  • Two of the outputs from charge pump circuit 460, Vread and Vpass, are provided to switch 472.
  • the signals Vss and Vdd are also provided to switch 472.
  • switch 472 will choose one of the four input voltages (Vread, Vpass, Vss or Vdd) to be provided as the unselected word line voltage to row decoder 480.
  • Row decoder 480 will receive one or more addresses from the state machine. Based on the address received from the state machine, row decoder 480 will determine which word lines will receive the selected word line voltage (WL_sel) and which word lines will receive the unselected word line voltage (WL_unsel). Row Decoder 480 will provide the appropriate voltages on the appropriate word lines to memory cell array 302.
  • the switches and row decoder are controlled by the state machine. In other embodiments, the switches and decoders can be controlled by other components.
  • charge pump 460, switch 472, switch 474 and row decoder 480 are part of row control 306 (see Figure 4). In other embodiments, charge pump 460, switch 472, switch 474 and row decoder 480 can be part of other portions of the memory system.
  • Figure 8 illustrates threshold voltage distributions for the memory cell array when each memory cell stores two bits of data.
  • Figure 8 shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions, A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the E distribution are negative and the threshold voltages in the A, B and C distributions are positive.
  • Each distinct threshold voltage range of Figure 8 corresponds to predetermined values for the set of data bits.
  • the specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
  • One example assigns "11" to threshold voltage range E (state E), “10” to threshold voltage range A (state A), “00” to threshold voltage range B (state B) and “01” to threshold voltage range C (state C).
  • other schemes are used.
  • Figure 8 also shows three read reference voltages, Vra, Vrb and Vrc, for reading data from memory cells.
  • the system can determine what state the memory cell is in. For example, if a memory cell turns on when Vra, Vrb and Vrc are applied to its control gate, then the memory cell is in state E. If a memory cell turns on when Vrb and Vrc are applied to its control gate, but not when Vra is applied to its control gate, then the memory cell is in state A. If a memory cell turns on when Vrc is applied to its control gate, but not when Vra or Vrb are applied to its control gate, then the memory cell is in state B. If the memory cell does not turn on in response to Vra, Vrb or Vrc being applied to its control gate, then the memory cell is in state C.
  • Figure 8 also shows three verify reference voltages, Vva, Vvb and Vvc.
  • Vva verify reference voltages
  • Vvb verify reference voltages
  • memory cells can be programmed from the erased state E directly to any of the programmed states A, B or C.
  • a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased state E. While some memory cells are being programmed from state E to state A, other memory cells are being programmed from state E to state B and/or from state E to state C.
  • Figure 8 also illustrates an example of a two-pass technique of programming a multi-state memory cell that stores data for two different pages: a lower page and an upper page.
  • states are depicted: state E (11), state A (10), state B (00) and state C (01).
  • state E both pages store a "1.”
  • state A the lower page stores a "0" and the upper page stores a "1.”
  • state B both pages store "0.”
  • state C the lower page stores "1" and the upper page stores "0.”
  • bit patterns may also be assigned.
  • the memory cell's threshold voltage level is set according to the bit to be programmed into the lower logical page.
  • the threshold voltage is not changed since it is in the appropriate state as a result of having been earlier erased. However, if the bit to be programmed is a logic "0,” the threshold level of the cell is increased to be state A, as shown by arrow 530. That concludes the first programming pass.
  • the cell's threshold voltage level is set according to the bit being programmed into the upper logical page. If the upper logical page bit is to store a logic "1,” then no programming occurs since the cell is in one of the states E or A, depending upon the programming of the lower page bit, both of which carry an upper page bit of "1.” If the upper page bit is to be a logic "0,” then the threshold voltage is shifted. If the first pass resulted in the cell remaining in the erased state E, then in the second phase the cell is programmed so that the threshold voltage is increased to be within state C, as depicted by arrow 534.
  • the memory cell is further programmed in the second pass so that the threshold voltage is increased to be within state B, as depicted by arrow 532.
  • the result of the second pass is to program the. cell into the state designated to store a logic "0" for the upper page without changing the data for the lower page.
  • a system can be set up to perform full sequence writing if enough data is written to fill up an entire page. If not enough data is written for a full page, then the programming process can program the lower page with the data received. When subsequent data is received, the system will then program the upper page. In yet another embodiment, the system can start writing in the mode that programs the lower page and convert to full sequence progratnrning mode if enough data is subsequently received to fill up an entire (or most of a) word line's memory cells. More details of such an embodiment are disclosed in U.S. Patent Application titled "Pipelined Programming of Non- Volatile Memories Using Early Data," Serial No. 11/013,125, filed on 12/14/04, inventors Sergy Anatolievich Gorobets and Yan Li, incorporated herein by reference in its entirety.
  • Fig. 9 is a flow chart describing one embodiment of a high level process for programming.
  • a request to program data can be received at the controller, the state machine, or another device.
  • data one or more bits of information
  • step 608 the memory cells to be programmed are erased.
  • Step 608 can include erasing more memory cells than those to be programmed (e.g., in blocks or other units).
  • step 608 can include moving all memory cells in a block to state E.
  • step 608 also includes performing a soft programming process. During the erase process, it is possible that some of the memory cells have their threshold voltages lowered to a value that is below the distribution E. The soft programming process will apply program voltage pulses to memory cells so that their threshold voltages will increase to be within threshold voltage distribution E.
  • a "data load" command is issued by controller 318 and input to command circuits 314, allowing data to be input to data input/output buffer 312.
  • address data designating the address for the appropriate portions of memory is input to row control 306 and data to be programmed is stored in the appropriate latches/registers in column control 304.
  • the process of Fig. 9 will be used to program one page of data. AU of the memory cells being programmed are on the same word line. Each memory cell will have its own bit line and a set of latches associated with that bit line. These latches will store indications of the data to be programmed for the associated memory cell.
  • step 610 may include determining which word line is connected to the memory cells to be programmed. This word line is referred to as the selected word line. For example, looking at Fig. 5, if memory cell 380 is to be programmed, then word line WL0_i is the selected word line. Word lines that are not selected are referred to as unselected word lines. In some embodiments, a programming process will have one selected word line and multiple unselected word lines. In some embodiments, it may be possible to have multiple selected word lines.
  • step 612 the magnitude of the first program pulse is set.
  • the voltage applied to the word lines during the programming process is a set of program pulses, with each pulse increasing in magnitude from the previous pulse by a step size (e.g., .2v-.4v).
  • step 614 the program count (PC) will be set to initially be zero.
  • step 616 a program pulse is applied to the appropriate word line(s).
  • step 628 the process of Fig. 12 continues at step 616 and the next program pulse is applied as part of another iteration of the process of steps 616 - 628.
  • Figure 10 is a signal diagram depicting the behavior of the selected word line (WL_sel) and the unselected word lines (WL_unsel) during one iteration of steps 616 and 618 of Figure 9.
  • the time period depicted in Figure 10 is broken up into six periods: standby, setup, program, verify, recovery and standby (again).
  • the selected word line (WL_sel) and the unselected word lines (WL_unsel) are both at Vss. for example, at zero volts or near zero volts. In one embodiment Vss could be near zero volts because of various parasitics that prevent Vss from being exactly at zero volts.
  • the setup phase (which is after the standby phase) the unselected word lines will be raised to Vdd to simplify the control circuitry so that the same voltage level can be used for a start level and end level for both program and read operations.
  • the system enters the program phase.
  • the unselected word lines (WL_unsel) are raised to Vpass, which can be approximately ten volts.
  • the selected word line (WL_sel) is raised to the program voltage Vpgm.
  • the program voltage Vpgm is comprised of a set of program pulses, with each pulse increasing magnitude by a step size (e.g., .2 to .4 volts).
  • the initial voltage level for Vpgm is 12 volts. Other values can also be used with Vpgm.
  • Figure 10 depicts a single program pulse during the program phase.
  • the selected word line (WL_sel) and the unselected word line (WL_unsel) are brought down to lower voltages.
  • the selected word line (WL_unsel) is brought down to Vss while the unselected word lines (WL_unsel) are brought down to Vdd.
  • the system performs a verify phase.
  • the selected word line is raised from Vss to Vcgv.
  • Vcgv (the compare voltage used during the verify process) is chosen based on the target threshold voltage distribution that the particular memory cell is being programmed to.
  • the unselected word lines (WL_unsel) are raised to Vread, as discussed above. While the unselected word lines (WL_unsel) are at Vread and the selected word line (WL_sel) is at Vcgv, the appropriate bit line is pre- charged, provided a path to discharge, and sensed with a sense amplifier. Based on whether the bit line is discharged, it is determined whether the threshold voltage of the memory cell being verified has reached the level of Vcgv.
  • the selected word line (WL_sel) is lowered to Vss and the unselected word lines (WL_unsel) are lowered to Vdd.
  • the unselected word lines (WL_unsel) are brought down to Vss. More detail about the verify phase will be explained below when describing the read process.
  • the read process is used to perform verify for programming.
  • a charge pump is typically good at charging, but not as good at discharging because it is not designed to sink large current. If it is necessary to sink a large current, a discharging circuit would typically be needed.
  • the circuit that manages and regulates Vdd is designed to supply a large current to a lot- of components in the memory system. Therefore, it can effectively sink a large amount of current.
  • the capacitance of Vdd is larger than the word line capacitances so Vdd can absorb change in the word lines without significant change to the voltage of Vdd.
  • the capacitances of unselected word lines tends to be in the hundreds of pico farads (e.g., 30OpF), while the capacitance of Vdd tends to be in the tens to hundreds of nano farads (e.g., 10OnF).
  • Figure 11 is a flow chart describing one embodiment of a process for reading data.
  • the process of Fig. 11 may be performed in response to a request to read data.
  • the system is in standby mode.
  • the system receives a request to read data. This request can be from a host device, from the controller, from the state machine, or another entity.
  • the memory cells that need to be read are identified. This will include determining which pages need to be read, which word line will be selected word line and which word lines will be unselected word lines.
  • the read setup phase will be performed, at which time appropriate signals are set up for the read process.
  • the bit line pre-charge phase is performed.
  • step 710 the bit line is provided with a path to discharge.
  • a sense amplifier will be used to determine whether the bit line discharged.
  • step 712 the signals will be allowed to recover. More details of steps 706-712 will be provided below with respect to Figure 12.
  • steps 708-712 are performed once for the particular Vcgr (or Vcgv). In one embodiment, Vcgr is equal to zero volts for binary memory cells. In embodiments where the memory cells are multi-state memory cells, then the read process will need to test for multiple read compare points, as explained above. Therefore, steps 708-712 will need to be performed multiple times for each read compare point.
  • step 714 the system determines whether there are more read compare points to test for. If so, the process loops back to step 708 and another iteration of steps 708-712 is performed. If all of the read compare points have been considered, then the device goes into standby mode in step 716.
  • step 718 the system determines the data stored in the selected memory cells. If the memory cell is a binary cell and the memory cell turned on, then it is assumed that the memory cell is an erased state. If the memory cell did not turn on, then the memory cell is in the program state. If the memory cell is a multi-state memory cell, then the system will determine the data stored in the memory cell based on whether the memory cell turned on or off in response to the various read compare points, as described above. The data determined in step 718 is reported in step 720. In one embodiment, the data could be reported to the state machine, the controller or the host.
  • Figure 12 is a timing diagram depicting various signals during the process of Figure 11.
  • Figure 12 shows the standby phase, setup phase, pre- charge/discharge phases, recovery phase and subsequent standby phase.
  • the signals depicted include the control gate voltage (SGD) for the drain side select gate, the word line voltage for the unselected word lines (WL_unsel), the word line voltage for the selected word line (WL_sel), the control gate voltage for the source side select gate (SGS), the voltage on the bit line selected for programming (BL_sel), and the source line voltage (Source).
  • SGD control gate voltage
  • WL_unsel word line voltage for the unselected word lines
  • WL_sel word line voltage for the selected word line
  • SGS source side select gate
  • BL_sel bit line selected for programming
  • Source source line voltage
  • the first standby phase occurs prior to time t ⁇ , in which all the signals depicted are at Vss.
  • the setup phase starts at time t0 and continues until time t2.
  • the unselected word lines are raised to Vdd.
  • the pre- charge/discharge phase start at time t3 and continue to time Xl.
  • the unselected word lines are raised from Vdd to Vread and the selected word line is raised from Vss to Vcgr. Because of capacitive coupling between the unselected word lines and the selected word line, the voltage on the selected word line is initially raised above Vcgr.
  • the word line voltage on the selected word line settles down to Vcgr.
  • the selected bit line is pre charged.
  • the source side select gate is turned on by raising SGS to Vdd. This provides a path to dissipate the charge on the bit line. If the threshold voltage of the memory cell selected for reading is greater than Vcgr then the selected memory cell will not turn on and the bit line will not discharge, as depicted by signal line 812. If the threshold voltage in the memory cell selected for reading is below Vcgr then the memory cell selected for reading will turn on and the bit line voltage will dissipate, as depicted by curve 814.
  • the sense amplifier will determine whether the bit line has dissipated a sufficient amount. At time t6, the selected word line will be lowered to Vss and the unselected word lines will be lowered to Vdd.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Un procédé de lecture de données (comprenant la vérification pendant la programmation) à partir d'éléments de stockage non volatiles sélectionnés d'un groupe (p. ex. chaîne NAND) consiste à conserver une tension intermédiaire comme tension de commande d'un élément de stockage non volatile non sélectionné puis à modifier la tension de commande de l'élément de stockage non volatile non sélectionné d'une tension intermédiaire à une tension d'autorisation de lecture. La tension de commande de l'élément de stockage non volatile sélectionné est transformé d'une tension de réserve (qui est différente de la tension intermédiaire) en une tension de comparaison de lecture. Tandis que la grille de commande de l'élément de stockage non volatile sélectionné se trouve au niveau de la tension de lecture comparaison et que la grille de commande de l'élément de stockage non volatile non sélectionné est au niveau de la tension d'autorisation de lecture, l'état de l'élément de stockage non volatile sélectionné est détecté pour déterminer des informations relatives aux données stockées dans l'élément de stockage non volatile sélectionné.
EP06845066A 2005-12-16 2006-12-11 Procede de lecture de stockage non volatile avec controle efficace de lignes de mots non selectionnees Withdrawn EP1964129A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/305,588 US7545675B2 (en) 2005-12-16 2005-12-16 Reading non-volatile storage with efficient setup
US11/303,193 US7369437B2 (en) 2005-12-16 2005-12-16 System for reading non-volatile storage with efficient setup
PCT/US2006/046961 WO2007078611A1 (fr) 2005-12-16 2006-12-11 Procede de lecture de stockage non volatile avec controle efficace de lignes de mots non selectionnees

Publications (1)

Publication Number Publication Date
EP1964129A1 true EP1964129A1 (fr) 2008-09-03

Family

ID=37950913

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06845066A Withdrawn EP1964129A1 (fr) 2005-12-16 2006-12-11 Procede de lecture de stockage non volatile avec controle efficace de lignes de mots non selectionnees

Country Status (5)

Country Link
EP (1) EP1964129A1 (fr)
JP (1) JP4820879B2 (fr)
KR (1) KR101007371B1 (fr)
TW (2) TWI334142B (fr)
WO (1) WO2007078611A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010129125A (ja) * 2008-11-27 2010-06-10 Toshiba Corp 多値不揮発性半導体メモリ
WO2021092830A1 (fr) 2019-11-14 2021-05-20 Yangtze Memory Technologies Co., Ltd. Dispositif de mémoire capable de réduire une perturbation de programme et procédé d'effacement coorespondant

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11224491A (ja) * 1997-12-03 1999-08-17 Sony Corp 不揮発性半導体記憶装置およびそれを用いたｉｃメモリカード
KR100562506B1 (ko) * 2003-12-01 2006-03-21 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
JP4157065B2 (ja) * 2004-03-29 2008-09-24 株式会社東芝 半導体記憶装置
JP4791812B2 (ja) * 2005-12-07 2011-10-12 株式会社東芝 不揮発性半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007078611A1 *

Also Published As

Publication number Publication date
JP2009520310A (ja) 2009-05-21
WO2007078611A1 (fr) 2007-07-12
TW200737204A (en) 2007-10-01
TW201027538A (en) 2010-07-16
KR101007371B1 (ko) 2011-01-13
KR20080089401A (ko) 2008-10-06
JP4820879B2 (ja) 2011-11-24
TWI334142B (en) 2010-12-01

Similar Documents

Publication Publication Date Title
EP1812932B1 (fr) Systeme de programmation a grande vitesse a surprogrammation reduite
EP1886319B1 (fr) Decalage de tension de programmation de depart avec utilisation cyclique de memoire non volatile
EP1759393B1 (fr) Programmation concurrente de memoire non volatile
US7733701B2 (en) Reading non-volatile storage with efficient setup
WO2016081064A1 (fr) Amplification non-et utilisant une rampe dynamique de tensions de lignes de mots
CN108428466B (zh) 用于抑制第一读取问题的字线的顺序取消选择
US7369437B2 (en) System for reading non-volatile storage with efficient setup
WO2007078793A1 (fr) Procede pour la programmation de memoire non volatile avec perturbation de programme reduite au moyen de tensions de passage modifiees
KR20090007297A (ko) 다른 전압들을 이용한 비휘발성 저장 장치에 대한 검증 동작
KR100984563B1 (ko) 프로그램 혼란이 감소된 ｎａｎｄ 타입 비휘발성 메모리의최종-최초 모드 및 프로그래밍 방법
KR101130332B1 (ko) 비휘발성 메모리에 대한 최상위 다중-레벨 상태의 고속 프로그래밍
EP1946324B1 (fr) Procede de programmation commandee de memoire non volatile presentant un couplage de canaux bit
EP2256748B1 (fr) Réduction de perturbations de lecture pour stockage non volatile
WO2005112036A1 (fr) Approche dirigée par bitune pour un contrôle de programme d’une mémoire non volatile
JP4820879B2 (ja) 非選択ワード線を効果的に制御して不揮発性メモリを読み出す方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080630

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20091005

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SANDISK TECHNOLOGIES INC.

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20140701